DETAILED ACTION
Claims 1-25 are pending.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/14/2026 has been entered.
The office acknowledges the following papers:
Claims and remarks filed on 5/14/2026,
Oath filed on 5/18/2026.
New Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (U.S. 2016/0283245), in view of Tanaka et al. (U.S. 5,086,498), in view of Official Notice.
As per claim 1:
Ben-Kiki disclosed an apparatus comprising:
decoder circuitry to decode an instance of a single instruction (Ben-Kiki: Figures 1 and 7 elements 106-108 and 706-708, paragraphs 31 and 56), the single instruction to include fields for an opcode (Ben-Kiki: Figures 1 and 4 elements 106 and 406, paragraphs 35 and 44), one or more fields to indicate a first source operand to provide an instruction pointer, one or more fields to indicate a second source operand to provide a second pointer, one or more fields to indicate a third source operand to provide a count value (Ben-Kiki: Figures 1-2 elements 106 and 206, paragraphs 31 and 37-38)(The user-level fork instruction includes source registers to store memory addresses that are transferred to program counter registers of a given helper thread. Additionally, the user-level fork instruction indicates a count number of allocated PEs for helper threads. Lastly, official notice is given that information explicitly indicated within instruction encoding as immediate data can be provided within source operands for the advantage of using more bits for instruction use. Thus, it would have been obvious to one of ordinary skill in the art to implement the count number within a third source register.), wherein the opcode is to indicate an entry into a microthread execution (Ben-Kiki: Figures 1-2 and 4 elements 106, 236, 406, and 436, paragraphs 31, 35, 38, 44, and 56-57)(Execution of the user-level fork instruction spawns a set of helper threads that start execution (i.e. microthread execution).);
execution circuitry to execute the decoded instruction according to the opcode to enter into microthread execution using data from the source operands (Ben-Kiki: Figures 6-7 elements 664, 674-675, 677, and 710, paragraphs 49, 51, and 56-57)(The user-level fork instruction includes source register(s) to store memory addresses that are transferred to program counter registers of a given helper thread. Execution of the user-level fork instruction spawns a set of helper threads that start execution (i.e. microthread execution).).
Ben-Kiki failed to teach a register to store an indication of location of a save state area to be used for a microthread, wherein each microthread is to share at least one control register with a host thread and has a register state independent of other microthreads, the register state to at least include general purpose registers, vector registers, and a register to store condition code values.
However, Tanaka combined with Ben-Kiki disclosed a register to store an indication of location of a save state area to be used for a microthread (Tanaka: Figure 4 elements 117, 120, and 130, column 9 lines 61-68 continued to column 10 lines 1-44)( Ben-Kiki: Figure 7 elements 714-1-N, 784, and 787-1-N, paragraphs 31, 37-38, 57 and 59-60)(Tanaka disclosed processing elements with general purpose, vector, and condition code registers. Ben-Kiki disclosed execution of the user-level fork instruction involves copying some/all of the architectural state to an architectural state location. The combination implements the additional PEs of Ben-Kiki with general purpose, vector, and condition code registers. The combination results in copying architectural state of general purpose, vector, and condition code registers to the additional PEs, but not copying the status register data. The first source register that provides a start instruction address for a first additional PE implicitly indicates the first additional PE as the location for storing copied architectural state data.), wherein each microthread is to share at least one control register with a host thread and has a register state independent of other microthreads, the register state to at least include general purpose registers, vector registers, and a register to store condition code values (Tanaka: Figure 4 elements 117, 120, and 130, column 9 lines 61-68 continued to column 10 lines 1-44)(Ben-Kiki: Figure 7 elements 714-1-N, 784, and 787-1-N, paragraphs 57 and 59-60)(Tanaka disclosed processing elements with general purpose, vector, and condition code registers. Ben-Kiki disclosed execution of the user-level fork instruction involves copying some/all of the architectural state to an architectural state location. The combination implements the additional PEs of Ben-Kiki with general purpose, vector, and condition code registers. The combination results in copying architectural state of general purpose, vector, and condition code registers to the additional PEs, but not copying the status register data. Each additional PE in Ben-Kiki has independent register states.).
The advantage of implementing PEs with their own corresponding register state storage is that architectural state data can be accessed more quickly as compared to the storage location of the additional PEs of Ben-Kiki. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the PE register storage system of Tanaka within the additional PEs of Ben-Kiki for the above advantage.
As per claim 2:
Ben-Kiki and Tanaka disclosed the apparatus of claim 1, wherein the one or more fields to indicate a source operand is to identify a register (Ben-Kiki: Figures 1-2 elements 106 and 206, paragraphs 31 and 37-38)(The user-level fork instruction includes source register(s) to store memory addresses that are transferred to program counter registers of a given helper thread.).
As per claim 3:
Ben-Kiki and Tanaka disclosed the apparatus of claim 1, wherein microthread execution is to start at the instruction pointer of the first source operand (Ben-Kiki: Figures 1-2 elements 106 and 206, paragraphs 31 and 37-38)(The user-level fork instruction includes source register(s) to store memory addresses that are transferred to program counter registers of a given helper thread. Execution of the helper threads on the PEs starts at the program counter value.).
As per claim 4:
Ben-Kiki and Tanaka disclosed the apparatus of claim 1, wherein the second pointer is a global pointer that is readable by a host process and microthreads (Ben-Kiki: Figures 1-2 elements 106 and 206, paragraphs 31 and 37-38)(The claim limitation further limits one of the Markush limitations. Ben-Kiki still reads upon the claim via the user-level fork instruction including source register(s) to store memory addresses that are transferred to program counter registers of a given helper thread.).
As per claim 5:
Ben-Kiki and Tanaka disclosed the apparatus of claim 1, wherein the execution circuitry is further to determine that a save state area is configured for the microthread execution (Ben-Kiki: Figure 7 elements 714-1-N and 787-1-N, paragraphs 57 and 59).
As per claim 6:
Ben-Kiki and Tanaka disclosed the apparatus of claim 1, wherein the count value is a value of desired microthreads and execution circuitry is to utilize the count to determine whether the apparatus supports the count value of desired microthreads (Ben-Kiki: Figures 1-2 elements 106 and 206, paragraphs 31 and 37-38)(The claim limitation further limits one of the Markush limitations. Ben-Kiki still reads upon the claim via the user-level fork instruction including source register(s) to store memory addresses that are transferred to program counter registers of a given helper thread.).
As per claim 7:
Ben-Kiki and Tanaka disclosed the apparatus of claim 6, wherein a number of supportable microthreads is to be stored by the apparatus (Ben-Kiki: Figures 1-2 and 7 elements 114-1-N and 236-1-N, paragraphs 31, 35, 38, and 59)(The PEs execute the helper threads spawned from the user-level fork instruction. Each PE stores a thread program counter and architectural state.).
As per claim 8:
Ben-Kiki and Tanaka disclosed the apparatus of claim 1, wherein the execution circuitry is further to set an indication of microthread execution (Ben-Kiki: Figures 1-2 and 7 elements 114-1-N and 236-1-N, paragraphs 31, 35, 38, and 59)(The PEs execute the helper threads spawned from the user-level fork instruction. Each PE stores a thread program counter and architectural state. Writes to the program counter and architectural state indicate helper thread execution.).
As per claim 9:
Ben-Kiki and Tanaka disclosed the apparatus of claim 1, wherein the apparatus is a processor core (Ben-Kiki: Figures 1 and 9 elements 100-102 and 990, paragraphs 27 and 77).
As per claim 10:
Ben-Kiki and Tanaka disclosed the apparatus of claim 1, wherein the apparatus is an accelerator (Ben-Kiki: Figures 1 and 9 elements 100-102 and 990, paragraphs 25, 27 and 77).
As per claim 11:
Claim 11 essentially recites the same limitations of claim 1. Claim 11 additionally recites the following limitations:
a memory to store an instance of a single instruction (Ben-Kiki: Figures 1 and 9 elements 106 and 934, paragraphs 31 and 78).
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 2. Therefore, claim 12 is rejected for the same reason(s) as claim 2.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 3. Therefore, claim 13 is rejected for the same reason(s) as claim 3.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 4. Therefore, claim 14 is rejected for the same reason(s) as claim 4.
As per claim 15:
The additional limitation(s) of claim 15 basically recite the additional limitation(s) of claim 5. Therefore, claim 15 is rejected for the same reason(s) as claim 5.
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 6. Therefore, claim 16 is rejected for the same reason(s) as claim 6.
As per claim 17:
The additional limitation(s) of claim 17 basically recite the additional limitation(s) of claim 7. Therefore, claim 17 is rejected for the same reason(s) as claim 7.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 8. Therefore, claim 18 is rejected for the same reason(s) as claim 8.
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 9. Therefore, claim 19 is rejected for the same reason(s) as claim 9.
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 10. Therefore, claim 20 is rejected for the same reason(s) as claim 10.
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (U.S. 2016/0283245), in view of Ireton (U.S. 5,826,089), in view of Official Notice.
As per claim 21:
Ben-Kiki disclosed a method comprising:
the single instruction to include fields for an opcode (Ben-Kiki: Figures 1 and 4 elements 106 and 406, paragraphs 35 and 44), one or more fields to indicate a first source operand to provide an instruction pointer, one or more fields to indicate a second source operand to provide a second pointer, one or more fields to indicate a third source operand to provide a count value (Ben-Kiki: Figures 1-2 elements 106 and 206, paragraphs 31 and 37-38)(The user-level fork instruction includes source registers to store memory addresses that are transferred to program counter registers of a given helper thread. Additionally, the user-level fork instruction indicates a count number of allocated PEs for helper threads. Lastly, official notice is given that information explicitly indicated within instruction encoding as immediate data can be provided within source operands for the advantage of using more bits for instruction use. Thus, it would have been obvious to one of ordinary skill in the art to implement the count number within a third source register.), wherein the opcode is to indicate an entry into a microthread execution (Ben-Kiki: Figures 1-2 and 4 elements 106, 236, 406, and 436, paragraphs 31, 35, 38, 44, and 56-57)(Execution of the user-level fork instruction spawns a set of helper threads that start execution (i.e. microthread execution).);
decoding the one or more instructions of the second instruction set (Ben-Kiki: Figures 1 and 7 elements 106-108 and 706-708, paragraphs 31 and 56); and
executing the decoded instruction according to the opcode to enter into microthread execution using data from the source operands (Ben-Kiki: Figures 6-7 elements 664, 674-675, 677, and 710, paragraphs 49, 51, and 56-57)(The user-level fork instruction includes source register(s) to store memory addresses that are transferred to program counter registers of a given helper thread. Execution of the user-level fork instruction spawns a set of helper threads that start execution (i.e. microthread execution).).
Ben-Kiki failed to teach translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set.
However, Ireton combined with Ben-Kiki disclosed translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set (Ireton: Figure 1 element 14, column 4 lines 7-63)(Ben-Kiki: Figure 1 element 100, paragraph 25)(Ireton disclosed an instruction translation unit to translate non-native instructions to native instructions for execution on the execution core. The combination implements the translation unit of Ireton within the processor of Ben-Kiki.).
The advantage of implementing an instruction translation unit within a processor is that it allows for execution of non-native applications. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the instruction translation unit of Ireton within the processor of Ben-Kiki for the above advantage.
As per claim 22:
The additional limitation(s) of claim 22 basically recite the additional limitation(s) of claim 2. Therefore, claim 22 is rejected for the same reason(s) as claim 2.
As per claim 23:
The additional limitation(s) of claim 23 basically recite the additional limitation(s) of claim 3. Therefore, claim 23 is rejected for the same reason(s) as claim 3.
As per claim 24:
The additional limitation(s) of claim 24 basically recite the additional limitation(s) of claim 4. Therefore, claim 24 is rejected for the same reason(s) as claim 4.
As per claim 25:
The additional limitation(s) of claim 25 basically recite the additional limitation(s) of claim 5. Therefore, claim 25 is rejected for the same reason(s) as claim 5.
Response to Arguments
The arguments presented by Applicant in the response, received on 5/14/2026 are partially considered persuasive.
Applicant argues regarding claims 1 and 11:
“For example, Ben-Kiki, as cited, does not appear to at least describe "decoder circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, one or more fields to indicate a first source operand to provide an instruction pointer, one or more fields to indicate a second source operand to provide a second pointer, one or more fields to indicate a third source operand to provide a count value, wherein the opcode is to indicate an entry into a microthread execution." The Office Action has not shown Ben-Kiki as having the three source operands.
For example, Ben-Kiki, as cited, does not appear to at least describe "a register to store an indication of location of a save state area to be used for a microthread, wherein each microthread is to share at least one control register with a host thread and has a register state independent of other microthreads, the register state to at least include general purpose registers, vector registers, and a register to store condition code values." Ben-Kiki, as cited, does not appear to describe threads that have their own register state and share at least one control register with a host thread.”
This argument is found to be persuasive for the following reason. The examiner agrees that Ben-Kiki failed to teach the newly claimed limitation. However, a new ground of rejection has been given due to the amendment.
Applicant argues for claim 21:
“For example, Ben-Kiki, as cited, does not appear to at least describe "translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set, the single instruction to include fields for an opcode, and one or more of: one or more fields to indicate a first source operand to provide an instruction pointer, one or more fields to indicate a second source operand to provide a second pointer, one or more fields to indicate a third source operand to provide a count value, wherein the opcode is to indicate an entry into a microthread execution." The Office Action has not shown Ben-Kiki as having the three source operands.”
This argument is not found to be persuasive for the following reason. Ben-Kiki allows for the count number to be explicitly specified by the user instruction, which reads upon the claimed “one or more fields”. Additionally, an official notice rejection has been given that immediate data within instruction encodings can also be provided within source registers. Thus, also reading upon the claimed limitation.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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