DETAILED ACTION
Claims 1-9, 11-19, and 21-26 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figs. 32-33 and the replacement drawings, filed August 28 2025, are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. When zooming into the drawings, pixelation on the words can be seen. Pixelation is a sign that the words were typed in a color other than black.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
[00320]: Insert “computing” after second instance of “(throughput)”.
[00330]: The phrase “a register maps” is grammatically incorrect and should be changed to “a register map”.
[00398]: The example embodiments suffer the same issues related to previous claim objections/rejections and current claim objections/rejections. Applicant is advised to fix these issues when appropriate.
Appropriate correction is required.
Claim Objections
Claims 3-24 are objected to because of the following informalities:
In claim 3, line 2, “is” should be inserted before the phrase “to be inactive”
In claim 4, line 1, add “status” before “indication” for clearer antecedent basis.
Claim 6 was written in a way that comprises a step per se, but apparatus claims do not comprise of steps. The claim should be rewritten such that it comprises a component to perform a step.
In claim 13, line 2, “is” should be inserted before the phrase “to be inactive”
In claim 14, line 1, add “status” before “indication” for clearer antecedent basis.
Claim 16 was written in a way that comprises a step per se, but system claims do not comprise of steps. The claim should be rewritten such that it comprises a component to perform a step.
In claim 21, line 7, change the phrase “the decoded instruction” to “the decoded one or more instructions” for clearer antecedent basis.
In claim 21, line 7, an “and” is missing at the end of the line and should be added.
In claim 23, line 2, “is” should be inserted before the phrase “to be inactive”
In claim 24, line 1, add “status” before “indication” for clearer antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-8, 12-18, and 22-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “the exit” in line 1. It’s unclear whether “the exit” refers to the first instance or second instance of “exit” in claim 1. For the sake of examination, Examiner is interpreting the second instance as “the exit.”
Claims 12 and 22 are rejected for the same reasons above.
Claims 3-4, 13-14, and 23-24 are rejected for inheriting the rejection of claims 2, 12, and 22, respectively.
Claim 5 recites the limitation “the exit” in line 1. It’s unclear whether “the exit” refers to the first instance or second instance of “exit” in claim 1. For the sake of examination, examiner is interpreting the second instance as “the exit.”
Claims 15 and 25 are rejected for the same reasons above.
Claims 6-8 and 16-18 are rejected for inheriting the rejection of claims 5 and 15, respectively.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 9, 11, and 19 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8, 8, 18, and 18 of copending Application No. 17/712130 (Using amended claims filed August 27 2025).
Claims 2-8 and 12-18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8, 8, 8, 8, 8, 8, 8, 18, 18, 18, 18, 18, 18, and 18 of copending Application No. 17/712130 in view of Arndt et al. (US 20120072707 A1).
Claims 21-26 of the Instant Application are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8, 8, 8, 8, 8, and 8 of copending Application No. 17/712130 (hereinafter Reference Application) in view of Sasanka (US 20140181479 A1) and Arndt et al. (US 20120072707 A1).
Regarding claim 1, the Reference Application teaches an apparatus comprising:
decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode (see Claim 8, specifically the limitations of Claim 1), wherein the opcode is to indicate execution circuitry is to exit from microthread execution (Claims 8: The exit instruction must have an opcode to indicate the type of instruction), wherein a microthread is not scheduled by an operating system and has its own microthread state save area (see Claim 8, specifically the limitations of Claim 1);
execution circuitry to execute the decoded instruction according to the opcode to exit from microthread execution (see Claim 8, specifically the limitations of Claim 1).
Regarding claim 2, although the Reference application teaches the apparatus of claim 1, it does not teach that the exit from microthread execution is for a single microthread.
Arndt teaches the exit from microthread execution is for a single microthread (Fig. 8 and [0071]: “When bit 20 signifies terminating a particular assist hardware thread, bits 6-10 include a source register (RS) location (e.g., general-purpose register location) that includes an assist thread number (ATN) corresponding to the assist hardware thread for which to terminate”).
It would have been obvious to one of ordinary skill in the art to combine the teachings of claim 8 of the Reference Application with the teachings of Arndt to exit microthread execution for a single microthread to stop the execution of a microthread by signaling an end in execution to avoid unnecessary resource usage.
Regarding claim 3, the Reference Application, in view of Arndt, teaches the apparatus of claim 2, wherein the execution circuitry is to further update an active status indication that the single microthread to be inactive (see Claim 8, specifically the limitations of claim 2).
Regarding claim 4, the Reference Application, in view of Arndt, teaches the apparatus of claim 3, wherein the active indication is to be stored in a bitvector, wherein individual bits of the bitvector are to be used to indicate an active status of microthreads (see Claims 8, specifically the limitation of claim 2).
Regarding claim 5, although the Reference Application teaches the apparatus of claim 1, it does not teach that the exit from microthread execution is for all microthreads and a return to a previous threaded mode
Arndt teaches the exit from microthread execution is for all microthreads and a return to a previous threaded mode (Figs. 5 and 8, [0071]: If the termination bit of the SAT instruction 800 is set to 0, all assist hardware threads terminate and exit from execution, and returns to singular thread mode (i.e., the mode prior to executing the create assist thread instructions). Assist hardware threads as microthreads).
It would have been obvious to one of ordinary skill in the art to combine the teachings of claim 8 of the Reference Application with the teachings of Arndt to have the instruction exit all microthreads from executing. One of ordinary skill would appreciate the control over all instructions as it can be seen as efficient to have one instruction exit execution of all microthreads instead of one exit instruction for each microthread.
Regarding claim 6, Although the Reference Application in view of Arndt teaches the apparatus of claim 5 of the Examining Application, the current combination does not teach clearing an indication of a microthread execution mode.
However, Arndt does also teach clearing an indication of a microthread execution mode (Figs. 2 and 5, [0044]: When no more assist threads are executing, the assist thread executing (ATE) 230 bit is cleared).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of claim 8 of the Reference Application with the teachings of Arndt to clear an indication of microthread execution mode. One of ordinary skill would appreciate a signal or indicator that the apparatus is or is not in a certain mode as it would allow for easier debugging, such as knowing whether it’s the cause of the microthreads or not.
Regarding claim 7, the Reference Application, in view of Arndt, teaches the apparatus of claim 6, wherein the indication is a zero flag in a flags register (Arndt, Fig. 2 and [0044]: The ATE bit 230 is set to “0” when no assist threads are executing (hence, considered to be the zero flag). The ATE bit is located within a status register known as the ATSR 130. Since the ATSR contains flags, it will be considered as a flags register).
Regarding claim 8, the Reference Application, in view of Arndt, teaches the apparatus of claim 7, wherein the flags register is accessible outside of the microthread execution mode (Arndt, Figs. 1 and 2, [0044]: ATE bit 230 may be read by software program 110, meaning that the processor 100 can access the register regardless of whether the initiating hardware thread is utilizing assist hardware threads or not).
Regarding claim 9, the Reference Application teaches the apparatus of claim 1, wherein the apparatus is an accelerator (Claim 8: the independent limitation of the Reference application teaches multiple active microthreads. Since there are multiple active microthreads, the apparatus must be accelerating execution using the microthreads. Therefore, the apparatus is an accelerator).
Regarding claim 11, the claim is rejected for the same reasons as claim 1, using claim 18 of the Reference Application
Regarding claim 12, although the Reference application teaches the system of claim 11, it does not teach that the exit from microthread execution is for a single microthread.
Arndt teaches the exit from microthread execution is for a single microthread (Fig. 8 and [0071]: “When bit 20 signifies terminating a particular assist hardware thread, bits 6-10 include a source register (RS) location (e.g., general-purpose register location) that includes an assist thread number (ATN) corresponding to the assist hardware thread for which to terminate”).
It would have been obvious to one of ordinary skill in the art to combine the teachings of claim 18 of the Reference Application with the teachings of Arndt to exit microthread execution for a single microthread to stop the execution of a microthread by signaling an end in execution to avoid unnecessary resource usage.
Regarding claim 13, the Reference Application, in view of Arndt, teaches the system of claim 12, wherein the execution circuitry is to further update an active status indication that the single microthread to be inactive (see Claim 18, specifically the limitations of claim 12).
Regarding claim 14, the Reference Application, in view of Arndt, teaches the system of claim 13, wherein the active indication is to be stored in a bitvector, wherein individual bits of the bitvector are to be used to indicate an active status of microthreads (see Claims 18, specifically the limitation of claim 12).
Regarding claim 15, although the Reference Application teaches the system of claim 11, it does not teach that the exit from microthread execution is for all microthreads and a return to a previous threaded mode
Arndt teaches the exit from microthread execution is for all microthreads and a return to a previous threaded mode (Figs. 5 and 8, [0071]: If the termination bit of the SAT instruction 800 is set to 0, all assist hardware threads terminate and exit from execution, and returns to singular thread mode (i.e., the mode prior to executing the create assist thread instructions). Assist hardware threads as microthreads).
It would have been obvious to one of ordinary skill in the art to combine the teachings of claim 18 of the Reference Application with the teachings of Arndt to have the instruction exit all microthreads from executing. One of ordinary skill would appreciate the control over all instructions as it can be seen as efficient to have one instruction exit execution of all microthreads instead of one exit instruction for each microthread.
Regarding claim 16, Although the Reference Application in view of Arndt teaches the system of claim 15 of the Examining Application, the current combination does not teach clearing an indication of a microthread execution mode.
However, Arndt does also teach clearing an indication of a microthread execution mode (Figs. 2 and 5, [0044]: When no more assist threads are executing, the assist thread executing (ATE) 230 bit is cleared).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of claim 18 of the Reference Application with the teachings of Arndt to clear an indication of microthread execution mode. One of ordinary skill would appreciate a signal or indicator that the apparatus is or is not in a certain mode as it would allow for easier debugging, such as knowing whether it’s the cause of the microthreads or not.
Regarding claim 17, the Reference Application, in view of Arndt, teaches the system of claim 16, wherein the indication is a zero flag in a flags register (Arndt, Fig. 2 and [0044]: The ATE bit 230 is set to “0” when no assist threads are executing (hence, considered to be the zero flag). The ATE bit is located within a status register known as the ATSR 130. Since the ATSR contains flags, it will be considered as a flags register).
Regarding claim 18, the Reference Application, in view of Arndt, teaches the system of claim 17, wherein the flags register is accessible outside of the microthread execution mode (Arndt, Figs. 1 and 2, [0044]: ATE bit 230 may be read by software program 110, meaning that the processor 100 can access the register regardless of whether the initiating hardware thread is utilizing assist hardware threads or not).
Regarding claim 19, the Reference Application teaches the system of claim 1, wherein the apparatus is an accelerator (Claim 18: the independent limitation of the Reference application teaches multiple active microthreads. Since there are multiple active microthreads, the apparatus must be accelerating execution using the microthreads. Therefore, the apparatus is an accelerator).
Regarding claim 21, the claim is mostly rejected for the same reasons as claim 1.
Claim 8 of the Reference Application does not teach translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set.
Sasanka does teach translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set (see Fig. 13 and [0120]).
It would have been obvious to one of ordinary skill in the art to have modified claim 8 of the Reference Application to incorporate the teachings of Sasanka to provide a way to translate an instance of a single instruction from a first instruction set to one or more instructions of a second instruction set architecture to then be sent to the processor. A common motivation for translating an instruction from a first instruction set to a second instruction set is that it allows one of ordinary skill in the art to create a simpler design based on the second instruction set. This simpler design would allow easier implementation of the hardware (e.g., a simpler decoder), would require less time to verify and debug the hardware, and an improvement in performance. In addition, it would allow the processor to accommodate non-native instructions to increase flexibility.
Regarding claim 22, although the Reference application, in view of Sasanka, teaches the method of claim 21, it does not teach that the exit from microthread execution is for a single microthread.
Arndt teaches the exit from microthread execution is for a single microthread (Fig. 8 and [0071]: “When bit 20 signifies terminating a particular assist hardware thread, bits 6-10 include a source register (RS) location (e.g., general-purpose register location) that includes an assist thread number (ATN) corresponding to the assist hardware thread for which to terminate”).
It would have been obvious to one of ordinary skill in the art to combine the teachings of claim 18 of the Reference Application with the teachings of Arndt to exit microthread execution for a single microthread to stop the execution of a microthread by signaling an end in execution to avoid unnecessary resource usage.
Regarding claim 23, the Reference Application, in view of Sasanka and Arndt, teaches the method of claim 22, wherein the execution circuitry is to further update an active status indication that the single microthread to be inactive (see Claim 8, specifically the limitations of claim 2).
Regarding claim 24, the Reference Application, in view of Sasanka and Arndt, teaches the method of claim 23, wherein the active indication is to be stored in a bitvector, wherein individual bits of the bitvector are to be used to indicate an active status of microthreads (see Claims 8, specifically the limitation of claim 2).
Regarding claim 25, although the Reference Application, in view of Sasanka, teaches the method of claim 21, it does not teach that the exit from microthread execution is for all microthreads and a return to a previous threaded mode
Arndt teaches the exit from microthread execution is for all microthreads and a return to a previous threaded mode (Figs. 5 and 8, [0071]: If the termination bit of the SAT instruction 800 is set to 0, all assist hardware threads terminate and exit from execution, and returns to singular thread mode (i.e., the mode prior to executing the create assist thread instructions). Assist hardware threads as microthreads).
It would have been obvious to one of ordinary skill in the art to combine the teachings of claim 8 of the Reference Application with the teachings of Arndt to have the instruction exit all microthreads from executing. One of ordinary skill would appreciate the control over all instructions as it can be seen as efficient to have one instruction exit execution of all microthreads instead of one exit instruction for each microthread.
Regarding claim 26, although the Reference Application, in view of Sasanka, teaches the method of claim 21, they do not teach clearing an indication of a microthread execution mode.
However, Arndt teaches clearing an indication of a microthread execution mode (Figs. 2 and 5, [0044]: When no more assist threads are executing, the assist thread executing (ATE) 230 bit is cleared).
It would have been obvious to one of ordinary skill in the art to combine the teachings of claim 8 of the Reference Application with the teachings of Arndt to clear an indication of microthread execution mode. One of ordinary skill would appreciate a signal or indicator that the apparatus is or is not in a certain mode as it would allow for easier debugging, such as knowing whether it’s the cause of the microthreads or not.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 and 11-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arndt et al. (US 20120072707 A1) in view of Joao et al. (US 20180276046 A1).
Regarding claim 1, Arndt teaches an apparatus (Fig. 1: Processor 100) comprising:
decoder circuitry to decode an instance of a single instruction (Fig. 1: Processor 100 must contain a decoder to execute the instructions mentioned in the specification), the single instruction to include a field for an opcode (Fig. 8 and [0071]: Stop Assist Thread (SAT) instruction 800 has opcode field from bits 0-5), wherein the opcode is to indicate execution circuitry is to exit from microthread execution ([0070-0071]: The SAT instruction may indicate that an assist thread is to stop executing. Assist threads as microthreads), wherein a microthread (Figs. 1 and 9, [0035]: Each assist hardware thread 150 have their own respective assist hardware thread registers 170. Assist hardware thread registers as the microthread state save area); and
execution circuitry to execute the decoded instruction according to the opcode to exit from microthread execution (Fig. 1 and [0035]: Initiating hardware thread 120 has an execution unit to execute instructions).
Arndt does not teach that each microthread is not scheduled by an operating system.
Note that Software Program in Arndt (as seen in Fig. 1, 110 and referenced in [0033]) can be interpreted as an operating system (see Wikipedia “Operating System”, Paragraph 1, in pertinent art section). The software program schedules instructions to either the assist thread or initiating thread (Arndt, see Fig. 1 and [0033, 0037]).
Joao teaches that thread scheduling is done by a hardware thread scheduler, not by the operating system (Figs. 1 and 5, [0050, 0054]: The operating system sends a request for a number of threads to the hardware thread scheduler 42, and the hardware thread scheduler checks performance metrics before deciding the number of threads to be scheduled).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Arndt with the teachings of Joao to have scheduled threads by use a thread scheduler instead of scheduling threads using the software program, i.e., the operating system. One of ordinary skill would appreciate offloading thread scheduling to a component that’s proficient in scheduling threads as thread schedulers such as the one mentioned in Joao can analyze current hardware utilization and decide how many threads should be scheduled (see Joao, [0055]), whereas the operating system may not have the capability to do so.
Regarding claim 2, Arndt, in view of Joao, teaches the apparatus of claim 1, wherein the exit from microthread execution is for a single microthread (Fig. 8 and [0071]: “When bit 20 signifies terminating a particular assist hardware thread, bits 6-10 include a source register (RS) location (e.g., general-purpose register location) that includes an assist thread number (ATN) corresponding to the assist hardware thread for which to terminate”).
Regarding claim 3, Arndt, in view of Joao teaches the apparatus of claim 2, wherein the execution circuitry is to further update an active status indication that the single microthread to be inactive (Figs. 3B and 5, [0061]: The assist hardware thread changes its status in hardware status store 125 from "executing" to "terminated").
Regarding claim 4, Arndt teaches the apparatus of claim 3, wherein the active indication is to be stored in a bitvector, wherein individual bits of the (Fig. 3B and [0048]: The hardware status store 125 may be represented as a vector indicating a particular hardware status thread, each bit indicating a certain hardware thread status of “executing” or “terminated”).
Regarding claim 5, Arndt teaches the apparatus of claim 1, wherein the exit from microthread execution is for all microthreads and a return to a previous threaded mode (Figs. 5 and 8, [0071]: If the termination bit of the SAT instruction 800 is set to 0, all assist hardware threads terminate and exit from execution, and returns to singular thread mode (i.e., the mode prior to executing the create assist thread instructions)).
Regarding claim 6, Arndt teaches the apparatus of claim 5, further comprising: clearing an indication of a microthread execution mode (Figs. 2 and 5, [0044]: When no more assist threads are executing, the assist thread executing (ATE) 230 bit is cleared).
Regarding claim 7, Arndt teaches the apparatus of claim 6, wherein the indication is a zero flag in a flags register (Fig. 2 and [0044]: The ATE bit 230 is set to “0” when no assist threads are executing (hence, considered to be the zero flag). The ATE bit is located within a status register known as the ATSR 130. Since the ATSR contains flags, it will be considered as a flags register).
Regarding claim 8, Arndt teaches the apparatus of claim 7, wherein the flags register is accessible outside of the microthread execution mode (Figs. 1 and 2, [0044]: ATE bit 230 may be read by software program 110, meaning that the processor 100 can access the register regardless of whether the initiating hardware thread is utilizing assist hardware threads or not).
Regarding claim 9, Arndt teaches the apparatus of claim 1, wherein the apparatus is an accelerator ([0003]: The initiating hardware thread assigns code segments for assist hardware threads to execute simultaneously, which is considered to be accelerating execution through multithreading).
Regarding claims 11-19, Arndt teaches memory to store an instance of a single instruction (see [0026]), and recites a system which implements the apparatus according to claims 1-9, respectively, and are therefore rejected on the same premises.
Claim(s) 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arndt et al. (US 20120072707 A1) in view of Joao et al. (US 20180276046 A1) and Sasanka (US 20140181479 A1).
Regarding claim 21, although Arndt, in view of Joao, teaches most of the method similar to that of the apparatus according to claim 1, they do not teach translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set.
However, Sasanka does teach translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set (see Fig. 13 and [0120]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Arndt, in view of Joao, to incorporate the teachings of Sasanka to provide a way to translate an instance of a single instruction from a first instruction set to one or more instructions of a second instruction set architecture to then be sent to the processor. A common motivation for translating an instruction from a first instruction set to a second instruction set is that it allows one of ordinary skill in the art to create a simpler design based on the second instruction set. This simpler design would allow easier implementation of the hardware (e.g., a simpler decoder), would require less time to verify and debug the hardware, and an improvement in performance. In addition, it would allow the processor to accommodate non-native instructions to increase flexibility.
Regarding claims 22-26, Arndt, in view of Joao and Sasanka, recites a method which is similar to the apparatus of claims 2-6, and are therefore rejected on the same premises.
Response to Arguments/Amendments
Applicant’s amendments, filed August 28 2025, with respect to the specification objections raised by the Examiner have been addressed. However, Examiner raises new specification objections. See specification objections above.
Applicant’s amendments, filed August 28 2025, with respect to the drawing objections raised by the Examiner have been mostly addressed. Examiner maintains an objection on Figures 32 and 33 and an objection has been raised on the replacement drawings. See drawing objections above.
Applicant's arguments, See Page 8, lines 12-13, filed August 28 2025, with respect to the claim objections have been fully considered but they are not persuasive.
Regarding arguments on Page 8, lines 12-13, Applicant states that the claims are grammatically correct.
Examiner respectfully disagrees, the phrasing “to further update an active status indication that the single microthread to be inactive” affects the flow/readability of the claim and should either use Examiner’s suggestion, or change the phrasing of the claim. The phrasing “further comprising: clearing an indication of a microthread execute mode” is used improperly as it states a step, rather than an element doing the step. See Applicant’s claim 11 for the proper use of “comprising”.
The objections will be maintained until further explanation is provided as to why the claims are written with proper grammar or the claims are amended to address the issues raised. Additionally, new claim objections have been raised and requires Applicant’s attention.
Applicant's arguments, see Page 9, lines 9 to Page 10, line 2, filed August 28 2025, with respect to the rejection of claims 1-9, 11-19, and 22-25 under 35 U.S.C. 112(a)/(b) have been fully considered and are mostly persuasive.
Regarding arguments on Page 9, lines 20-21, Applicant argues that there are no two different “exits” in claim 1.
Examiner disagrees with this argument. See line 4 and line 8 of claim 1. All independent claims have two instances of “exit”.
Examiner will maintain the 112(b) rejections on claims 2, 5-8, 12, 15-18, 22 and 25, and will withdraw all other 112(a)/(b) rejections. Examiner raises new 112(b) issues due to adjusted claim dependencies.
Applicant’s arguments, see Page 10, line 4 to Page 11, line 3, filed August 28 2025, with respect to the rejection(s) of claims 1-9 and 11-19 under 35 U.S.C. 102(a)(1) have been fully considered but they are not persuasive.
Regarding Applicant’s arguments on page 10, lines 17-20, Applicant argues that the hardware threads of Arndt do not have their own state save area. Refer to Figs. 1 and 9 and paragraph [0035] of Arndt where they explain that when initiating the assist hardware thread, the initiating hardware thread copies register value from the initiating hardware thread registers to the assist hardware thread registers (as seen in Figs. 1 and 9). Therefore the initiating thread and assist threads each have their own thread registers, i.e., state save area. Applicant’s argument regarding that each hardware thread does not have its own state save area is considered not persuasive.
Despite Applicant’s arguments being not persuasive, the rejection has been withdrawn because of the added matter unrelated to what Applicant argued. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 over Arndt in view of Joao. See 103 rejections above.
Applicant’s arguments, see Page 11, line 5 to Page 12, line 6, filed August 28 2025, with respect to the rejection(s) of claims 10 and 20-26 under 35 U.S.C. 102(a)(1) have been fully considered and are mostly persuasive.
Regarding Applicant’s arguments on page 12, lines 1-4, Applicant argues that the hardware threads of Arndt do not have their own state save area.
See above for reasoning why argument is unpersuasive.
Despite Applicant’s arguments being unpersuasive, the rejection has been withdrawn because of the added matter unrelated to what Applicant argued. However, upon further consideration, a new ground(s) of rejection is made for claims 21-26 under 35 U.S.C. 103 over Arndt in view of Sasanka and Joao. See 103 rejections above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
“Operating System” by Wikipedia: Provides the definition of an operating system.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.A./Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183