DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figs. 32-33 and the replacement drawings, filed August 27 2025, are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. When zooming into the drawings, pixelation on the words can be seen. Pixelation is a sign that the words were typed in a color other than black.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
[00320]: Insert “computing” after second instance of “(throughput)”.
[00331]: The phrase “a register maps” is grammatically incorrect and should be changed to “a register map”.
[00398]: The example embodiments suffer the same issues related to previous claim objections/rejections and current claim objections/rejections. Applicant is advised to fix these issues when appropriate.
Appropriate correction is required.
Claim Objections
Claim 21 is objected to because of the following informalities:
Line 7: Change the phrase “the decoded instruction” to “the decoded one or more instructions” for clearer antecedent basis.
Line 7: An “and” is missing at the end of the line and should be added.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 5-6, 15-16, and 25-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the microthread state save area" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. There was no prior recitation of “a microthread state save area”, only a recitation of multiple “microthread state save area” in claim 1. For the sake of Examination, Examiner will interpret this limitation to be “a microthread state save area”.
Claims 6, 15-16, and 25-26 are rejected for the same reasons above.
Claim Rejections - 35 USC § 103
Claims 1-2, 4-9, 11-12, 14-19, 21-22, and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Arndt et al. (US 20120072707 A1) in view of Pearce et al. (US 20200104139 A1) and Joao et al. (US 20180276046 A1).
Regarding claim 1, Arndt teaches an apparatus (Fig. 1: Processor 100) comprising:
decoder circuitry to decode an instance of a single instruction (Fig. 1: Processor 100 must contain a decoder to execute the instructions mentioned in the specification), wherein each microthread (Figs. 1 and 9, [0035]: Each assist hardware thread 150 have their own respective assist hardware thread registers 170. Assist hardware thread registers as the microthread state save area); and
execution circuitry to execute the decoded instruction (Fig. 1 and [0035]: Initiating hardware thread 120 and assist hardware threads 150 all have an execution unit to execute instructions).
Arndt does not teach that the single instruction to include an opcode to indicate execution circuitry is to return an active number of microthread and that each microthread is not scheduled by an operating system
Pearce teaches an instruction that returns the active number of microthreads (Figs. 1A-1B and [0297]: Instruction TOCCUPANCY returns the number of active threads and follows the instruction structure as seen in Figs. 1A-1B, which includes an opcode field. Threads as microthreads)
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Arndt with the teachings of Pearce to have returned the number of active microthreads. One of ordinary skill would appreciate knowing how many microthreads are running as to understand the current hardware utilization or use as a debug tool to understand potential utilization issues.
Arndt, in view of Pearce, still does not teach that each microthread is not scheduled by an operating system.
Note that Software Program in Arndt (as seen in Fig. 1, 110 and referenced in [0033]) can be interpreted as an operating system (see Wikipedia “Operating System”, Paragraph 1, in pertinent art section). The software program schedules instructions to either the assist thread or initiating thread (Arndt, see Fig. 1 and [0033, 0037]).
Joao teaches that thread scheduling is done by a hardware thread scheduler, not by the operating system (Figs. 1 and 5, [0050, 0054]: The operating system sends a request for a number of threads to the hardware thread scheduler 42, and the hardware thread scheduler checks performance metrics before deciding the number of threads to be scheduled).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Arndt, in view of Pearce, with the teachings of Joao to have scheduled threads by use a thread scheduler instead of scheduling threads using the software program, i.e., the operating system. One of ordinary skill would appreciate offloading thread scheduling to a component that’s proficient in scheduling threads as thread schedulers such as the one mentioned in Joao can analyze current hardware utilization and decide how many threads should be scheduled (see Joao, [0055]), whereas the operating system may not have the capability to do so.
Regarding claim 2, Arndt, in view of Pearce and Joao, teaches the apparatus of claim 1, wherein the active number of microthreads are indicated by a bitvector with each microthread to have a bit position to indicate its active status (Arndt, Fig. 3B and [0048]: Hardware status store 125 contains the assist hardware thread status, which may be stored in a vector. The vector as the bitvector and assist hardware threads as microthreads).
Regarding claim 4, Arndt, in view of Pearce and Joao, teaches the apparatus of claim 2, wherein the bitvector is stored in a microthread state save area (Arndt, Fig. 6 and [0076]: Hardware status store 125 as the microthread state save area, different from the microthread state save area cited in claim 1).
Regarding claim 5, Arndt, in view of Pearce and Joao, teaches the apparatus of claim 2, wherein the microthread state save area is to store contents of general purpose registers used by each active microthread (Arndt, Fig. 9 and [0066]: Base registers in initiating/assist hardware thread registers as the general purpose registers).
Regarding claim 6, Arndt, in view of Pearce and Joao, teaches the apparatus of claim 2, wherein the microthread state save area is to store contents of vector registers used by each active microthread (Arndt, Fig. 9 and [0076]: Implementation-dependent set of registers in initiating/assist hardware thread registers may include vector registers).
Regarding claim 7, Arndt, in view of Pearce and Joao, teaches the apparatus of claim 2, wherein the bitvector is to be updated by microcode per microthread exit (Arndt, Fig. 5, [0025] and [0061]: At step 520, when the assist hardware thread (similar to microthreads of Pearce) exits execution, it will update the hardware status store 125, which is maintained as a vector. The vector may be updated by hardware or software (such as micro-code, where micro-code and microcode are the same thing)).
Regarding claim 8, Arndt, in view of Pearce and Joao, teaches the apparatus of claim 2, wherein a microthread exit is set by an execution of an instance of a microthread exit instruction (Arndt, Fig. 8 and [0059]: SAT instruction terminates the thread that executes the instruction (i.e., a thread exist occurs). SAT instruction as the microthread exit instruction).
Regarding claim 9, Arndt, in view of Pearce and Joao, teaches the apparatus of claim 1, wherein the apparatus is an accelerator (Arndt, Fig. 14: Each assist thread in processor 1400 is executing instruction, accelerating the processor throughput. Therefore, processor 1400 is an accelerator).
Regarding claims 11, Arndt, in view of Pearce and Joao teaches a system comprising (Fig. 17: Information Handling System 1700):
memory to store an instance of a single instruction (Fig. 17: System Memory 1720).
The rest of the claim recites a system similar to the apparatus of claim 1, therefore the claim is rejected on the same premises.
Regarding claims 12 and 14-19, the claims recite a system similar to the apparatus of claims 2 and 4-9, therefore the claims are rejected on the same premises.
Regarding claim 21, the claim is mostly rejected by Arndt, in view of Pearce and Joao. Arndt, in view of Pearce and Joao, does not currently teach translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set.
Pearce also teaches translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set (Pearce, Fig. 11 and [0148]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have further combined the teachings of Arndt, in current view of Pearce and Joao, with the teachings of Pearce to provide a way to translate an instance of a single instruction from a first instruction set to one or more instructions of a second instruction set architecture to then be sent to the processor. A common motivation for translating an instruction from a first instruction set to a second instruction set is that it allows one of ordinary skill in the art to create a simpler design based on the second instruction set. This simpler design would allow easier implementation of the hardware (e.g., a simpler decoder), would require less time to verify and debug the hardware, and an improvement in performance. In addition, it would allow the processor to accommodate non-native instructions to increase flexibility.
Regarding claims 22 and 24-26, the claims recite a method similar to the apparatus of claims 2 and 4-6, therefore the claims are rejected on the same premises.
Claim(s) 3, 13, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arndt et al. (US 20120072707 A1) in view of Pearce et al (US 20200104139 A1), Joao et al. (US 20180276046 A1), and Bolz et al. (US 9665958 B2).
Although Arndt, in view of Pearce and Joao, teaches the apparatus of claim 2, they do not teach wherein the execution circuitry is to perform a population count on the bitvector.
However, Bolz does teach the wherein the execution circuitry is to perform a population count on the bitvector (Col. 6, lines 36-41: The POPCount instruction counts the bits of the active mask to return a number of active threads. Since POPCount is an instruction, the execution circuitry is able to perform the operations related to POPCount. The mask to be interpreted as the bitvector).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Arndt, in view of Pearce and Joao, with the teachings of Bolz to implement the return active number of microthreads instruction as a POPCOUNT instruction to count the number of bits of the bitvector to generate a number of active threads. Popcount is known as one of the most effective ways to count the number of bits within a bus of bits. Other ways such as bitwise comparison is known to be slow and ineffective, especially for a system that focuses on high throughput such as the one taught in Arndt.
Regarding claim 13, the claim recites a system similar to the apparatus of claim 3, therefore the claim is rejected on the same premises.
Regarding claim 23, the claim recites a method similar to the apparatus of claim 3, therefore the claim is rejected on the same premises.
Claim(s) 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Arndt et al. (US 20120072707 A1) in view of Pearce et al (US 20200104139 A1), Joao et al. (US 20180276046 A1) and Barreh et al. (US 7383403 B1).
Regarding claim 10, although Arndt, in view of Pearce and Joao, teaches the apparatus of claim 1, they do not teach wherein the execution circuitry is to generate a fault when the apparatus is not in a microthreaded execution mode.
However, first note that microthreaded execution mode is being mapped to as the state before the initiating hardware thread creates an assist thread (Arndt, Fig. 4). This is a microthreaded execution mode because it refers to a mode where only the initial hardware thread is executing instructions and the assist hardware threads are inactive.
Here, Barreh teaches the execution circuitry is to generate a fault when the apparatus is not in a microthreaded execution mode (Col. 16, lines 17-20: In other words, when a thread experiences an exception while executing instructions, for example, the thread will redirect to the exception handler. The executing thread containing the execution circuitry and the exception as the fault).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Pearce with the teachings of Barreh to allow the execution circuit to generate a fault when not in microthreaded execution mode. Throwing a fault will guarantee that the processor won’t execute the instruction as to prevent undefined behavior from occurring as a result of executing an unknown instruction. In addition, the processor may log the fault somewhere so that it can be retrieved for later uses like debugging, which may be appreciated by one of ordinary skill.
Regarding claim 20, the claim recites a system similar to the apparatus of claim 10, therefore the claim is rejected on the same premises.
Response to Arguments/Amendments
Applicant’s amendments, filed August 27 2025, with respect to the drawing objections raised by the Examiner have been mostly addressed. Examiner maintains an objection on Figures 32 and 33 and an objection has been raised on the replacement drawings. See drawing objections above.
Applicant’s amendments, filed August 27 2025, with respect to the claim objections raised by the Examiner have been addressed. However, Examiner raises new claim objections. See claim objections above.
Applicant’s amendments, filed August 27 2025, with respect to claims 5-6, 15-16 and 25-26 rejected under 35 U.S.C. 112(b), have not been addressed. Although the amendments on claims 4, 14, and 24 that were rejected under 112(b) have been addressed, the amendments do not address the 112(b) issues in claims 5-6, 15-16, and 25-26 as there still exists a lack of antecedent basis in the claims. Therefore the 112(b) rejections on claims 4, 14, and 24 are withdrawn and the 112(b) rejections on claims 5-6, 15-16, and 25-26 are maintained.
Applicant's arguments, see Page 8, line 22 to Page 9, last line, filed August 27 2025, with respect to the rejection of claims 1-6, 9, 11-16, 19, and 20-26 under 35 U.S.C. 101 have been fully considered but they are not persuasive.
Regarding arguments on Page 8, lines 22 to Page 9, line 12, Applicant argues that the claimed subject matter does pass the Alice/Mayo analysis in determining eligible subject matter, even if the Examiner “improperly” asserted that the claims are directed to an abstract idea.
See MPEP 2106 regarding patent subject matter eligibility. The claim is directed to an abstract idea. When analyzing the subject matter in Step 2A, Prong 1, Examiner determined that the single instruction of “return[ing] the active number of microthreads” in which Applicant tried to claim is considered to be a mental process of decoding an instruction to indicate a mathematical process of counting and returning a number counted (see MPEP 2106.04(a)(2)(III)(C), Paragraphs 1-2 and 2106.04(a)(2)(I)(C)). As explained in the office action, the abstract idea was then implemented with elements that were recited at a high level of generality, which amount to no more than mere instructions to apply the judicial exception under Step 2A Prong Two and Step 2B (see MPEP 2106.05(f)(2), Paragraphs 1-2). In other words, the abstract idea was simply “applied” onto a computer, where the computer components are all recited at a high level. The application of the abstract idea raises the issue of non-patentable subject matter. Therefore, the remarks in response to patentable subject matter are considered not persuasive.
Regarding arguments on Page 9, lines 15-18, Applicant argues that claim 1, at least, is not directed towards “software per se”.
Within the 101 rejection, Examiner did not assert that the claims lean toward “software per se”. Examiner believes that Applicant is referring to the phrase “no more than mere instructions…”, which does not have anything to do with software or hardware instructions, but rather instructions to implement the abstract idea or to “apply it” (See MPEP 2106.05(f), Paragraph 1). Therefore, the remarks in response to how claim 1 was analyzed under the Alice/Mayo framework are considered not persuasive.
Regarding arguments on Page 9, lines 18-23, Applicant argues that if an instruction has “never existed”, then the circuitry for the instruction has “never existed”.
Examiner respectfully disagrees with this argument. Applicant doesn’t go into depth as to what makes their decoder and execution circuitry different from a “generic” decoder and execution circuitry as they recite the elements at a high level, which doesn’t integrate the judicial exception into a practical application (see MPEP 2106.05(f)(2), Paragraphs 1-2). Therefore, the remarks regarding no “generic computer” can execute the particular instruction is considered not persuasive.
Although Applicant’s arguments are not persuasive, rejection of claims 1-6, 9, 11-16, 19, and 20-26 under 35 U.S.C. 101 are withdrawn due to the matter added to the claims, making them patent-eligible.
Applicant’s arguments, see Page 10, lines 11-17, filed August 27 2025, with respect to the rejections of claims 1, 9, and 11 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made under 35 U.S.C. 103 over Arndt, in view of Pearce. See 103 rejections above.
Applicant’s arguments, see Page 11, lines 3-9, filed August 27 2025, with respect to the rejections of claims 2-8, 12-19, and 22-26 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made under 35 U.S.C. 103 over Arndt, in view of Pearce and Joao, a new ground of rejection under 35 U.S.C. 103 over Arndt, in view of Pearce, Joao, and Bolz, and a new ground of rejection is made under 35 U.S.C. 103 over Arndt, in view of Pearce, Joao, and Barreh. See new 103 rejections above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
“Operating System” by Wikipedia: Provides the definition of an operating system.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.A./Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183