DETAILED ACTION
This office action is in response to applicant’s amendment filed on March 11, 2026. Claims 1-15 and 17-20 are under consideration.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the amended limitations of claim 1, lines 10-15:
“a first wiring pattern and at least one first electrical connection of the plurality of first electrical connections interconnecting the at least one converter to a corresponding at least one host chip; and
a second wiring pattern having a first end electrically connected to at least one of the second electrical connections of the plurality of second electrical connections, and a second end opposite the first end, electrically connected to the corresponding at least one host chip.”
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The limitation of claim 15—a lens embedded in the first opposing surface of the packaging substrate configured to collimate the optical signals generated by the at last one electro-optical converter output from the bridge chip—must be shown or the feature(s) canceled from the claim(s).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-15, and 17-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 is amended to include—at least one converter, the at least one converter located on top of the first opposing surface and comprising at least one of an electro-optical converter and an optical-electro converter, the electro-optical converter configured to convert an electrical signal to an optical signal and the optical-electro converter configured to convert an optical signal to an electrical signal—is not shown in the figures or in the written description.
Fig. 5 shows the bridge chip 70 is set in trench 68. The converter 76 is shown to be embedded inside the bridge chip 70 and the converter does not appear to be located on top of the first opposing surface. Converter 76 appears to be embedded within the bridge chip 70. In this embodiment it is unclear how the converter 76 that is centered on the bridge chip 70 is related to the embodiment of the bridge chip 12 shown in Fig. 2 wherein the converters 24 are distributed throughout the bridge chip. Also, it is unclear if the converters 24 are “located on top of the first opposing surface” from the view of fig. 2. Fig. 3 is a side view but does not show converters 24. Furthermore, the bridge chip 70 shown in Fig. 5 does not show a lens or alignment holes. Therefore, it appears the bridge chip 12 and the bridge chip 70 are different embodiments, but the bridge chip 70 is most representative of the structure recited in claim 1. For these reasons, the examiner considers the converter located on top of the first opposing surface is new matter. For examination purposes, the examiner shall consider the converter to be within the bridge chip.
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The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "connected to at least one of the second electrical connections" in line 14. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wilkerson et al. (US 2022/0342165 A1, herein “Wilkerson”).
Claim 1, Wilkerson discloses a bridge chip (at least Figs. 5-7, PIC modules 314) comprising:
a first and second opposing surfaces, the first opposing surface having a plurality of first electrical connections (conductive elements 326 on the left) and a plurality of second electrical connections (conductive elements 326 on the right);
at least one converter (within PIC module 314), the at least one converter comprising at least one of an electro-optical converter and an optical-electro converter, the electro-optical converter configured to convert an electrical signal to an optical signal and the optical-electro converter configured to convert an optical signal to an electrical signal (Para [0041]);
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a first wiring pattern (PIC interconnects 320 on the left) and at least one first electrical connection of the plurality of first electrical connections (conductive elements 326 on the left) interconnecting at least one converter (PIC module 314) to a corresponding at least one host chip (semiconductor chip 302 on the left); and
a second wiring pattern (bond pads 332 right) having a first end electrically connected to at least one of the second electrical connections of the plurality of second electrical connections (conductive elements 326 on the right), and a second end opposite the first end electrically connected to the corresponding at least one host chip (302)(Para [0052]).
Claim 2. Wilkerson discloses the bridge chip of claim 1, wherein the first wiring pattern (320) interconnects a plurality of host chips (left chip 302, right chip 302) to each other (via RDL 330, Para [0057]).
Claim 3. Wilkerson discloses the first wiring pattern interconnects the plurality of host chips in a topology is a bus topology, as evidenced by the description of Fig. 7 is “a fanout module” and the basic interconnect embodiment of Fig. 2, refers to the semiconductor chip (102) houses various components including functional logic blocks, logic gates, clocks, buses, and other elements (Para [0047]).
Claim 7. Wilkerson discloses the invention of claim 1, further comprising at least one electrical through link (conductive pillars 308) connected to the second wiring pattern (bond pad 340 via plurality of second electrical connections), the at least one electrical through link (308) extending from the first opposing surface to the second opposing surface, the at least one electrical through link being configured to output electrical signals from the at least one host chip. The fanout module integrating a photonic integrated circuit are electrically interconnected via conductive elements, bond pads, RDL, and conductive pillars. Wilkerson further discloses electrical signals convey data between the PIC modules 114 and the semiconductor chip (“host chip” 102) through electrical pathways (Para [0041]) and substrate (190) supplies power and ground to the components of the package structure (100) and for providing I/O pathways to external components (Para [0043]). Therefore, the examiner considers Wilkerson implicitly discloses the electrical through link as recited in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Wilkerson in view of McLaren et al. (US 2015/0003841 A1, herein “McLaren”).
Regarding claims 4-6, Wilkerson discloses the bridge chip of claim 1, and further the bridge chip includes an optical interface (optical interface 318) configured to output optical signals generated by the at least one electro-optical converter (integrated within PIC module 314).
However, Wilkerson does not disclose an optical interface located on the second opposing surface and configured to output the optical signals generated by the at least one electro-optical converter from the second opposing surface and configured to receive optical signals through the second opposing surface and to transmit the received optical signals to the at least one optical-electro converter.
McLaren teaches an electro-optical package for an opto-electronic engine (Figs. 2B and 3A) wherein a bridge chip (110) has a plurality of electrical connections (annotated “bond pads”) and an opto-electronic component (210) formed on the first surface of the bridge chip (110) for communicating with integrated chip (240). An optical interface comprises of optical via (118-1) and optical lens (130-1) provided on the second surface (opposing surface) of the bridge chip (110) to insure a beam exiting the assembly of the opto-electronic engine (201) has low divergence (collimating, Para [0035). The opto-electronic component (210-1) may be a photo-diode or a surface-emitting laser (VCSEL, for transmitting). In Fig. 3A, optical signal from waveguide 344 is received by the optical interface (lens or aperture 126-1) through optical via (118-1), wherein the circuitry of Fig. 2B the electrical signals travel directly in the carrier substrate (110, or “bridge chip”) between the integrated circuit 240) and the opto-electronic component (210-1) (Para [0025]). This direct communication is made possible by the electro-optical package includes a carrier substrate (110), a plurality of intra-package electrical interconnects wherein the received optical signal from lens (130-1) is transmitted to the opto-electronic component (210) which converts the optical signal to an electrical signal, and vice versa, via the photodiode therein (Para [0018], [0031]).
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It would have been obvious to one having ordinary skill at the time of filing to recognize the bridge chip of McLaren wherein the converter is formed on the first side of the bridge chip and an optical interface formed on the second side of the bridge chip and the optical signal is facilitated by optical via would have been obvious to one having ordinary skill in the art, such as Wilkerson. One motivation would be the trade-off of higher fabrication cost for improved signal quality (Para [0024]).
Claims 8-14, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wilkerson in view of Zhang et al. (US 2022/0199600 A1, herein “Zhang”) and McLaren et al. (US 2015/0003841 A1, herein “McLaren”).
The examiner notes, the method steps of claims 17-20 are not patentably distinct from the product claims since the assembly and operation of the device as recited in claims 8-15 would also teach the method steps of claims 17-20. Therefore, the rejections to the method claims 17-20 are incorporated herein.
Regarding claim 8 and 17, Wilkerson discloses a bridge chip (at least Figs. 5-7) comprising:
a first and second opposing surfaces, the first opposing surface having a plurality of first electrical connections (conductive elements 326 on the left) and a plurality of second electrical connections (conductive elements 326 on the right);
at least one converter (within PIC module 314), the at least one converter comprising at least one of an electro-optical converter and an optical-electro converter, the electro-optical converter configured to convert an electrical signal to an optical signal and the optical-electro converter configured to convert an optical signal to an electrical signal (Para [0041]);
a first wiring pattern (PIC interconnects 320 on the left) and at least one first electrical connection of the plurality of first electrical connections (conductive elements 326 on the left) interconnecting at least one converter (PIC module 314) to a corresponding at least one host chip (semiconductor chip 302 on the left); and
a second wiring pattern (bond pads 332 right) having a first end electrically connected to at least one of the second electrical connections of the plurality of second electrical connections (conductive elements 326 on the right), and a second end opposite the first end electrically connected to the corresponding at least one host chip (302)(Para [0052]);
at least one host chip (302 on the left and 302 on the right) overlying the first opposing surface of the bridge chip and the first opposing surface of the packaging substrate, the at least one host chip being directly connected to the first opposing surface of the bridge chip and the first opposing surface of the packaging substrate by a plurality of electrical connections (See annotated Fig. 6 above).
However, Wilkerson does not teach the packaging structure comprising: a packaging substrate having a first and second opposing surfaces, a trench provided in the first opposing surface of the packaging substrate; a bridge chip disposed in the trench; an opening provided in the second opposing surface of the packaging substrate, the opening extending to the second opposing surface of the bridge chip and; wherein the optical signals are output from the integrated circuit packaging structure through the opening in the second opposing surface of the packaging substrate.
Zhang discloses an optical multichip package with multiple system-on-chip dies.
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The configuration shown in Fig. 7, replicated above, shows a packaging substrate (704) comprising a first and second opposing surfaces, a trench (opening that is occupied by SOC Core 708) provided in the first opposing surface of the packaging substrate; a bridge chip (SOC Core 708) disposed in the trench. At least one host chip overlying the first opposing surface of the bridge chip being directly connected to the first opposing surface of the bridge chip and the first opposing surface of the packaging substrate by a plurality of electrical connections (705).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the bridge chip of Wilkerson would be modifiable to provide interconnection (bridge) to multi-chip with multiple system-on-chip dies as demonstrated by Zhang. One would be motivated to design the bridge chip to lie within the trench for planarization and miniaturization of the chip package.
Wilkerson in view of Zhang do not explicitly teach an opening provided in the second opposing surface of the package substrate, the opening extending to the second opposing surface of the bridge chip; wherein the optical signals are output from the integrated circuit packaging structure through the opening in the second opposing surface of the packaging substrate.
McLaren teaches the bridge chip (carrier substrate 110) is interconnect electrically with an opto-electronic component 210-1 (PIC die) mounted on the back side (110-1) of the carrier substrate (110) and includes an optical aperture (126-1) at the front side (110-2) of the carrier substrate (110) for communication of optical signals through the optical via (118-1) to and from the opto-electronic component (210-1). McLaren further teaches the opto-electronic component (210-1) may be selected from the group consisting of an optical transmitter such as a vertical-cavity surface emitting laser (VCSEL), and an optical receiver, such as a photo-diode, without limitation thereto. The package base (140) is to provide for communication of electrical signals to or from an integrated circuit (240) and the opto-electronic component (210-1) (Para [0021]-[0022] and Fig. 2A)
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the optical through via (118-1) of McLaren would be modifiable by forming through vias through a semiconductor carrier substrate using reactive ion etching. One motivation for providing optical through vias such that the multichip package assembly can be independent and flexible in integration since there are interconnection channels (electrical and optical) on the front side of the chip package and the back side of the chip package.
Claim 9. Wilkerson / Zhang / McLaren teach the invention of claim 8, Wilkerson further discloses the host chips (302) are electrically connected (first wiring pattern) to each other via RDL structure (330) and the RDL structure (330 is connected to the first wiring pattern (316) via conductive element (326). Thus, the host chips are interconnected to each other.
Claim 10. Wilkerson in view of Zhang and McLaren (herein “Wilkerson / Zhang / McLaren”) teach the invention of claim 8. Wilkerson further teaches the first wiring pattern interconnects the plurality of host chips in a topology is a bus topology, as evidenced by the description of Fig. 7 is “a fanout module” and the basic interconnect embodiment of Fig. 2, refers to the semiconductor chip (102) houses various components including functional logic blocks, logic gates, clocks, buses, and other elements (Para [0047]).
Regarding claims 11-13, Wilkerson / Zhang / McLaren teach the invention of claim 8, McLaren further teaches the bridge chip (carrier substrate 110) is interconnect electrically with an opto-electronic component (PIC die 210-1) mounted on the back side (110-1) of the carrier substrate (110) and includes an optical aperture (126-1) at the front side (110-2) of the carrier substrate (110) for communication of optical signals through the optical via (118-1) to and from the opto-electronic component (210-1). The optical interface comprises of optical via (118-1) and optical lens (130-1) provided on the second surface (opposing surface) of the bridge chip (110) to insure a beam exiting the assembly of the opto-electronic engine (201) has low divergence (collimating or focus, Para [0035). The opto-electronic component (210-1) may be a photo-diode or a surface-emitting laser (VCSEL, for transmitting). In Fig. 3A, optical signal from waveguide 344 is received by the optical interface (lens or aperture 126-1) through optical via (118-1), wherein the circuitry of Fig. 2B the electrical signals travel directly in the bridge chip (110) between the integrated circuit (240) and the opto-electronic component (210-1) (Para [0025]). This direct communication is made possible by the electro-optical package includes a bridge chip (110), a plurality of intra-package electrical interconnects wherein the received optical signal from lens (130-1) is transmitted to the opto-electronic component (210-1) which converts the optical signal to an electrical signal, vice versa, via the photodiode therein (Para [0018], [0031]).
Claims 14 and 20. Wilkerson / Zhang / McLaren teach the invention of claim 8, Wilkerson further comprising at least one electrical through link (conductive elements 326) connected to the second wiring pattern (PIC interconnects 320), the at least one electrical through link extending from the first opposing surface to the second opposing surface, the at least one electrical through link being configured to output electrical signals from the at least one host chip. The fanout module integrating a photonic integrated circuit are electrically interconnected via conductive elements, bond pads, RDL, and conductive pillars. Wilkerson further discloses electrical signals convey data between the PIC modules 114 and the semiconductor chip (“host chip” 102) through electrical pathways (Para [0041]) and substrate (190) supplies power and ground to the components of the package structure (100) and for providing I/O pathways to external components (Para [0043]). Therefore, the examiner considers Wilkerson implicitly discloses the electrical through link as recited in the claim.
Claims 15, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wilkerson / Zhang / McLaren in further view of Thacker et al. (US 2016/0216445 A1, herein “Thacker”) and Dutta (US 2005/0224946 A1, herein “Dutta”).
Regarding claims 15 and 18-19, Wilkerson / Zhang / McLaren teach the invention of claim 11, McLaren further teaches a lens (130-1) embedded in the first opposing surface of the packaging substrate (bridge chip 110) configured to collimate the optical signals (has low divergence, Para [0035]) generated by the at least one electro-optical converter output from the bridge chip. The optical signals and electrical signals in McLaren’s hybrid electro-optical package are facilitated by the optical via (118-1) and electrical via (114-1).
However, Wilkerson / Zhang / McLaren do not teach a lens embedded in the first opposing surface of the packaging substrate configured to collimate the optical signals generated by the at least one electro-optical converter output from the bridge chip and to focus the received optical signals to the at least one optical-electro converter.
Thacker teaches a chip package that is capable of converting electrical signals to optical signals and vice versa (Para [0033], [0035]). Figure 1 shows an optical interface (cavity 158) provided within the chip package (100). The optical interface comprises a lens (162) on the second opposing surface configured to couple light externally to the optical fiber connector (140-1).
However, prior arts to Wilkerson / Zhang / McLaren in view of Thacker is silent to the lens is configured to collimate the output optical signals and focus the received signals to the receiver.
Dutta teaches an integrated microlens (232) are formed on the back surface of substrate (222) to correct the optical beam profile so that the beam propagating towards the back surface (receiver) is focused with a low divergence angle (collimated beam) for coupling into the waveguide. The microlens(es) can be formed using the same encapsulation layer material such as adhesive, epoxy, or polymer materials and using the standard microlens process. Furthermore, Dutta teaches “[t]o make a collimated output beam, the focal length of the microlens should be designed to be around twice of the substrate thickness” (Para [0115] and Figs. 21A-21C).
It would have been obvious to one having ordinary skill at the time of filing to modify the optical interface in the invention of Wilkerson / Zhang / McLaren’s teaching (McLaren Fig. 2B) with the integrated lens embedded in the packaging substrate and allowing the optical signal to be received or transmitted to the integrated circuit through the bridge chip facilitated by optical vias and electrical vias. The resulting implementation allows the opto-electronic package to have high quality signals while reducing the overall device profile.
Response to Arguments
Applicant's arguments filed on March 11, 2026 have been fully considered but they are not persuasive. Applicant argues Wilkerson does not teach the amended limitations of claim 1, and similarly in claim 8 and 17. Bond pads 332 in Wilkerson’s Fig. 2B are disposed entirely on top of the first opposing surface. As for the at least one converter located on top of the first opposing surface does not appear to be fully disclosed in the relevant embodiment that is integrated with the packaging substrate and the host chips, namely Fig. 5. Applicant remarked Figs. 1-3 disclose the amended limitation to the converter located on top of the first opposing surface. However, the relevant embodiment which wherein the bridge chip is placed in the cavity, as shown in Fig. 5, the converter appears to be embedded within the bridge chip. The text of the Fig. 5 does not clarify the modification or changes from the bridge chip in embodiment of Fig. 2 to the bridge chip in the embodiment of Fig. 5. For these reasons, the examiner considers applicant’s argument that Wilkerson not teaching the amended limitations of claims 1, 8, and 17 not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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