DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Claims 1-4, 7, 9-13, 16, 18, and 21 are currently pending.
Independent claim(s) 1, 9 and 16 have been amended by applicant’s amendments received 05 August 2026. No new matter has been introduced.
Claims 6, 15 and 20 have been canceled, and therefore the prior rejections is/are moot.
Response to Arguments
Applicant’s arguments, see pgs. 7-8 of Remarks, filed 05 August 2026, with respect to the rejection(s) of claim(s) 1-4, 6-7, 9, and 21 under 35 U.S.C. 103 have been considered but are moot because the new ground of rejection does not rely on the specific combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument, notably the newly added limitation to the independent claims.
Regarding specifically claims 1, 9 and 16 applicant cites that the cited art (Yamazaki, US 20140034982 A1 in view of Nakanishi, US 20210088928 A1) fails to make obvious the newly added limitations “and the signal line is arranged between each of the areas such that the signal line does not overlap any of the areas in plan view”. While Yamazaki in view of Nakanishi teaches a combination where the signal line is arranged between areas, neither explicitly describes that signals lines would not overlap the other areas in the plurality of areas. However, upon further search and consideration, the rejections under 35 USC § 103 have been updated as can be found below in view of newly found prior art reference(s).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7, 9, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20140034982 A1), in view of Nakanishi (US 20210088928 A1), and further in view of Ohno (US 20130250031 A1).
Regarding claims 1 and 9, as an oxide film acts as an insulator, Yamazaki teaches a light emitting device, comprising
a semiconductor substrate (Figs 1A, 1B, 11A, 11B; substrate (100));
a light-emitting-element section formed on the semiconductor substrate and including a plurality of light emitting elements that radiate light ([0177] - [0179]; Fig. 8 which shows a pixel portion (120), which has multiple light-emitting pixels (253));
a signal line that is formed along a first direction on the semiconductor substrate and that transmits a signal to the light emitting elements ([0177] - [0179], [0253]), wherein the signal line does not supply a current for causing the light emitting elements to emit light ([0183], [0199] - [0212]; Figs. 11A, B where signal line (272) is separate from power line (273));
and an oxide film (insulator) formed between the signal line and the semiconductor substrate along an extension direction of the signal line ([0199] - [0212]), wherein
and the oxide film (insulator) is formed continuously between the signal line and the semiconductor substrate over an entire region where the signal line is formed ([0199] - [0212]; Figs. 11A, B where insulating layer (oxide film) (102) occurs continuously above substrate (100) and below signal lines (272)).
Yamazaki does not inherently teach that the light-emitting-element section includes a plurality of areas, where signal lines do not overlap the areas.
Nakanishi teaches a light-emitting-element section includes a plurality of areas, and the light emitting elements are connected to the signal line in each of the plurality of areas ([0147] - [0150]; Figs. 3, 17A where element array chips (C1 to C29) each are formed as light emitting device (100) and connected via connector (270)).
Ohno discloses that for an array of areas (rows) of light emitting regions, the signal lines of a first area do not overlap with a second area or the second area’s signal lines, such that the signal line(s) is/are arranged between each of the areas such that the signal line does not overlap any of the areas in plan view ([0006], [0062], [0063]; Fig. 8, where rows of light emitting regions (108) are connected by light emission signal lines (107) which, in plan view, do not overlap other rows of light emitting elements. Examiner’s note: This limitation is given the Broadest Reasonable Interpretation in view of the specification such as on pg. 10, where the signal lines are described to “… not overlap the areas 35 except for portions connected to the light emitting elements 40 in the areas 35”. This BRI is given to the teachings of both Nakanishi and Ohno, where there is some obvious overlap of signal lines within areas to send signals to the light emitting components).
To one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Yamazaki to incorporate the teachings of Nakanishi and Ohno to combine multiple light emitting sections (pixel portions) with non-overlapping signal lines, where each pixel portion has a plurality of emitting elements as taught by Yamazaki, with a reasonable expectation of success of creation of an emitter array, which is grouped into subsects of emitters. The light emitting device of Yamazaki is similar to the light emitting device taught by Nakanishi ([0037]; Fig. 2A, 2B, emitter (100)) and Ohno (Figs. 10-13 show various embodiments of multiple groups of emitters and options for signal line placement) which has a plurality of emitters on a semiconductor substrate, where the individual emitters are thyristors. Arrangement of the light emitting devices of Nakanishi (Fig. 17A, C1 to C29) so that the signal lines of each semiconductor light emitting device (Fig. 3, (100)) are aligned between element sections would not have modified the operation of the device of Fig. 17A, and therefore would be a predictable rearrangement of parts to form a larger emitter array with separate groups of pixels/emitters.
Regarding claim 2, Yamazaki as modified above teaches the light emitting device according to Claim 1, wherein
the signal line transmits a signal from a terminal disposed in the semiconductor substrate to the light- emitting-element section ([0178] - [0179], [0201]; where the signal lines can occur in channel formations within the semiconductor layers).
Regarding claim 3, Yamazaki as modified above teaches the light emitting device according to Claim 2, wherein
a signal for causing the light emitting elements to emit light is transmitted from the terminal to the signal line ([0177] - [0179], [0281]).
Regarding claim 4, Yamazaki as modified above teaches the light emitting device according to Claim 3, wherein
the signal line has a same potential regardless of distances from the light emitting elements ([0194]; where the system may set the potential of the signal lines to a specific value).
Regarding claim 7, Yamazaki as modified above teaches the light emitting device according to Claim 1, wherein
a width of the signal line in a short-side direction is smaller than a width of each of the areas in plan view ([0199] - [0212]; Figs. 11A, 11B where signal line (272) is narrower than width of one pixel, and therefore would be narrower than an area which includes a plurality of pixels).
Regarding claim 21, Yamazaki as modified above teaches the light emitting device according to Claim 1, further comprising
an anode electrode to which the current for causing the light emitting elements to emit light is supplied, wherein the signal line is a wiring different from a wiring connected to the anode electrode ([0149]; Fig. 1A, 1B where pixel electrode (106) may serve as a cathode or anode and supplies power to the light-emitting device).
Claim(s) 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20140034982 A1), in view of Nakanishi (US 20210088928 A1) and Ohno () as applied to claims 1 and 9 above, and further in view of Shimada et al. (hereinafter Shimada, US 20240213281 A1).
Regarding claim 10, Yamazaki as modified above teaches the light emitting device according to Claim 1, but fails to teach an optical measurement apparatus which includes a light receiver or a measurer to determine distance.
Shimada teaches a distance measuring system, where a light receiver receives light emitted from the light emitting device and reflected by an object ([0267] - [0269]; Fig. 32, receiver (652))
and a measurer that measures a distance to the object based on a flight distance of light emitted from the light emitting device and received by the light receiver ([0269] - [0270]; Fig. 32, signal processing circuit (653)).
To one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to incorporate the emitter device of Yamazaki as modified by Nakanishi into a distance measurement system as taught by Shimada with a reasonable expectation of success. Shimada notes that the type of laser source within their system can be arbitrarily set to align with the application of the distance measuring system ([0265]). This would incorporate the emitter array of Yamazaki as modified by Nakanishi with predictable results where a distance measuring system emits light and the reflected light is received by the system, such that a time-of-flight distance measurement is obtained between the system and an object in the environment.
Claims 11, 12 and 13 are similarly rejected to claim 10.
Claim(s) 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20140034982 A1), in view of Nakanishi (US 20210088928 A1), Ohno (US 20130250031 A1), and Kondo (JP 6369613).
Regarding claim 16, Yamazaki teaches a light emitting device, comprising
a semiconductor substrate (Figs 1A, 1B, 11A, 11B; substrate (100));
a light-emitting-element section formed on the semiconductor substrate and including a plurality of light emitting elements that radiate light ([0177] - [0179]; Fig. 8 which shows a pixel portion (120), which has multiple light-emitting pixels (253));
a signal line that is formed along a first direction on the semiconductor substrate and that transmits a signal to the light emitting elements ([0177] - [0179], [0253]), wherein the signal line does not supply a current for causing the light emitting elements to emit light ([0183], [0199] - [0212]; Figs. 11A, B where signal line (272) is separate from power line (273));
and an oxide film (insulating layer) formed between the signal line and the semiconductor substrate along an extension direction of the signal line ([0199] - [0212]), wherein
and the oxide film (insulator) is formed continuously between the signal line and the semiconductor substrate over an entire region where the signal line is formed ([0199] - [0212]; Figs. 11A, B where insulating layer (oxide film) (102) occurs continuously above substrate (100) and below signal lines (272)).
Yamazaki does not inherently teach that the light-emitting-element section includes a plurality of areas, where signal lines do not overlap the areas, or a resistor in the circuit.
Nakanishi teaches a light-emitting-element section includes a plurality of areas, and the light emitting elements are connected to the signal line in each of the plurality of areas ([0147] - [0150]; Figs. 3, 17A where element array chips (C1 to C29) each are formed as light emitting device (100) and connected via connector (270)).
Ohno discloses that for an array of areas (rows) of light emitting regions, the signal lines of a first area do not overlap with a second area or the second area’s signal lines, such that the signal line(s) is/are arranged between each of the areas such that the signal line does not overlap any of the areas in plan view ([0006], [0062], [0063]; Fig. 8, where rows of light emitting regions (108) are connected by light emission signal lines (107) which, in plan view, do not overlap other rows of light emitting elements. Examiner’s note: This limitation is given the Broadest Reasonable Interpretation in view of the specification such as on pg. 10, where the signal lines are described to “… not overlap the areas 35 except for portions connected to the light emitting elements 40 in the areas 35”. This BRI is given to the teachings of both Nakanishi and Ohno, where there is some obvious overlap of signal lines within areas to send signals to the light emitting components).
Kondo teaches a resistor that limits a current to the light emitting elements ([0032] - [0034], [0054]; Figs. 5,6 where light-emitting chip (C1) has resistors (Rg1) to (Rg128)).
To one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Yamazaki to incorporate the teachings of Nakanishi and Ohno to combine multiple light emitting sections (pixel portions) with non-overlapping signal lines, where each pixel portion has a plurality of emitting elements as taught by Yamazaki, and to incorporate the teachings of Kondo to explicitly include a resistor within the circuit, with a reasonable expectation of success of creation of an emitter array, which is grouped into subsects of emitters, with the currents controlled. The light emitting device of Yamazaki is similar to the light emitting device taught by Nakanishi ([0037]; Fig. 2A, 2B, emitter (100)) and Ohno (Figs. 10-13 show various embodiments of multiple groups of emitters and options for signal line placement) which has a plurality of emitters on a semiconductor substrate, where the emitters are thyristors. Arrangement of the light emitting devices of Nakanishi (Fig. 17A, C1 to C29) so that the signal lines of each semiconductor light emitting device (Fig. 3, (100)) are aligned between element sections would not have modified the operation of the device of Fig. 17A, and therefore would be a predictable rearrangement of parts to form a larger emitter array with separate groups of pixels/emitters. Additionally, Yamazaki notes that the system already inherently includes taking resistance of components into account ([0074]), and as resistors are well known circuit components, integration would have the predictable result of specifically controlling the current at points within the emitter array.
Regarding claim 18, Yamazaki as modified above teaches the light emitting device according to Claim 16, wherein
the insulating layer is further formed in a predetermined region around the region of the resistor ([0231] - [0329]; Figs. 9, 11A-B, 14, 15; wherein if the system as modified in claim 16 incorporates resistors within the circuits such as in Fig. 14, the resistors will be formed in the regions of the first transistor (261) and the second transistor (262) and therefore will be reasonably formed in an area with the insulating layer (102) underlying it).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Anzaki et al. (US 5173759 A) teaches an array of light emitting devices or detectors, where the invention relates to an optical printer head using plural light emitting devices, or an image sensor or other array using plural photo detectors, and an apparatus for printing or reading using the array, method of manufacturing the array, and method of mounting the array.
Lee et al. (US 12014509 B2) teaches an optical device with an emitter and receiver, where the emitter contains a plethora of light emitting units in element groups, which make up an array connected by a conductive circuit.
Endo (US 20230005400 A1) teaches a light emitting apparatus, with an array of pixel includes current paths situated between the pixels all formed on a semiconductor substrate with an insulating layer.
Fukutome (US 20180095336 A1) teaches a semiconductor device with an array, driver circuit, and use of oxide and insulating films within the device which may overlap with wiring.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kara Richter whose telephone number is (571)272-2763. The examiner can normally be reached Monday - Thursday, 8A-5P EST, Fridays are variable.
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/K.M.R./Examiner, Art Unit 3645
/JAMES R HULKA/Primary Examiner, Art Unit 3645
