DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/28/2025 has been entered.
Response to Amendment
The Amendment filed on 10/28/2025 has been entered. Claims 21-39 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 24-27 and 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over United States Application Publication No. 2010/0267158, hereinafter Chou in view of United States Application Publication No. 2016/0013804, hereinafter Peluso.
Regarding claim 24, Chou teaches a system (figure 5) comprising: a plurality of sensor electrodes (the inside ends of items 14 and 15) corresponding to an array of nanogap sensors (paragraph [0029]), with a first nanogap sensor of the array of nanogap sensors including a first pair of sensor electrodes of the plurality of sensor electrodes (figure 5), and with the first pair of sensor electrodes being separated by a nanometric-size gap in a range between about 1 nm and about 100 nm (paragraph [0041]); an analog electrode (the outside ends of 14 and 15) configured to receive current from the plurality of sensor electrodes.
Chou fails to teach an integrator having a capacitor configured to integrate current from the analog electrode; a comparator configured to compare the integrated current with a reference voltage; a counter circuit configured to increase a count every time the integrator reaches the reference voltage in the comparator; and a cancellation circuit configured to remove charge from the capacitor.
Peluso teaches current counting system (Peluso, abstract) with an integrator (Peluso, item 304) having a capacitor (Peluso, item 304) configured to integrate current from the analog electrode (Peluso, paragraph [0036]); a comparator (Peluso, item 308) configured to compare the integrated current with a reference voltage (Peluso, paragraph [0035]); a counter circuit (Peluso, item 310) configured to increase a count every time the integrator reaches the reference voltage in the comparator (Peluso, paragraph [0036]); and a cancellation circuit (Peluso, item 306) configured to remove charge from the capacitor (Peluso, paragraph [0036]) so that the number of occurrences of the current can be counted (Peluso, abstract).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have utilized the current counting system of Peluso because it would allow for the number of occurrences of the current to be counted (Peluso, abstract) of the nanogap sensors.
Regarding claim 25, modified Chou teaches wherein the cancellation circuit removes the charge from the capacitor every time the count is increased (Peluso, paragraph [0036]).
Regarding claim 26, these limitations are directed to the function of the apparatus and/or the manner of operating the apparatus, all the structural limitations of the claim has been disclosed by Chou and Peluso and the apparatus of modified Chou is capable of determining a number of counts during a predetermined time period. As such, it is deemed that the claimed apparatus is not differentiated from the apparatus of modified Chou (see MPEP §2114).
Regarding claim 27, these limitations are directed to the function of the apparatus and/or the manner of operating the apparatus, all the structural limitations of the claim has been disclosed by Chou and Peluso and the apparatus of modified Chou is capable having the number of counts be a digital representation of the current. As such, it is deemed that the claimed apparatus is not differentiated from the apparatus of modified Chou (see MPEP §2114).
Regarding claim 37, these limitations are directed to the function of the apparatus and/or the manner of operating the apparatus, all the structural limitations of the claim has been disclosed by Chou and Peluso and the apparatus of modified Chou is capable having the current from the plurality of sensors combined to represent an average current. As such, it is deemed that the claimed apparatus is not differentiated from the apparatus of modified Chou (see MPEP §2114).
Claim(s) 28 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou and Peluso as applied to claim 24 above, and further in view of United States Application Publication No. 2015/0085985, hereinafter Funaki.
Regarding claims 28 and 29, Chou and Peluso teaches all of the limitations of claim 24; however, they fail to teach the cancellation circuit which is in electrical communication with a cancellation reference voltage and having a cancellation capacitor.
Funaki teaches a signal processing device which has a cancellation circuit with a capacitor which cancels out the integrating capacitor with the opposite charge from the capacitor to remove the charge on the integrating capacitor (Funaki, paragraph [0120]).
Examiner further finds that the prior art contained a device/method/product (i.e., a cancellation circuit with a cancellation capacitor) which differed from the claimed device by the substitution of component(s) (i.e., a grounded cancellation circuit) with other component(s) (i.e., cancellation circuit with a cancellation capacitor), and the substituted components and their functions were known in the art as above set forth. An ordinarily skilled artisan at the time of invention could have substituted one known element with another (i.e., a ground cancellation circuit with a cancellation circuit with a cancellation capacitor), and the results of the substitution (i.e., cancelling the charge on the integrator capacitor) would have been predictable.
Therefore, pursuant to MPEP §2143 (I), Examiner concludes that it would have been obvious to an ordinarily skilled artisan at the time of invention to substitute the grounded cancellation circuit of reference Peluso with the cancellation circuit with a cancellation capacitor of reference Funaki, since the result would have been predictable.
Claim(s) 30-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou and Peluso as applied to claim 24 above, and further in view of United States Patent No. 6,337,649, hereinafter Becker.
Regarding claims 30, Chou and Peluso teach all limitations of claim 24; however, they fail to teach a filtering circuit.
Becker teaches a comparator with a filter circuit which filters the pulse count so as to remove the number of counts which are counted in error and only propagates the actual valid counts (Becker, columns 2-3, lines 64-4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have added a filtering circuit to the device of modified Chou because it would remove the number of counts which are counted in error and only propagates the actual valid counts (Becker, columns 2-3, lines 64-4).
Regarding claim 31, these limitations are directed to the function of the apparatus and/or the manner of operating the apparatus, all the structural limitations of the claim has been disclosed by Chou, Peluso and Becker and the apparatus of modified Chou is capable of decimating the count. As such, it is deemed that the claimed apparatus is not differentiated from the apparatus of modified Chou (see MPEP §2114).
Regarding claim 32, these limitations are directed to the function of the apparatus and/or the manner of operating the apparatus, all the structural limitations of the claim has been disclosed by Chou, Peluso and Becker and the apparatus of modified Chou is capable of smooth the count. As such, it is deemed that the claimed apparatus is not differentiated from the apparatus of modified Chou (see MPEP §2114).
Regarding claim 33, these limitations are directed to the function of the apparatus and/or the manner of operating the apparatus, all the structural limitations of the claim has been disclosed by Chou, Peluso and Becker and the apparatus of modified Chou is capable of averaging the count over a second predetermined period of time. As such, it is deemed that the claimed apparatus is not differentiated from the apparatus of modified Chou (see MPEP §2114).
Claim(s) 34 and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou and Peluso as applied to claim 24 above, and further in view of United States Application Publication No. 2018/0034452, hereinafter Lu.
Regarding claims 34-35, Chou and Peluso teaches all limitations of claim 24; however, they fail to teach a multiplexer which is configured to multiplex the count with other data channels.
Lu teaches a device which utilizes a multiplexer which couples of the output of each additional oscillator to the counter one at a time and reading the resulting count for each of the additional oscillators so the system can be scaled up to include additional oscillators (Lu, paragraph [0103]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have added a multiplexer to the device of Chou because it would allow for the reading and counting of multiple sensors so that the system can be scaled up to include additional sensors (Lu, paragraph [0103]).
Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou, Peluso and Becker as applied to claim 30 above, and further in view of United States Patent No. 4,110,747, hereinafter LaBrie.
Regarding claim 36, Chou, Peluso and --Becker teach all limitations of claim 30; however, they fail to each a register.
LaBrie teaches a signal processing device in which a set of registers are utilized to store counts corresponding to the signal levels (LaBrie, column 5, lines 23-30).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have added a register because it would be able to store the counts corresponding to the values being detected (LaBrie, column 5, lines 23-30).
Claim(s) 38 and 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou and Peluso as applied to claim 37 above, and further in view of United States Application Publication No. 2008/0037008, hereinafter Shepard.
Regarding claims 38 and 39, Chou and Peluso teach all limitations of claim 37; however, they fail to teach a current conveyor which is a cascode between the analog electrode and the integrator.
Shepard teaches a biosensor chip in which an active cascode is utilized to increase the performance of the circuit by mitigating the effects of finite device output conductance (Shepard, paragraph [0065]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have added an active cascode before the integrator because it would increase the performance of the circuit by mitigating the effects of finite device output conductance (Shepard, paragraph [0065]).
Response to Arguments
Applicant’s arguments, see pages 6-7, filed 10/28/2025, with respect to the rejection(s) of claim(s) 24-27 and 37 under 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chou and Peluso.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW D KRCHA whose telephone number is (571)270-0386. The examiner can normally be reached M-Th 7am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Elizabeth Robinson can be reached at (571)272-7129. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW D KRCHA/ Primary Examiner, Art Unit 1796