Prosecution Insights
Last updated: April 19, 2026
Application No. 17/721,246

BOUNDARY CELLS ADJACENT TO KEEP-OUT ZONES

Non-Final OA §102
Filed
Apr 14, 2022
Examiner
YASMEEN, NISHATH
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tsmc Nanjing Company Limited
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
86%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
355 granted / 464 resolved
+8.5% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
21 currently pending
Career history
485
Total Applications
across all art units

Statute-Specific Performance

§103
59.1%
+19.1% vs TC avg
§102
19.2%
-20.8% vs TC avg
§112
18.3%
-21.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 464 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on 4/14/22, 4/15/24, 4/28/25 are being considered by the examiner. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "overlap", "layer", "portion" “region” are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently disclose a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “to occupy the same area in part”, “one thickness lying over or under another”, “an often limited part of a whole” “a part, portion, or area having no fixed boundaries” respectively. Further note the limitation “contact” is being interpreted to include "direct contact" (no intermediate materials, elements or space disposed there between) and "indirect contact" (intermediate materials, elements or space disposed there between). Claim(s) 1, 2, 6, 8, 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Furuta et al (US 2014/0091478 A1 hereinafter Furuta). Regarding Claim 1, Furuta discloses in Fig 8-10: An integrated circuit comprising: a first keep-out zone (KOZ) See Fig 10 having a first vertical zone-boundary; a second keep-out zone (See Fig 8) having a second vertical zone-boundary; an array of first-type active-region structures and an array of second-type active-region structures extending in a first direction between the first vertical zone-boundary and the second vertical zone-boundary, and wherein each of the first vertical zone-boundary and the second vertical zone-boundary extends in a second direction that is perpendicular to the first direction; an array of first-side boundary cells aligned with the first vertical zone-boundary along the second direction, wherein a first-side boundary cell has one or more ESD protection circuits (1003) and a pick-up region (1002); and an array of second-side boundary cells aligned with the second vertical zone-boundary along the second direction, wherein a second-side boundary cell has one or more ESD protection circuits. Examiner notes that Figs 10 illustrate a single TSV with a keep-out zone, however, based on Fig 8, the same configuration of I/O pad and ESD devices can be applied to other TSVs on the device [0063-0065]. PNG media_image1.png 442 671 media_image1.png Greyscale Regarding Claim 2, Furuta discloses in Fig 8-10: The integrated circuit of claim 1, wherein most length of an active-region structure in the first-side boundary cell is occupied by one or more ESD device regions (1003) See Fig 10. Regarding Claim 6, Furuta discloses in Fig 8-10: The integrated circuit of claim 1, wherein most length of an active-region structure in the second-side boundary cell is occupied by one or more ESD device regions (1003) See Fig 10. Regarding Claim 8, Furuta discloses in Fig 8-10: The integrated circuit of claim 1, wherein the second-side boundary cell further has a pick-up region (pad 1002) See Fig 10. Regarding Claim 9, Furuta discloses in Fig 8-10: An integrated circuit comprising: a first keep-out zone (KOZ) having a first vertical zone-boundary extending in a second direction that is perpendicular to a first direction; a second keep-out zone (See Fig 10) having a second vertical zone-boundary extending in the second direction; an array of active-region structures including a first pair of adjacent active-region structures and a second pair of adjacent active-region structures, the first pair of adjacent active-region structures having a first first-type active-region structure and a first second-type active-region structure, the second pair of adjacent active-region structures having a second first-type active-region structure and a second second-type active-region structure, wherein the first first-type active-region structure is adjacent to the second first-type active-region structure (See mark-up for claim 1), and (Examiner notes that there are no structural details of the active region structures, first first-type active-region structure, first second-type active-region structure, the second first-type active-region structure and a second second-type active-region structure are claimed and thus each of the cells as disclosed by Furuta reads on the above mentioned limitations. Additionally, the claim does not state that the “first-type” and “second-type” are different in any manner. wherein each active-region structure in the array of active-region structures extends in the first direction between the first vertical zone-boundary and the second vertical zone-boundary (It is noted that the active region structures are three dimensional structures and thus will extend in a first direction); a first-side boundary cell adjacent to the first vertical zone-boundary and having one or more ESD protection circuits (1003) and at least one pick-up region (1002); and a second-side boundary cell adjacent to the second vertical zone-boundary and having one or more ESD protection circuits (See Fig 10) [0063-0065]. Allowable Subject Matter Claims 19-20 are allowed. The following is an examiner’s statement of reasons for allowance: With respect to claim 19, the primary reason for allowance is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “a boundary cell having an ESD device region, a dummy device region, and a pick-up region in the active-region structure, wherein the pick-up region is between the ESD device region and the dummy device region” as recited in claim 19 in combination with the remaining features. Dependent claim 20 is allowed based on virtue of their dependencies The most relevant prior art references, US 2014/0091478 A1 to Furata et al in Figs 8-10 substantially teaches the limitations of the claim 19, with the exception of the limitations described in the preceding paragraph. None of the references disclose a dummy device region as claimed. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Claims 3-5, 7, 10-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 3, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “the first-side boundary cell has an ESD device region and a dummy device region therein, and wherein the dummy device region is between the ESD device region and the first vertical zone-boundary” as recited in claim 3 in combination with the remaining features. Dependent claim 4 is indicated as containing allowable subject matter based on virtue of its dependency. The most relevant prior art references, US 2014/0091478 A1 to Furata et al in Figs 8-10 substantially teaches the limitations of the claim 3, with the exception of the limitations described in the preceding paragraph. None of the references disclose a dummy device region as claimed. With respect to claim 5, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein the pick-up region in the first-side boundary cell is an active-region structure that also has an ESD device region and a dummy device region therein, and wherein the dummy device region is between the pick-up region and the first vertical zone-boundary.” as recited in claim 5 in combination with the remaining features. The most relevant prior art references, US 2014/0091478 A1 to Furata et al in Figs 8-10 substantially teaches the limitations of the claim 5, with the exception of the limitations described in the preceding paragraph. None of the references disclose a dummy device region as claimed. With respect to claim 7, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein an active-region structure in the second-side boundary cell has an ESD device region and a dummy device region therein, and wherein the dummy device region is between the ESD device region and the second vertical zone-boundary.” as recited in claim 7 in combination with the remaining features. The most relevant prior art references, US 2014/0091478 A1 to Furata et al in Figs 8-10 substantially teaches the limitations of the claim 7, with the exception of the limitations described in the preceding paragraph. None of the references disclose a dummy device region as claimed. With respect to claim 10, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein the first-side boundary cell includes a first dummy device region in the first first-type active-region structure and a second dummy device region in the first second-type active-region structure, and wherein each of the first dummy device region and the second dummy device region is adjacent to the first vertical zone-boundary.” as recited in claim 10 in combination with the remaining features. Dependent claims 11-15 are indicated as containing allowable subject matter based on virtue of their dependency. The most relevant prior art references, US 2014/0091478 A1 to Furata et al in Figs 8-10 substantially teaches the limitations of the claim 10, with the exception of the limitations described in the preceding paragraph. None of the references disclose a dummy device region as claimed. With respect to claim 16, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein the second-side boundary cell includes an ESD device region and a dummy device region in the first first-type active-region structure, and wherein the dummy device region is between the ESD device region and the second vertical zone-boundary.” as recited in claim 16 in combination with the remaining features. The most relevant prior art references, US 2014/0091478 A1 to Furata et al in Figs 8-10 substantially teaches the limitations of the claim 16, with the exception of the limitations described in the preceding paragraph. None of the references disclose a dummy device region as claimed. With respect to claim 17, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein the second-side boundary cell includes an ESD device region and a dummy device region in the first second-type active-region structure, and wherein the dummy device region is between the ESD device region and the second vertical zone-boundary.” as recited in claim 17 in combination with the remaining features. The most relevant prior art references, US 2014/0091478 A1 to Furata et al in Figs 8-10 substantially teaches the limitations of the claim 17, with the exception of the limitations described in the preceding paragraph. None of the references disclose a dummy device region as claimed. With respect to claim 18, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein the second-side boundary cell includes an ESD device region, a pick-up region, and a dummy device region in the first first-type active-region structure, and wherein the pick-up region is between the ESD device region and the dummy device region.” as recited in claim 18 in combination with the remaining features. The most relevant prior art references, US 2014/0091478 A1 to Furata et al in Figs 8-10 substantially teaches the limitations of the claim 18, with the exception of the limitations described in the preceding paragraph. None of the references disclose a dummy device region as claimed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NISHATH YASMEEN whose telephone number is (571)270-7564. The examiner can normally be reached Mon-Fri 9AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NISHATH YASMEEN/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Apr 14, 2022
Application Filed
Jan 02, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
86%
With Interview (+9.8%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 464 resolved cases by this examiner. Grant probability derived from career allow rate.

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