DETAILED ACTION
Claims 1-20 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0303040 A1 to Frolikov in view of U.S. Pub. No. 2003/0105927 A1 to Aoki and further in view of U.S. Pat. No. 9,063,668 B1 issued to Jung et al. and further in view of U.S. Pub. No. 2018/0365141 A1 To Dragojevic et al. and further of U.S. Pub. No. 2018/0239711 A1 to Hanson et al.
As to claim 1, Frolikov teaches a method comprising:
receiving, at a first processor located on a peripheral compute device (Controller 107), a stack pool reservation request from a host process executing on a second processor (Host System 101) (“…In general, the controller (107) can receive commands or operations from the host system (101) and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices (109A to 109N)...To have the capability of performing the factory functions, the controller (107) running the firmware (104) reserves and/or allocates a set hardware resources of the storage system (103). For example, a portion of the stack memory (102) is reserved for a processor (e.g., 121) and/or a process (e.g., running in a processor (e.g., 121)) that executes one or more factory functions programmed via the firmware (104)…” paragraphs 0021/0029), located on a host device communicatively coupled to the peripheral compute device via a host interface (host interface), the stack pool reservation request requesting a reservation of a pool of stack memory of a computing device for the host process (“…In general, the controller (107) can receive commands or operations from the host system (101) and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices (109A to 109N)...To have the capability of performing the factory functions, the controller (107) running the firmware (104) reserves and/or allocates a set hardware resources of the storage system (103). For example, a portion of the stack memory (102) is reserved for a processor (e.g., 121) and/or a process (e.g., running in a processor (e.g., 121)) that executes one or more factory functions programmed via the firmware (104)…” paragraphs 0021/0029); and
reserving of the pool of memory corresponding to the stack pool reservation request (“…In general, the controller (107) can receive commands or operations from the host system (101) and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices (109A to 109N)...To have the capability of performing the factory functions, the controller (107) running the firmware (104) reserves and/or allocates a set hardware resources of the storage system (103). For example, a portion of the stack memory (102) is reserved for a processor (e.g., 121) and/or a process (e.g., running in a processor (e.g., 121)) that executes one or more factory functions programmed via the firmware (104)…” paragraphs 0021/0029).
Frolikov is silent with reference to creating, by the first processor, a new thread corresponding to the host process, the new thread to be executed on the first processor,
assigning, at the first processor, a portion of the pool of memory to the new thread,
responsive to receiving the stack pool reservation request, reserving the pool of memory on the peripheral device for exclusive use of threads started by the host process or threads started by threads started by the host process,
the portion of the pool of memory assigned to the new thread specified in the stack pool reservation request and
wherein assigning the portion of the pool of memory is performed without transmitting a memory request across the host interface for the portion of the pool of memory.
Aoki teaches creating, by the first processor (Controller Unit 112/Accelerator Device 101), a new thread corresponding to the host process, the new thread to be executed on the first processor (“…The controller unit 112 performs various processing according to instructions from the CPU 102. When the controller unit 112 receives an instruction "Start" from the CPU 102 to start processing, it performs, for example, byte code processing by the interpreter, stack operation in the stack memory unit 113 or, when a byte code that cannot be executed by the accelerator device 101 is fetched out, stops the accelerator device 101 (STOP) and notifies the CPU 102…First, when the CPU 102 enters an interpreter loop, it transmits the instruction "START" to the accelerator device 101, which, in turn, executes interpreter processing…When a thread is generated, a stack area to which the generated thread belongs is determined. These values are stored for respective threads. When a thread becomes the current thread, the data is always located in the same area (stack area) of the stack memory 113…The number of threads belonging to each stack area is known so that when a new thread is generated, it is allocated to a stack area with the least number of threads… Hereinafter, a method for allocating stack frames when the number of threads exceeds the number of partitioned areas of the stack memory unit 113 will be described with reference to FIGS. 2 to 4. First, when the number of the generated threads does not exceed the number of the partitioned areas of the stack memory unit 113, the generated threads are directly allocated to the stack areas of the stack memory unit 113…” paragraphs 0018/0022//0029/0031) and
assigning, at the first processor, a portion of the pool of memory to the new thread (“…When a thread is generated, a stack area to which the generated thread belongs is determined. These values are stored for respective threads. When a thread becomes the current thread, the data is always located in the same area (stack area) of the stack memory 113…The number of threads belonging to each stack area is known so that when a new thread is generated, it is allocated to a stack area with the least number of threads… Hereinafter, a method for allocating stack frames when the number of threads exceeds the number of partitioned areas of the stack memory unit 113 will be described with reference to FIGS. 2 to 4. First, when the number of the generated threads does not exceed the number of the partitioned areas of the stack memory unit 113, the generated threads are directly allocated to the stack areas of the stack memory unit 113…” paragraphs 0027//0029/0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov with the teaching of Aoki because the teaching of Aoki would improve the system of Frolikov by providing a technique of allocating computing resources for optimal task processing.
Jung reaches responsive to receiving the stack pool reservation request (allocation request), reserving the pool of memory on the peripheral device (Thread Stack (e.g. 406a)) for exclusive use of threads (reserved for exclusive use) started by the process or threads started by threads started by the process (“…Thread memory (e.g. 410a) is used exclusively by the corresponding threads (e.g. 102a). The thread memory 410 includes a thread code (e.g. 412a) which comprises computer software instructions for implementing the logic of the thread. Also, the thread (e.g. 102a) has access to some portions of the global heap 108. The thread (e.g. 102a) gains access to memory blocks in the global heap 108 by sending an allocation request to the GMM 104 and receiving from GMM 104 addresses of memory blocks in the global heap 108 that have been allocated for the thread's exclusive use. The thread (e.g. 102a) also has access to its corresponding thread stack (e.g. 406a). The thread stack (406a) is reserved for exclusive use by the corresponding thread (e.g. 102a)…” Col. 9 Ln. 3-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov and Aoki with the teaching of Jung because the teaching of Jung would improve the system of Frolikov and Aoki by providing a technique of allowing for dedicated use of computing resource and thus providing for prioritized resource allocation.
Dragojevic teaches the portion of the pool of memory assigned to the thread specified in the stack pool reservation request (The request comprises a requested memory size) (“…In block 102, a user mode memory allocator of the computing device receives a request for non-volatile memory allocation of an object from a program executing on the computing device. The request comprises a requested memory size and registration data from the program. The registration data may be registration data for a page, which comprises at least one memory portion with a size suitable for allocation to the object…” paragraph 0037).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov, Jung, and Aoki with the teaching of Dragojevic because the teaching of Dragojevic would improve the system of Frolikov, Jung, and Aoki by providing a mechanism for allowing a memory requester to specify a required memory size.
Hanson teaches wherein assigning the portion of the pool of memory is performed without transmitting a memory request across the host interface for the portion of the pool of memory (any associated data to assigned memory locations located within the host's Dynamic Random Access Memory (DRAM) address space. These assigned location addresses are host memory-mapped to the NVMe Submission Queues.) (“…(NVMe). Hosts may interface with NVMe storage devices over a Peripheral Component Interconnect Express (PCIe) channel using a plurality of standardized memory-mapped Submission Queue and Completion Queue pairs…Host processors post data Input/Output (I/O) requests to NVMe storage devices by moving commands and any associated data to assigned memory locations located within the host's Dynamic Random Access Memory (DRAM) address space. These assigned location addresses are host memory-mapped to the NVMe Submission Queues. NVMe devices may detect posted requests and retain them until device processing logic moves them into the device for fulfillment…” paragraphs 0026/0027).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov, Jung, Aoki and Dragojevic with the teaching of Hanson because the teaching of Hanson would improve the system of Frolikov, Jung, Aoki and Dragojevic by providing a mechanism for allocating memory resource while avoiding round trip latency between at least two processing units.
As to claims 10 and 16, see the rejection of claim 1 above.
Claims 1, 4, 7-10, 13, 15, 16, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0303040 A1 to Frolikov in view of U.S. Pub. No. 2003/0105927 A1 to Aoki and further in view of U.S. Pat. No. 9,063,668 B1 issued to Jung et al. and further in view of U.S. Pub. No. 6,427,195 B1 issued to McGowen et al. and further of U.S. Pub. No. 20180239711 A1 to Hanson et al.
As to claim 1, Frolikov teaches a method comprising:
receiving, at a first processor located on a peripheral compute device (Controller 107), a stack pool reservation request from a host process executing on a second processor (Host System 101) (“…In general, the controller (107) can receive commands or operations from the host system (101) and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices (109A to 109N)...To have the capability of performing the factory functions, the controller (107) running the firmware (104) reserves and/or allocates a set hardware resources of the storage system (103). For example, a portion of the stack memory (102) is reserved for a processor (e.g., 121) and/or a process (e.g., running in a processor (e.g., 121)) that executes one or more factory functions programmed via the firmware (104)…” paragraphs 0021/0029), located on a host device communicatively coupled to the peripheral device via a host interface (host interface), the stack pool reservation request requesting a reservation of a pool of stack memory of the peripheral computing device for the host process (“…In general, the controller (107) can receive commands or operations from the host system (101) and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices (109A to 109N)...To have the capability of performing the factory functions, the controller (107) running the firmware (104) reserves and/or allocates a set hardware resources of the storage system (103). For example, a portion of the stack memory (102) is reserved for a processor (e.g., 121) and/or a process (e.g., running in a processor (e.g., 121)) that executes one or more factory functions programmed via the firmware (104)…” paragraphs 0021/0029); and
reserving of the pool of memory corresponding to the stack pool reservation request (“…In general, the controller (107) can receive commands or operations from the host system (101) and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices (109A to 109N)...To have the capability of performing the factory functions, the controller (107) running the firmware (104) reserves and/or allocates a set hardware resources of the storage system (103). For example, a portion of the stack memory (102) is reserved for a processor (e.g., 121) and/or a process (e.g., running in a processor (e.g., 121)) that executes one or more factory functions programmed via the firmware (104)…” paragraphs 0021/0029).
Frolikov is silent with reference to creating, by the first processor, a new thread corresponding to the host process, the new thread to be executed on the first processor,
assigning, at the first processor, a portion of the pool of memory to the new thread,
responsive to receiving the stack pool reservation request, reserving the pool of memory for exclusive use of threads started by the host process or threads started by threads started by the host process,
the portion of the pool of memory assigned to the new thread specified in the stack pool reservation request and
wherein assigning the portion of the pool of memory is performed without transmitting a memory request across the host interface for the portion of the pool of memory.
Aoki teaches creating, by the first processor (Controller Unit 112/Accelerator Device 101), a new thread corresponding to the host process, the new thread to be executed on the first processor (“…The controller unit 112 performs various processing according to instructions from the CPU 102. When the controller unit 112 receives an instruction "Start" from the CPU 102 to start processing, it performs, for example, byte code processing by the interpreter, stack operation in the stack memory unit 113 or, when a byte code that cannot be executed by the accelerator device 101 is fetched out, stops the accelerator device 101 (STOP) and notifies the CPU 102…First, when the CPU 102 enters an interpreter loop, it transmits the instruction "START" to the accelerator device 101, which, in turn, executes interpreter processing…When a thread is generated, a stack area to which the generated thread belongs is determined. These values are stored for respective threads. When a thread becomes the current thread, the data is always located in the same area (stack area) of the stack memory 113…The number of threads belonging to each stack area is known so that when a new thread is generated, it is allocated to a stack area with the least number of threads… Hereinafter, a method for allocating stack frames when the number of threads exceeds the number of partitioned areas of the stack memory unit 113 will be described with reference to FIGS. 2 to 4. First, when the number of the generated threads does not exceed the number of the partitioned areas of the stack memory unit 113, the generated threads are directly allocated to the stack areas of the stack memory unit 113…” paragraphs 0018/0022//0029/0031) and
assigning, at the first processor, a portion of the pool of memory to the new thread (“…When a thread is generated, a stack area to which the generated thread belongs is determined. These values are stored for respective threads. When a thread becomes the current thread, the data is always located in the same area (stack area) of the stack memory 113… The number of threads belonging to each stack area is known so that when a new thread is generated, it is allocated to a stack area with the least number of threads… Hereinafter, a method for allocating stack frames when the number of threads exceeds the number of partitioned areas of the stack memory unit 113 will be described with reference to FIGS. 2 to 4. First, when the number of the generated threads does not exceed the number of the partitioned areas of the stack memory unit 113, the generated threads are directly allocated to the stack areas of the stack memory unit 113…” paragraphs 0018/0022//0029/0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov with the teaching of Aoki because the teaching of Aoki would improve the system of Frolikov by providing a technique of allocating computing resources for optimal task processing.
Jung reaches responsive to receiving the stack pool reservation request (allocation request), reserving the pool of memory (Thread Stack (e.g. 406a)) for exclusive use of threads (reserved for exclusive use) started by the process or threads started by threads started by the process (“…Thread memory (e.g. 410a) is used exclusively by the corresponding threads (e.g. 102a). The thread memory 410 includes a thread code (e.g. 412a) which comprises computer software instructions for implementing the logic of the thread. Also, the thread (e.g. 102a) has access to some portions of the global heap 108. The thread (e.g. 102a) gains access to memory blocks in the global heap 108 by sending an allocation request to the GMM 104 and receiving from GMM 104 addresses of memory blocks in the global heap 108 that have been allocated for the thread's exclusive use. The thread (e.g. 102a) also has access to its corresponding thread stack (e.g. 406a). The thread stack (406a) is reserved for exclusive use by the corresponding thread (e.g. 102a)…” Col. 9 Ln. 3-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov and Aoki with the teaching of Jung because the teaching of Jung would improve the system of Frolikov and Aoki by providing a technique of allowing for dedicated use of computing resource and thus providing for prioritized resource allocation.
McGowen teaches the portion of the pool of memory assigned to the thread specified in the stack pool reservation request (the size of the requested block) (“…Each of the cache slots comprises a portion used for caching small blocks (if the small block allocation is active) and a portion used for caching ordinary blocks. As shown in FIG. 3A, when a memory request for a block of memory having a size of n bytes is received in step 301, the memory allocator 103 determines, in step 302, whether the request may be satisfied by a small block allocator within the cache layer 106. In a preferred embodiment, the determination is based on a comparison of the block size, i.e., n bytes, with a predetermined threshold value, e.g., 512 bytes. The threshold maybe configurable by a user. If the size of the requested block is less than or equal to the threshold, then the request is satisfied by a small block allocator within the cache layer 106 as shown in FIG. 3C. On the other hand, if the size of the requested block is greater than the threshold, then the request is satisfied by an ordinary block allocator within the cache layer 106 as shown in FIG. 3B…” Col. 6 Ln. 59-67, Col. 7 Ln. 1-8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov, Jung and Aoki with the teaching of McGowen because the teaching of McGowen would improve the system of Frolikov, Jung and Aoki by providing a mechanism for allowing a memory requester to specify a required memory size.
Hanson teaches wherein assigning the portion of the pool of memory is performed without transmitting a memory request across the host interface for the portion of the pool of memory (any associated data to assigned memory locations located within the host's Dynamic Random Access Memory (DRAM) address space. These assigned location addresses are host memory-mapped to the NVMe Submission Queues.) (“…(NVMe). Hosts may interface with NVMe storage devices over a Peripheral Component Interconnect Express (PCIe) channel using a plurality of standardized memory-mapped Submission Queue and Completion Queue pairs…Host processors post data Input/Output (I/O) requests to NVMe storage devices by moving commands and any associated data to assigned memory locations located within the host's Dynamic Random Access Memory (DRAM) address space. These assigned location addresses are host memory-mapped to the NVMe Submission Queues. NVMe devices may detect posted requests and retain them until device processing logic moves them into the device for fulfillment…” paragraphs 0026/0027).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov, Jung, Aoki and McGowen with the teaching of Hanson because the teaching of Hanson would improve the system of Frolikov, Jung, Aoki and McGowen by providing a mechanism for allocating memory resource while avoiding round trip latency between at least two processing units.
As to claim 4, Aoki teaches the method of claim 1, wherein the operations of creating, by the first processor (Controller Unit 112), the new thread is executed responsive to a new thread creation command from the host process on the second processor (CPU 102) (“…The controller unit 112 performs various processing according to instructions from the CPU 102. When the controller unit 112 receives an instruction "Start" from the CPU 102 to start processing, it performs, for example, byte code processing by the interpreter, stack operation in the stack memory unit 113 or, when a byte code that cannot be executed by the accelerator device 101 is fetched out, stops the accelerator device 101 (STOP) and notifies the CPU 102… First, when the CPU 102 enters an interpreter loop, it transmits the instruction "START" to the accelerator device 101, which, in turn, executes interpreter processing…When a thread is generated, a stack area to which the generated thread belongs is determined. These values are stored for respective threads. When a thread becomes the current thread, the data is always located in the same area (stack area) of the stack memory 113… The number of threads belonging to each stack area is known so that when a new thread is generated, it is allocated to a stack area with the least number of threads… Hereinafter, a method for allocating stack frames when the number of threads exceeds the number of partitioned areas of the stack memory unit 113 will be described with reference to FIGS. 2 to 4. First, when the number of the generated threads does not exceed the number of the partitioned areas of the stack memory unit 113, the generated threads are directly allocated to the stack areas of the stack memory unit 113…” paragraphs 0018/0022//0029/0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov, Jung, McGowen and Hanson with the teaching of Aoki because the teaching of Aoki would improve the system of Frolikov, Jung, McGowen and Hanson by providing a technique of allocating computing resources for optimal task processing.
As to claim 7, Frolikov teaches the method of claim 1, wherein the first processor (Controller 107) is one of a plurality of processors on a device communicatively coupled to a host device (Host System 101) (“…In general, the controller (107) can receive commands or operations from the host system (101) and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices (109A to 109N)...To have the capability of performing the factory functions, the controller (107) running the firmware (104) reserves and/or allocates a set hardware resources of the storage system (103). For example, a portion of the stack memory (102) is reserved for a processor (e.g., 121) and/or a process (e.g., running in a processor (e.g., 121)) that executes one or more factory functions programmed via the firmware (104)…” paragraphs 0021/0029).
As to claim 8, Frolikov teaches the method of claim 1, wherein the host interface is a Peripheral Component Interconnect Express (PCI-e) interface (Examples of a physical host interface include…a peripheral component interconnect express (PCIe) interface) (“…The host system (101) can be a computing device such as a desktop computer, laptop computer, network server, mobile device, or such computing device that includes a memory and a processing device. The host system (101) can include or be coupled to the memory system (108) so that the host system (101) can read data from or write data to the memory system (108). The host system (101) can be coupled to the memory system (108) via a physical host interface. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as, electrical, optical, magnetic, etc. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), etc. The physical host interface can be used to transmit data between the host system (101) and the memory system (108)…” paragraph 0016).
As to claim 9, Aoki teaches the method of claim 1, wherein the operations of creating the new thread and assigning the portion of the pool of memory to the new thread is performed without intervention from the second processor (CPU 102) (“…The controller unit 112 performs various processing according to instructions from the CPU 102. When the controller unit 112 receives an instruction "Start" from the CPU 102 to start processing, it performs, for example, byte code processing by the interpreter, stack operation in the stack memory unit 113 or, when a byte code that cannot be executed by the accelerator device 101 is fetched out, stops the accelerator device 101 (STOP) and notifies the CPU 102…First, when the CPU 102 enters an interpreter loop, it transmits the instruction "START" to the accelerator device 101, which, in turn, executes interpreter processing…When a thread is generated, a stack area to which the generated thread belongs is determined. These values are stored for respective threads. When a thread becomes the current thread, the data is always located in the same area (stack area) of the stack memory 113… The number of threads belonging to each stack area is known so that when a new thread is generated, it is allocated to a stack area with the least number of threads… Hereinafter, a method for allocating stack frames when the number of threads exceeds the number of partitioned areas of the stack memory unit 113 will be described with reference to FIGS. 2 to 4. First, when the number of the generated threads does not exceed the number of the partitioned areas of the stack memory unit 113, the generated threads are directly allocated to the stack areas of the stack memory unit 113…” paragraphs 0018/0022//0029/0031) and
assigning, at the first processor, a portion of the pool of memory to the new thread (“…When a thread is generated, a stack area to which the generated thread belongs is determined. These values are stored for respective threads. When a thread becomes the current thread, the data is always located in the same area (stack area) of the stack memory 113… The number of threads belonging to each stack area is known so that when a new thread is generated, it is allocated to a stack area with the least number of threads… Hereinafter, a method for allocating stack frames when the number of threads exceeds the number of partitioned areas of the stack memory unit 113 will be described with reference to FIGS. 2 to 4. First, when the number of the generated threads does not exceed the number of the partitioned areas of the stack memory unit 113, the generated threads are directly allocated to the stack areas of the stack memory unit 113…” paragraphs 0018/0022//0029/0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov, Jung, McGowen and Hanson with the teaching of Aoki because the teaching of Aoki would improve the system of Frolikov, Jung, McGowen and Hanson by providing a technique of allocating computing resources for optimal task processing.
As to claims 10 and 16, see the rejection of claim 1 above.
As to claims 13 and 19, see the rejection of claim 4 above.
As to claims 15 and 20, see the rejection of claim 9 above.
Claims 2, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0303040 A1 to Frolikov in view of U.S. Pub. No. 2003/0105927 A1 to Aoki and further in view of U.S. Pat. No. 9,063,668 B1 issued to Jung et al. and further in view of U.S. Pub. No. 6,427,195 B1 issued to McGowen et al. and further of U.S. Pub. No. 20180239711 A1 to Hanson et al. as applied to claims 1, 10 and 16 above, and further in view of U.S. Pub. No. 2008/0140979 A1 to A1 to Kim et al.
As to claim 2, Frolikov as modified by Aoki, Jung, McGowen and Hanson teaches the method of claim 1, however it is silent with reference to identifying that the new thread has ceased executing; and responsive to identifying that the new thread has ceased executing, releasing the portion of the pool of memory for use by a subsequently created thread of the host process.
Kim teaches identifying that the new thread has ceased executing; and responsive to identifying that the new thread has ceased executing, releasing the portion of the pool of memory for use by a subsequently created thread of the host process (“…One aspect of the present invention provides a method of dynamically allocated a stack in a multi-threaded sensor operating system environment, the method comprising the steps of: whenever a function is called while a thread is performing an operation, dynamically allocated a stack space to be used by the called function; and when execution of the function is finished, returning the allocates stack space…” paragraph 0015).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov, Aoki, Jung, McGowen and Hanson with the teaching of Zolnowsky because the teaching of Zolnowsky would improve the system of Frolikov, Aoki, Jung, McGowen and Hanson by providing a technique for managing and controlling resources allocation.
As to claims 11 and 17, see the rejection of claim 2 above.
Claims 3, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0303040 A1 to Frolikov in view of U.S. Pub. No. 2003/0105927 A1 to Aoki and further in view of U.S. Pat. No. 9,063,668 B1 issued to Jung et al. and further in view of U.S. Pub. No. 6,427,195 B1 issued to McGowen et al. and further of U.S. Pub. No. 20180239711 A1 to Hanson et al. as applied to claims 1, 10 and 16 above, and further in view of U.S. Pub. No. 20140095812 A1 to McLachan et al.
As to claim 3, Frollikov as modified by Aoki, Jung, McGowen and Hanson teaches the method of claim 1, however it is silent with reference to wherein the operations of creating, by the first processor, the new thread is executed responsive to a new thread creation command from an already existing thread executing on the first processor.
McLachan teaches wherein the operations of creating, by the first processor, the new thread (child thread) is executed responsive to a new thread creation command from an already existing thread (main thread) executing on the first processor (“…A process, which makes extensive use of the stack, can encounter "stack pressure" issues due to the fixed size allocation of the stack space. Each process can be launched with specific default stack size, which is designated for use by the main thread of the process. Each subsequent thread created can then be allocated its own default stack. Main thread default stack allocations can be in the Megabyte range, while child thread default stack sizes can be in the Kilobyte range…In one embodiment, a process main thread may be allocated an address range in a Static Stack Pool 522, while child threads can be allocated in the Dynamic Stack 524. In such embodiments, processes can be initialized and begin performing single threaded operations while a dynamic stack is allocated and prepared for additional threads of that process…” paragraphs 0031/ 0037).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov, Aoki, Jung, McGowen and Hanson with the teaching of McLachan because the teaching of McLachan would improve the system of Frolikov, Aoki, Jung, McGowen and Hanson by providing a technique for creating additional threads (child threads) when additional tasks needs to be performed to allow for optimal execution.
As to claims 12 and 18, see the rejection of claim 3 above.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0303040 A1 to Frolikov in view of U.S. Pub. No. 2003/0105927 A1 to Aoki and further in view of U.S. Pat. No. 9,063,668 B1 issued to Jung et al. and further in view of U.S. Pub. No. 6,427,195 B1 issued to McGowen et al. and further of U.S. Pub. No. 20180239711 A1 to Hanson et al. as applied to claims 1 and 10 above, and further in view of U.S. Pat. No. 4,766,537 A to Zlnowsky.
As to claim 5, Frollikov as modified by Aoki, Jung, McGowen and Hanson teaches the method of claim 1, however it is silent with reference to wherein reserving the pool of memory comprises setting a configuration status register.
Zolnowsky teaches wherein reserving the pool of memory comprises setting a configuration status register (“…a Change Stack bit in a Status Register is set to indicate that the processor should allocate a new stack for the called module…” Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov, Aoki, Jung, McGowen and Hanson with the teaching of Zolnowsky because the teaching of Zolnowsky would improve the system of Frolikov, Aoki, Jung, McGowen and Hanson by providing a technique for managing and controlling resources allocation.
As to claim 14, see the rejection of claim 5 above.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0303040 A1 to Frolikov in view of U.S. Pub. No. 2003/0105927 A1 to Aoki and further in view of U.S. Pat. No. 9,063,668 B1 issued to Jung et al. and further in view of U.S. Pub. No. 6,427,195 B1 issued to McGowen et al. and further of U.S. Pub. No. 2018/0239711 A1 to Hanson et al. as applied to claim 1 above, and further in view of U.S. Pub. No. 2021//0004456 A1 to Savry.
As to claim 6, Frollikov as modified by Aoki, Jung, McGowen and Hanson teaches the method of claim 1, however it is silent with reference to wherein the first processor executes a RISC-V instruction set.
Savry teaches wherein the first processor executes a RISC-V instruction set (“…By way of illustration, the microprocessor 2 has a RISC (Reduced Instructions Set Computer) architecture and implements the “RISC-V instruction set A pointer may also be generated during the execution of the binary code 30. This is notably the case when the binary code contains instructions that, when they are executed by the microprocessor 2, dynamically allocate a free memory region with a view to storing data therein. When such instructions are executed, they generate a pointer that points to the memory region. Here, such instructions are executed by the microprocessor 2 in the step 290 described below with reference to FIG. 6. Such instructions are frequently used to dynamically allocate a memory region in the heap 48…” paragraphs 0066/0096).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Frolikov, Aoki, Jung, McGowen and Hanson with the teaching of Savry because the teaching of Savry would improve the system of Frolikov, Aoki, Jung, McGowen and Hanson by providing an open-standard architecture with simplified instructions to the processor to accomplish various tasks.
Response to Arguments
Applicant's arguments filed 03/06/26 have been fully considered but they are not persuasive.
Applicants argued in substance that (1) the applied prior art does not teach or suggest "wherein assigning the portion of the pool of memory is performed without transmitting a memory request across the host interface for the portion of the pool of memory" and (2) the applied prior art does not teach or suggest "the portion of the pool of memory assigned to the new thread specified in the stack pool reservation request".
The Examiner disagrees.
As to point (1), the Hanson prior art discloses a Non-Volatile Dual In-Line Memory Module (NVDIMM) communicating with a host processor using a plurality of standardized memory-mapped submission queue and completion queue pairs. An exposed memory of the NVDIMM is exposed to the host processor for memory-mapped activities. Host processors post data Input/Output (I/O) requests from the an application to NVDIMM storage devices by moving commands and any associated data to assigned memory locations located within the host's Dynamic Random Access Memory (DRAM) address space. These assigned location addresses are host memory-mapped to the NVDIMM Submission Queues. NVDIMM devices may detect posted requests and retain them until device processing logic moves them into the device for fulfillment. In essence, the memory-mapped provides queues that maps the host's Dynamic Random Access Memory (DRAM) address space to the NVDIMM instead of direct communication between the host and the NVDIMM.
As to point (2), the Dragojevic and McGovern prior arts are applied to address the claim limitation of memory size of the request.
The Aoki prior art is applied to show the allocation or assignment of a stack memory to new or additional threads. The Aoki prior art discloses systems and methods for stack memory allocation to a plurality of threads. When a thread is generated, a stack area to which the generated thread belongs is determined. information are stored for respective threads. When a thread becomes the current thread, the data is always located in the same area (stack area) of the stack memory device. The number of threads belonging to each stack area is known so that when a new thread is generated, it is allocated to a stack area.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHARLES E ANYA/Primary Examiner, Art Unit 2194
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