DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Examiner acknowledges and accepts the amendment filed on 12/02/25.
Claims 1-2 are amended;
Claim 14 remains withdrawn; and
Claims 1-20 are currently pending.
Response to Arguments
Applicant’s arguments with respect to claims 1-13 and 15-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5-6, 9-10, 13 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over SAKAI et al. (US PG Pub 2022/0293545 A1) in view of JP2009117662A (herein JP’662, machine translation is provided) and Yokoyama (US PG Pub 2008/0193145 A1).
Regarding claim 1, SAKAI discloses a semiconductor light emitter (Fig. 2B) comprising:
a substrate (100, Fig. 2B, [0043]);
a semiconductor multilayer structure (300, Fig. 2B, where 300 is a semiconductor laser, [0044]) including a light emission unit that emits light; and
a shaping optical system (700, Fig. 2B, [0061]) held against the substrate (via 600, Fig. 2B, [0061]) to shape a luminous flux emitted from the semiconductor multilayer structure.
SAKAI does not disclose the light emission unit that emits light in an oblique direction with respect to the substrate; a base on which the substrate is disposed; and a holding member that holds the substrate at an angle set in advance with respect to the base.
JP’662 discloses a semiconductor light emitter (Figs. 18 and 20) comprising: a substrate (71, Fig. 18); a semiconductor multilayer structure (70, Fig. 18) including a light emission unit (3, Fig. 18) that emits light in an oblique direction with respect to the substrate (56˚ with respect to the substrate, Fig. 20); a base (302, Fig. 20) on which the substrate is disposed; a holding member (301, Fig. 20) that holds the substrate at an angle (θ6, Fig. 20) set in advance with respect to the base (see underlined portion on page 17 of machine translation).
JP’662 further discloses “By changing the emission direction in a direction substantially perpendicular to the upper surface 301a of the base portion 302 and using the surface emitting laser device 300 as a light source, the crystal growth surface has excellent flatness. Since a plurality of laser beams (nine) whose light scattering is suppressed by the plurality of reflecting surfaces 200c (9 places) are emitted, the surface emitting laser device 300 with improved light emission efficiency is provided.” (see underlined portion on page 16 of machine translation)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor light emitter of SAKAI with emitting light in an oblique direction with respect to the substrate via the inclined block disposed on the base as taught by JP’662 in order to obtain desired emission direction with improved light emission efficiency.
SAKAI does not disclose a temperature control unit disposed outside of and parallel to the substrate to adjust a temperature of the substrate.
Yokoyama discloses a temperature control unit (4, FIG. 6, [0030]) disposed outside of and parallel to the substrate (2, FIG. 6, [0030]) to adjust a temperature of the substrate (“The entire optical waveguide substrate 2 is mounted on the temperature controlling element 4 and the temperature controlling element 4 is capable of controlling the temperature of the entire substrate,” [0036]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor light emitter of SAKAI with attaching the temperature control unit under the substrate as taught by Yokoyama in order to obtain desired temperature control of the entire substrate.
Regarding claim 2, same rejection as applied to claim 1 is maintained since claim 2 contains substantially the same limitations as claim 1. The modified device also discloses the temperature control unit being disposed between the holding member and the substrate since the substrate of SAKAI is bonded to the holding member of JP’662.
Regarding claims 5-6, SAKAI, as modified, discloses in a case where a light emission angle with respect to the substrate in the semiconductor multilayer structure is θ1 (56˚ with respect to the substrate, Fig. 20 of JP’662) and an angle between a holding surface of the substrate and a mounting surface to the base in the holding member is θ2 (θ6, Fig. 20, where θ6 = 26˚ of JP’662), θ1+θ2 is 0°, 90°, or 180° (θ1+θ2 = 90°).
Regarding claims 9-10 and 13, SAKAI discloses the semiconductor multilayer structure and the substrate are electrically connected via an electrode pad (an electrode pad connecting 101 to 200, Fig. 2A) formed on the substrate.
Regarding claims 15, SAKAI, as modified, discloses the temperature control unit is disposed on a surface of the substrate opposite to a holding surface of the semiconductor multilayer structure (4 is mounted on a bottom surface of 2, FIG. 6 of Yokoyama).
Regarding claim 16, SAKAI discloses the substrate is provided with a thermal via portion (104/107, Fig. 2B, [0055]) in a disposition region of the semiconductor multilayer structure, and the thermal via portion includes a plurality of thermal via groups (a first group of 104 and a second group of 107, Fig. 2B) consisting of a plurality of thermal vias (Fig. 2B), and the plurality of thermal vias in the thermal via group are connected by solid wiring (103, Fig. 2B, [0053]) for each thermal via group.
Regarding claim 17, SAKAI discloses a spacing between the thermal via groups adjacent to each other is wider than a spacing between the thermal vias adjacent to each other in the thermal via group (a spacing between the groups 104/107 is wider than thermal vias within the group, Fig. 2B).
Regarding claim 18, SAKAI discloses a spacing between the thermal vias adjacent to each other in a longitudinal direction is uniform in the thermal via group (a spacing within the thermal vias in the thermal via groups is uniform, Fig. 2B).
Claims 3-4, 7-8 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over SAKAI et al., JP’662 and Yokoyama as applied to claims 1-2 above, and further in view of KONDO et al. (US PG Pub 2018/0059586 A1).
Regarding claims 3-4, the combination has disclosed the semiconductor light emitter outlined in the rejection to claims 1-2 above except the semiconductor multilayer structure includes a light amplification unit that amplifies the light propagating in an extended direction. KONDO discloses the semiconductor multilayer structure (10, FIG. 1B, [0030]) includes a light amplification unit (14, FIG. 1B, [0030]) that amplifies the light propagating in an extended direction. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor multilayer structure of the combination with including the light amplification unit that amplifies the light propagating in an extended direction as taught by KONDO in order to obtain amplified output.
Regarding claims 7-8, the combination discloses in a case where a light emission angle with respect to the substrate in the semiconductor multilayer structure is θ1 (56˚ with respect to the substrate, Fig. 20 of JP’662) and an angle between a holding surface of the substrate and a mounting surface to the base in the holding member is θ2 (θ6, Fig. 20, where θ6 = 26˚ of JP’662), θ1+θ2 is 0°, 90°, or 180° (θ1+θ2 = 90°).
Regarding claims 11-12, SAKAI discloses the semiconductor multilayer structure and the substrate are electrically connected via an electrode pad (an electrode pad connecting 101 to 200, Fig. 2A) formed on the substrate.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over SAKAI et al. and JP’662 as applied to claim 15 above, and further in view of McDonald et al. (US PG Pub 2007/0002926 A1).
Regarding claim 19, the combination has disclosed the semiconductor light emitter outlined in the rejection to claim 15 above and SAKAI further discloses the substrate includes a driver circuit (200, Fig. 2B, [0043]) that controls the semiconductor multilayer structure except a temperature measurement unit that measures a temperature of the substrate, and the temperature measurement unit is disposed between the driver circuit and the semiconductor multilayer structure on the substrate. McDonald discloses a thermally responsive substrate comprises an embedded thermal heater and an embedded temperature monitor (see claim 12). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the substrate of the combination with the temperature measurement unit that measures a temperature of the substrate as taught by McDonald in order to obtain temperature feedback control of the substrate. It also would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to place the temperature measurement unit between the driver circuit and the semiconductor multilayer structure on the substrate in order to obtain more accurate temperature reading, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Allowable Subject Matter
Claim 20 is allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUANDA ZHANG whose telephone number is (571)270-1439. The examiner can normally be reached M-F 10:30 AM - 6:30 PM.
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/YUANDA ZHANG/Primary Examiner, Art Unit 2828