Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is non-final and is in response to claims filed on 04/19/2022 and the response to the restriction requirement filed 11/10/2025. Claims 1-4 are pending for examination. The applicant’s response was not clear on how to treat claim 5. For examination purposes, claim 5 is being withdrawn from consideration in light of the election of claims 1-4.
Specification
The disclosure is objected to because of the following informalities:
The specification, in paragraph [0005], recites “using the Low-Discrepancy (LD) deterministic method of SC”, however, all acronyms must be spelled out the first time they are used. The specification should recite “using the Low-Discrepancy (LD) deterministic method of stochastic computing (SC)”.
The specification, table I page 14, references methods from different authors, however, the specification does not mention the titles or cite these references anywhere.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites “converting the data to Low Discrepancy (LD) bit-streams”. However, this should read “converting the input data to Low Discrepancy (LD) bit-streams”.
Claim 1 recites “performing multiplication by bitwise operations in a parallel manner”. However, this should read “performing multiplication on the LD bit-streams by bitwise operations in a parallel manner”.
Claim 1 recites “performing multiplication using Memory Aided Logic”. However, this should read “performing multiplication on the bitstreams using Memory Aided Logic”.
Appropriate correction is required.
Claim Interpretation
Claim 1 is directed to a method that recites conditional language. Claim 1 recites “converting each N-bit binary data to a (2N-1)2 bit bitstream for two-input exact (full-precision) and to a (2N - 1) bit bit-stream for limited-precision multiplication”.
The conditional nature of this claim language allows for an interpretation where any prior art meets the broadest reasonable interpretation of the claim without having the conditional language even occurring (and thus only the preceding limitations required by the prior art). For example, in claim 1, the method could require 0, 1, or 2 conversions to take place. See MPEP 2111.04(II); see also Ex parte Schulhauser. Examiner notes that the broadest reasonable interpretation of the method of claim 1 requires 0, 1, or 2 conversions to take place. Examiner encourages claim amendments that specifically removes the conditional language of the claims and thus expressly has the claimed scenarios occur. Examiner respectfully reiterates that without changing the conditional nature of the claim, the method claims carry no patentable weight as noted above.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "converting each N-bit binary data". There is insufficient antecedent basis for this limitation in the claim. The claims does not state “N-bit binary data”. For examination purposes, examiner has interpreted “providing input data in binary-radix format” as “providing N-bit binary input data in binary-radix format” and “converting each N-bit binary data” as “converting each N-bit binary input data”.
Claim 1 recites “converting each N-bit binary data to a (2N-1)2 bit bitstream for two-input exact (full-precision) and to a (2N - 1) bit bit-stream for limited-precision multiplication”. It is unclear if the claim requires both conversions to be performed or if there us a determination as to the type of precision prior to the conversion.
Claim 1 recites “performing multiplication by bitwise operations in a parallel manner” and “performing multiplication using Memory Aided Logic”. It is unclear if these multiplications are the same operation or two distinct operations. For examination purposes, examiner has interpreted “performing multiplication using Memory Aided Logic” as “performing the multiplication using Memory Aided Logic”.
Claim 1 recites “converting the data to Low Discrepancy (LD) bit-streams” and “converting each N-bit binary data to a”. It is unclear if these conversions are the same operation or different operations.
Claims 2-4 are rejected for being dependent on an above rejected claim.
Claim Rejections - 35 USC § 101
Claims 1-4 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 1, at step 1, the claim is directed to a method, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A method of exact Stochastic Computing - based multiplication in memristive memory, comprising: (mental process, evaluation)
(1) providing input data in binary-radix format; (mental process, evaluation; mathematical relationship)
(2) converting the data to Low Discrepancy (LD) bit-streams by using LD distributions; (mathematical calculation)
(3) performing multiplication (mathematical calculation) by bitwise operations in a parallel manner; (mental process, evaluation)
(4) converting each N-bit binary data to a (2N-1)2 bit bitstream for two-input exact (full-precision) and to a (2N - 1) bit bit-stream for limited-precision multiplication; (mathematical calculation)
(5) performing multiplication (mathematical calculation) using Memory Aided Logic; and (mental process, evaluation)
(6) preserving the output in memory in bit-stream format. (mental process, evaluation; mathematical relationship)
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “A method of exact Stochastic Computing - based multiplication in memristive memory, comprising” limitation is an evaluation mental process that can be performed by choosing what the method comprises. The “input data in binary-radix format” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing the format of the inputs. The “converting the data to Low Discrepancy” limitation is a mathematical calculation that can be performed by converting the data by hand using pen and paper. The “performing multiplication” limitation is a mathematical calculation that can be performed by performing the multiplication by hand using pen and paper. The “by bitwise operations in a parallel manner” limitation is an evaluation mental process that can be performed by choosing how the multiplication is performed. The “converting each N-bit binary data to” limitation is a mathematical calculation that can be performed by converting the binary data by hand using pen and paper. The “performing multiplication” limitation is a mathematical calculation that can be performed by performing the multiplication by hand using pen and paper. The “using Memory Aided Logic” limitation is an evaluation mental process that can be performed by choosing how the multiplication is performed. The “preserving the output” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what to do with the output.
At step 2A Prong 2, the additional elements are bolded above. The “providing” limitation, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘providing’ in the context of the claim encompasses mere data gathering. The “preserving” limitation, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘preserving’ in the context of the claim encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “providing input data in binary-radix format”, “preserving the output in memory”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 2, it is directed to mental processes and/or mathematical concepts. The “further comprising” limitation is an evaluation mental process that can be performed by choosing what the method comprises. The “converting the output from bit-stream format to binary format” limitation is a mathematical calculation that can be performed by converting the output by hand using pen and paper. Under steps 2A prong 2 and 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 3, it is directed to mental processes and/or mathematical concepts. The “wherein the output is converted from bit-stream format to binary format” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing how the conversion is performed and converting the output by hand using pen and paper. Under step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. in-memory conversion, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 4, it is directed to mental processes and/or mathematical concepts. The “wherein the output is converted from bit-stream format to binary format” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing how the conversion is performed and converting the output by hand using pen and paper. Under step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. off-memory conversion, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Jong-Eun et al. (machine translation of KR 102023095 B1) hereinafter Jong-Eun in view of Rosing et al. (US 20220019441 A1) hereinafter Rosing further in view of Salehi et al. (“Low-correlation Low-cost Stochastic Number Generators”) hereinafter Salehi.
With regards to claim 1, Jong-Eun teaches A method of exact Stochastic Computing - based multiplication [in memristive memory,] comprising: (Jong-Eun Page 1 Abstract: The present invention is a Stochastic Computing (SC) multiplier using a stochastic computing multiplication algorithm)
(1) providing input data in binary-radix format; (Jong-Eun Page 1 Abstract: which obtains a first input (x) and converts a binary number into a stochastic number)
(2) converting the data to Low Discrepancy (LD) bit-streams by using LD distributions; (Jong-Eun Page 1 Abstract: which obtains a first input (x) and converts a binary number into a stochastic number; Jong-Eun Page 3 Paragraph 7: In summary, the accuracy is improved over previous work by i) the new SC multiplication algorithm of the present invention and ii) the use of the new low-discrepancy Stochastic Number Generator (SNG) scheme of the present invention; Jong-Eun Page 4 Paragraph 3: In SC, numbers (called stochastic numbers, or SNs) are represented as bit streams)
(3) performing multiplication by bitwise operations in a parallel manner; (Jong-Eun Page 6 Paragraph 3: In the following, the SC multiplier of the present invention describes how to optimize bit parallelism. To reduce the latency of the SC multiplier of the present invention, bit parallel processing can be proposed)
(4) converting each N-bit binary data [to a (2N-1)2 bit bitstream for two-input exact (full-precision) and to a (2N - 1) bit bit-stream for limited-precision multiplication;] (Jong-Eun Page 1 Abstract: which obtains a first input (x) and converts a binary number into a stochastic number; Jong-Eun Page 4 Paragraph 3: In SC, numbers (called stochastic numbers, or SNs) are represented as bit streams)
(5) performing multiplication [using Memory Aided Logic;] (Jong-Eun Page 1 Abstract: The present invention is a Stochastic Computing (SC) multiplier using a stochastic computing multiplication algorithm)
and (6) preserving the output [in memory] in bit-stream format (Jong-Eun Page 2 paragraph 8: First, the SC multiplier 110 of the present invention obtains a first input (x) and a second input (w) to provide an SC multiplier for outputting x .Math. w by stochastic computing).
Jong-Eun fails to teach that the multiplication occurs in memristive memory, performing the multiplication using Memory Aided Logic, and [preserving the output] in memory.
However, Rosing teaches that the multiplication of Jong-Eun occurs in memristive memory (Rosing [0488]: We disclose, herein, SCRIMP, an architecture for stochastic computing acceleration with resistive RAM (ReRAM) in-memory processing, which enables SC in memory)
performing the multiplication of Jong-Eun using Memory Aided Logic (Rosing [0488]: We disclose, herein, SCRIMP, an architecture for stochastic computing acceleration with resistive RAM (ReRAM) in-memory processing, which enables SC in memory).
[preserving the output] of Jong-Eun in memory (Rosing [0488]: We disclose, herein, SCRIMP, an architecture for stochastic computing acceleration with resistive RAM (ReRAM) in-memory processing, which enables SC in memory; Rosing [0520]: The operation can be executed in parallel for the entire bit-stream, bi, and takes just one cycle to compute the final output)
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Jong-Eun with the in memory computing of Rosing. One of ordinary skill in the art would be motivated to make this combination because SCRIMP is more power efficient than all DNN accelerators being 3.2×, 2.4×, and 6.3× better than DaDianNao, ISAAC, and PipeLayer, respectively as taught by Rosing (Rosing [0551]).
Jong-Eun in view of Rosing fails to teach [(4) converting each N-bit binary data] to a (2N-1)2 bit bitstream for two-input exact (full-precision) and to a (2N - 1) bit bit-stream for limited-precision multiplication.
However, Salehi teaches [(4) converting each N-bit binary data] to a (2N-1)2 bit bitstream for two-input exact (full-precision) and to a (2N - 1) bit bit-stream for limited-precision multiplication (Salehi Page 2 Section I: Normally, LFSR is designed to have the maximum sequence length of 2N-1).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Jong-Eun in view of Rosing with the bit-stream length as taught by Salehi. One of ordinary skill in the art would be motivated to make this combination because it would reduce the amount of bits needed for calculating the results making calculations faster.
With regards to claim 2, Jong-Eun in view of Rosing further in view of Salehi teaches all of the limitations of claim 1 above. Jong-Eun further teaches further comprising converting the output from bit-stream format to binary format (Jong-Eun Page 4 paragraph 3: Finally, the bit counter converts unipolar SNs to BNs).
With regards to claim 3, Jong-Eun in view of Rosing further in view of Salehi teaches all of the limitations of claim 2 above. Jong-Eun fails to teach wherein the output is converted from bit-stream format to binary format using in-memory conversion.
However, Rosin teaches wherein the output is converted from bit-stream format to binary format using in-memory conversion (Rosing [0505]: SCRIMP architecture consists of multiple ReRAM crossbar memory blocks grouped into multiple banks; Rosing [0507]: Any stochastic application may have three major phases, (i) binary to stochastic conversion (B2S), (ii) stochastic logic computation, (iii) stochastic to binary (S2B) conversion... Digital PIM techniques combined with memory peripherals enable logic computation in memory and S2B conversion in SCRIMP).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Jong-Eun in view of Rosing further in view of Salehi with converting the output in memory as taught by Rosing. One of ordinary skill in the art would be motivated to make this combination it would speed up the operation of the system as the data would not need to be transferred to different components. Also, because SCRIMP is more power efficient than all DNN accelerators being 3.2×, 2.4×, and 6.3× better than DaDianNao, ISAAC, and PipeLayer, respectively as taught by Rosing (Rosing [0551]).
With regards to claim 4, Jong-Eun in view of Rosing further in view of Salehi teaches all of the limitations of claim 2 above. Jong-Eun further teaches wherein the output is converted from bit-stream format to binary format using off-memory conversion (Jong-Eun Page 4 paragraph 3: Finally, the bit counter converts unipolar SNs to BNs).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jakob O Gudas whose telephone number is (571)272-0695. The examiner can normally be reached Monday-Thursday: 7:30AM-5:00PM Friday: 7:30AM-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151