Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed February 17, 2026 have been fully considered but they are not persuasive.
In response to Applicant's argument on page 6 – 7 pertaining to “The Office Action states, "In analogous art, Hinger teaches, - one or more processors (Fig. 5, ¶ 57 DSP, or a processor) configured to execute code that cause the one or more processors to: generate a trigger gating signal (Fig. 5, ¶ 58 Trigger 1, and Trigger 2) for the row selection circuit (Fig. 5, ¶ 58 row controller) and the column selection circuit (Fig. 5, ¶ 58 column controller); and produce the sample clock (Fig. 6, ¶ 59 ultrasonic signal 614) for the row selection circuit and the column selection circuit ..." … There is no indication anywhere in Hinger that the trigger signals are sent to the row and column controller. See FIG. 5. The trigger signals appear to be sent to the pixels to effect the capture of the return signal.”. The Examiner respectfully disagrees.
As mentioned in this Office Action (OA), the Examiner does not rely on Hinger, the Examiner relies on Simeoni. Simeoni teaches, — one or more processors (Fig. 6, static interferometry system “the system inherently has processor since it samples signals”) configured to execute code that cause the one or more processors to: generate a trigger gating signal (Fig. 7b, ¶ 58 triggers a sampling of the signals S i, j) for the row selection circuit (Fig. 7b, ¶ 58 row index i, detector matrices MD1 and MD2) and the column selection circuit (Fig. 7b, ¶ 58 column index j, detector matrices MD1 and MD2); and produce the sample (Fig. 7b, ¶ 58 sample acquired (sample k)) clock for the row selection circuit and the column selection circuit; —
In response to Applicant's argument on page 7 pertaining to “Claim 15 depends from claim 14. For the reasons discussed above, the combination of Pickerd, Hinger, and Varughese does not teach all the elements of the invention as claimed in claim 14, much less the further features of the dependent claims. The addition of Levinson does not cure these deficiencies.”
As mentioned above, the Examiner does not rely on Hinger, the Examiner does not rely on Hinger, the Examiner relies on Simeoni.
In response to Applicant's argument on page 7 pertaining to “Claim 17 depends from claim 14. For the reasons discussed above, the combination of Pickerd, Hinger, and Varughese does not teach all the elements of the invention as claimed in claim 14, much less the further features of the dependent claims. The addition of Odedara does not cure these deficiencies.”
As mentioned above, the Examiner does not rely on Hinger, the Examiner does not rely on Hinger, the Examiner relies on Simeoni.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14, 16, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pickerd (US 2005/0273284 A1) (herein after Pickerd) in view of Simeoni et al (US 2011/0032531 A1) (herein after Simeoni), and further in view of Varughese et al (US 2022/0407595 A1) (herein after Varughese).
Regarding Claim 14, Pickerd teaches, a test and measurement system (Fig. 1, ¶ 14 test and measurement device), comprising: a flash array digitizer (Fig. 1, a flash array digitizer (FAD) 100) comprising: an array of counters having rows and columns configured to store a waveform image representing a signal received from a device under test (Fig. 1, ¶ 21 counter array 150, N rows and M columns; ¶ 14 signal under test (SUT)); a row selection circuit (Fig. 1, delay lines 140) configured to select a row in the array of counters (Fig. 1, ¶ 22 rows in the array are enabled by the output of the logic element); and a column selection circuit (Fig. 1, sweep flip-flops 166) configured to select a column in the array of counters (Fig. 1, ¶ 22 rows in the array are enabled by the output of the logic element); a sample clock (Fig. 1, ¶ 29 clock signal (e.g., the sweep clock signal SWPCLK)) connected to the row selection circuit and the column selection circuit to determine when a sample of the signal is captured; —.
Pickerd fails to teach, — one or more processors configured to execute code that cause the one or more processors to: generate a trigger gating signal for the row selection circuit and the column selection circuit; and produce the sample clock for the row selection circuit and the column selection circuit; and a machine learning system configured to receive the waveform image from the flash array digitizer and provide operating parameters for the device under test.
In analogous art, Simeoni discloses, — one or more processors (Fig. 6, static interferometry system) configured to execute code that cause the one or more processors to: generate a trigger gating signal (Fig. 7b, ¶ 58 triggers a sampling of the signals S i, j) for the row selection circuit (Fig. 7b, ¶ 58 row index i, detector matrices MD1 and MD2) and the column selection circuit (Fig. 7b, ¶ 58 column index j, detector matrices MD1 and MD2); and produce the sample (Fig. 7b, ¶ 58 sample acquired (sample k)) clock for the row selection circuit and the column selection circuit; —
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Varughese by combining the test and measurement system taught by Varughese with a test and measurement system comprising: one or more processors configured to execute code that cause the one or more processors to: generate a trigger gating signal for the row selection circuit and the column selection circuit; and produce the sample clock for the row selection circuit and the column selection circuit; disclosed by Simeoni for the benefit of sampling a signal while decreasing the impact of non-uniformities of the detection device. [Simeoni: ¶ 72].
Pickerd in view of Simeoni fail to teach, — and a machine learning system configured to receive the waveform image from the flash array digitizer and provide operating parameters for the device under test.
In analogous art, Varughese teaches, — and a machine learning system (Fig. 1, ¶ 32 neural network 155b) configured to receive the waveform image from the flash array digitizer and provide operating parameters for the device under test (Fig. 1, ¶ 32 generate parameters of the transmitter under test 110b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pickerd in view of Simeoni by combining the test and measurement system taught by Pickerd in view of Simeoni with a test and measurement system comprising: a machine learning system configured to receive the waveform image from the flash array digitizer and provide operating parameters for the device under test; taught by Varughese for the benefit of reducing overfitting and improving generalization error in machine learning [Varughese: ¶ 47].
Regarding Claim 16, Pickerd in view of Simeoni in view of Varughese teaches the limitations of claim 14, which this claim depends on.
Pickerd further teaches, the test and measurement system as claimed in claim 14, further comprising a preamplifier (Fig. 1, ¶ 15 plurality of comparators 120) and a track and hold circuit (Fig. 1, ¶ 56 sample/hold circuitry may be used) connected to each of the row selection circuit and the column selection circuit, the track and hold circuit also connected to the sample clock.
Regarding Claim 19, Pickerd in view of Simeoni in view of Varughese teaches the limitations of claim 14, which this claim depends on.
Pickerd further teaches, the test and measurement system as claimed in claim 14, wherein the machine learning system is configured to operate on unfiltered waveform image data (Fig. 1, ¶ 27 acquired samples associated with the SUT, without ever converting them to a binary format.).
Regarding Claim 20, Pickerd in view of Simeoni in view of Varughese teaches the limitations of claim 14, which this claim depends on.
Pickerd further teaches, the test and measurement system as claimed in claim 14, wherein the machine learning system is configured to operate on filtered waveform image data (Fig. 3, ¶ 46 data post processing route 326PP, filtering routines (box car filtering, low pass filtering, high pass filtering, and the like)).
Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Pickerd (US 2005/0273284 A1) (herein after Pickerd) in view of Simeoni et al (US 2011/0032531 A1) (herein after Simeoni), in view of Varughese et al (US 2022/0407595 A1) (herein after Varughese), and further in view of Levinson et al (US 2003/0053170 A1) (herein after Levinson).
Regarding Claim 15, Pickerd in view of Simeoni in view of Varughese teaches the limitations of claim 14, which this claim depends on.
Pickerd in view of Simeoni in view of Varughese fail to teach, the test and measurement system as claimed in claim 14, wherein the row selection circuit and the column selection circuit comprise analog-to-digital converters.
In analogous art, Levinson teaches, the test and measurement system as claimed in claim 14, wherein the row selection circuit and the column selection circuit comprise analog-to-digital converters (Fig. 7A, ¶ 64 circuit board 704; Fig. 5, ¶ 61 multiplexer (mux) 530).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pickerd in view of Simeoni in view of Varughese by combining the test and measurement system taught by Pickerd in view of Simeoni in view of Varughese with a row selection circuit and a column section circuit wherein, the row selection circuit and the column selection circuit comprise analog-to-digital converters; taught by Levinson for the benefit of a highly flexible interface between an optoelectronic device and a host device. [Levinson: ¶ 7].
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Pickerd (US 2005/0273284 A1) (herein after Pickerd) in view of Simeoni et al (US 2011/0032531 A1) (herein after Simeoni), and further in view of Varughese et al (US 2022/0407595 A1) (herein after Varughese), and further in view of Odedara et al (US 2017 /0038264 A1) (herein after Odedara).
Regarding Claim 17, Pickerd in view of Simeoni in view of Varughese teaches the limitations of claim 14, which this claim depends on.
Pickerd in view of Simeoni in view of Varughese fail to teach, the test and measurement system as claimed in claim 14, wherein the row selection circuit and the column selection circuit comprise flash converters, each flash converter comprising a voltage divider circuit and a stack of comparators to output a thermometer code, and a series of logic gates configured to receive the thermometer code and produce a row selection signal to select a row in the array of counters.
In analogous art, Odedara teaches, wherein the row selection circuit and the column selection circuit comprise flash converters (Fig. 1, ¶ 36 a digital logic circuit, an analog circuit), each flash converter comprising a voltage divider circuit and a stack of comparators (Fig. 1, ¶ 32 divider value N) to output a thermometer code (Fig. 1, ¶ 33 the divider signal), and a series of logic gates configured to receive the thermometer code and produce a row selection signal to select a row in the array of counters (Fig. 1, ¶ 33 a counter module).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pickerd in view of Simeoni in view of Varughese by combining the test and measurement system taught by Pickerd in view of Simeoni in view of Varughese with a row selection circuit and column selection circuit wherein, the row selection circuit and the column selection circuit comprise flash converters, each flash converter comprising a voltage divider circuit and a stack of comparators to output a thermometer code, and a series of logic gates configured to receive the thermometer code and produce a row selection signal to select a row in the array of counters; taught by Odedara for the benefit of reducing noise on a measurement signal to accurately reflect a temperature [Odedara: ¶ 25].
Allowable Subject Matter
Claims1 – 13 are allowed.
The following is an Examiner's statement for reasons for allowance:
Applicant’s remark filed on September 25, 2025, with respect to the independent claim 1 have been fully considered and the claims are allowable.
Applicant argues on pages 10 – 11 of the remarks regarding the rejection of independent claim 1 under 35 U.S.C § 103 as being unpatentable over Pickerd (US 2005/0273284 A1) (herein after Pickerd) in view of Malkin (US 9,071,262 B1) (herein after Malkin) in view of Varughese et al (US 2022/0407595 A1) (herein after Varughese) that “The sweep circuit in Pickerd is not an "equivalent time" sweep mechanism as in the instant application, which is discussed in many places (paragraphs 0013, 0017, 0020, among others), which relies upon a pattern trigger output based upon pattern in the waveform to increment the sweep clock and implement the delay. The trigger in Pickerd is not based upon a pattern. The description in paragraph 20 discloses that the delay used is to ensure that "a subsequent display of the digitized signal includes portions of the signal preceding a triggering event." The triggering event results from a trigger threshold established by a D/A converter to enable the storage of data. Any delay between the trigger events and data acquisition are done "such that a subsequent display of the acquired data is presented or displayed to a user in a more easily understood or recognizable form." Pickerd does not show, teach, or suggest, that "the offset equal to one sample intervale of a final equivalent time sample rate." Pickerd therefore cannot show that the sweep logic circuit receives the pattern trigger signal and the end of row signals to produce the clock signal with a delay ... " No pattern trigger signal exists in Pickerd, and no need for a clock recovery circuit, as the system of Pickerd has a clock, see FIG. 1.”
Applicant’s argument regarding the rejection of independent claims 1 – 13 under 35 U.S.C § 103 as being unpatentable over Pickerd (US 2005/0273284 A1) (herein after Pickerd) in view of Malkin (US 9,071,262 B1) (herein after Malkin) in view of Varughese et al (US 2022/0407595 A1) (herein after Varughese) is persuasive because of the applicant’s arguments filed on September 25, 2025. Therefore, the rejection of claim 1 has been withdrawn.
Claims 1 – 13 are allowed in view of the applicant’s arguments filed on September 25, 2025.
The closest prior art considered is Pickerd (US 2005/0273284 A1) (herein after Pickerd), Malkin (US 9,071,262 B1) (herein after Malkin), and Varughese et al (US 2022/0407595 A1) (herein after Varughese).
Regarding Claim 1, Pickerd teaches, a test and measurement system (Fig. 1, ¶ 14), comprising: — a flash array digitizer (Fig. 1) comprising: an array of counters having rows and columns configured to store a waveform image representing the signal received from the device under test (Fig. 1, ¶ 21; ¶ 14); a row selection circuit configured to select a row in the array of counters (Fig. 1, ¶ 22); and a ring counter circuit (Fig. 1) configured to receive a clock signal, select a column (Fig. 1, ¶ 29) in the array of counters, produce end of row signals, produce a fill complete signal (Fig. 1, ¶ 42) upon all of the columns having been swept, the fill complete signal indicating completion of the waveform image (Fig. 1, ¶ 42);.
Malkin teaches, — comprising: a clock recovery circuit (Fig. 1) configured to receive a signal from a device under test and to produce a pattern trigger signal (Fig. 1. Col. 11. Ln. 30-31) based upon a repeating pattern having a record length N (Fig. 1. Col. 10. Ln. 24-25);
Varughese teaches, — and a machine learning system (Fig. 1B, ¶ 32) configured to receive the waveform image and provide operating parameters for the device under test (Fig. 1, ¶ 32).
The prior art does not teach or suggest, alone or in combination with the rest of the limitations in the claim: “and an equivalent time sweep logic circuit configured to receive the pattern trigger signal and the end of row signals from the ring counter and to produce the clock signal with a delay with respect to a reference position of the pattern trigger signal to increment a clock delay to the ring counter until the fill complete signal is received, the end of row signals resulting in an offset equal to one sample interval of a final equivalent time sample rate;”
Claims 2 – 6, 8, and 10 – 13 are allowable due to their dependencies on claim 1. Claim 7 is allowable due to its dependency on claim 6. Claim 9 is allowable due to its dependency on claim 8.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. SEPP (US 20090121762 A1) a test and measurement system (Fig. 5, oscilloscope 500).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH O. NYAMOGO whose telephone number is (469)295-9276. The examiner can normally be reached 9:00 A to 5:00 P CT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALFAKAWI can be reached at 571-272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH O. NYAMOGO/
Examiner
Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 5/7/2026
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