DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
Response filed on 6 June 2025 has been entered. Applicant has canceled claim 5, amended claims 1, 2, and 9. Claims 11-21 remain withdrawn. Claims 1-4, and 6-21 are pending.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12 June 2025 has been considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 6-10 rejected under 35 U.S.C. 103 as being unpatentable over Odnoblyudov et al. US PGPUB 20180114726 (hereinafter Odnoblyudov) in view of Kweskin US PGPUB 20190057897 (hereinafter Kweskin) and Arikado et al. US PGPUB 20030003608 (hereinafter Arikado).
Regarding claim 1, Odnoblyudov discloses (fig. 1-4) a semiconductor structure comprising:
a first <111>-oriented silicon (Si) wafer substrate (320 ¶59);
a second Si wafer substrate (125 ¶56, 58-62) bonded to the first <111>-oriented Si wafer substrate; and
a gallium nitride (GaN) epitaxial layer (410/420 ¶60) grown on a top side of the first<111>-oriented Si wafer substrate.
Odnoblyudov discloses use of single crystal substrates, but is silent on the edge bevel and use of wafer ID marks. Therefore, Odnoblyudov does not disclose wherein a top side of the second Si wafer substrate is bonded to a bottom side of the first Si wafer substrate, bottom sides of both Si wafer substrates contain a wafer ID mark, and each Si wafer substrate has a C-bevel edge.
In the same field of endeavor, Kweskin discloses (fig. 2) wherein a top side of the second Si wafer substrate (100, Kweskin ¶26-27) is bonded to a bottom side of the first Si wafer substrate (500, Kweskin ¶36-37) and each Si wafer substrate has a C-bevel edge (Kweskin fig. 2, where each single crystal wafer substrate is shown with a C-bevel edge shape).
It would have been obvious to one of ordinary skill in the art at the time of filing for the single crystal wafer substrates of Odnoblyudov to retain the circumferential edge and curved bevel disclosed by Kweskin, providing improved reliability by not machining the curved bevel of the standard single crystal wafer and introducing additional defects.
Odnoblyudov in view of Kweskin does not disclose bottom sides of both Si wafer substrates contain a wafer ID mark.
In the same field of endeavor, Arikado discloses (fig. 13-14) a wafer ID mark (44) on the bottom side of a Si wafer substrate (42) (Arikado ¶187) denoting crystal orientation (Arikado ¶16). It would have been obvious to one of ordinary skill in the art at the time of filing to use the ID marking of Arikado on the wafer substrates, allowing for positive identification of the crystal orientation, ensuring use of the desired GaN growth surface of <111>-oriented silicon and reducing cost by not requiring each wafer to be <111>-oriented silicon.
Regarding claim 2, Odnoblyudov in view of Kweskin and Arikado discloses the semiconductor structure of claim 1,
wherein the semiconductor structure has a B-bevel edge (Kweskin fig. 2, where a B-bevel edge shape is shown by the joined C-bevel edge wafer substrates).
Regarding claim 3, Odnoblyudov in view of Kweskin and Arikado discloses the semiconductor structure of claim 1 further comprising:
an intermediate silicon dioxide (SiO2) layer between the first Si wafer substrate and the second Si wafer substrate (Kweskin discloses a dielectric layer, 420 "may include silicon nitride, silicon oxide, silicon oxynitride, and combinations of these materials." Kweskin ¶22)
It would have been obvious to one of ordinary skill in the art at the time of filing for the high-quality thermal oxide of Odnoblyudov to made of silicon dioxide, providing a low-cost dielectric bonding layer between the silicon single crystal wafer substrates.
Regarding claim 4, Odnoblyudov in view of Kweskin and Arikado discloses the semiconductor structure of claim 3,
wherein the intermediate SiO2 layer has a thickness of at least 100 nm (Kweskin ¶39). It would have been obvious to one of ordinary skill in the art at the time of filing for the dielectric silicon oxide layer to have the thickness disclosed by Kweskin, providing improved device versatility by using the layer(s) as “as an etch stop, diffusion barrier, optical component, or hard mask,” (Kweskin ¶24).
Regarding claim 6, Odnoblyudov in view of Kweskin and Arikado discloses the semiconductor structure of claim 1,
wherein each Si wafer substrate is a 300 mm diameter wafer substrate (Kweskin ¶28). It would have been obvious to one of ordinary skill in the art at the time of filing for the wafer substrates to be of a diameter disclosed by Kweskin, reducing cost by using a standard size (Kweskin ¶28-29).
Regarding claim 7, Odnoblyudov in view of Kweskin and Arikado discloses the semiconductor structure of claim 1,
wherein a thickness across the two Si wafer substrates is at least 1.55 mm ( “the wafer thickness may be about 775 micrometers,” Kweskin ¶28, where two of these wafers would be at least 1.55 mm). Additionally, the instant application discloses that 300 mm diameter, 0.775 mm thickness wafers are a “standard size” (spec ¶13), where two 775 µm wafers bonded together would be at least 1.55 mm in thickness.
Regarding claim 8, Odnoblyudov in view of Kweskin and Arikado discloses the semiconductor structure of claim 1,
wherein a thickness of the GaN epitaxial layer is not more than 10 µm (“the GaN layer 420 may have a thickness of about 5 μm,” Odnoblyudov ¶60).
Regarding claim 9, Odnoblyudov in view of Kweskin and Arikado discloses the semiconductor structure of claim 1,
wherein a thickness of the first <111>-oriented Si wafer substrate is approximately 0.775 mm (Kweskin ¶28).
Regarding claim 10, Odnoblyudov in view of Kweskin and Arikado discloses the semiconductor structure of claim 1,
wherein the second Si wafer substrate (125) is a <100>-oriented Si wafer substrate (Odnoblyudov ¶56).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Seth Lawson whose telephone number is (703)756-5675. The examiner can normally be reached M-F 8-5 PST.
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/Seth D Lawson/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893