DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed on 11/25/2025 have been fully considered and are made of record.
Claim 20 has been amended.
Claim 22 has been cancelled.
Claims 5 and 17-19 have been withdrawn.
Claim 14 is allowable. The restriction requirement between species, as set forth in the Office action mailed on 5/28/2025, has been reconsidered in view of the allowability of claims to the elected invention pursuant to MPEP § 821.04(a). The restriction requirement is hereby withdrawn as to any claim that requires all the limitations of an allowable claim. Specifically, the restriction requirement of 5/28/2025 is partially withdrawn. Claim 17-18, directed to current sensor 400 comprising two amplifiers 210 and 310; DC level shift 220 is connected to output of 210 by transistor McH; Gated Averaging Sampling 290, transistors M2i, M2o are connected to drain of McH in Fig. 4 is no longer withdrawn from consideration because the claim(s) requires all the limitations of an allowable claim. However, claim 5, directed to Current sensor 300 comprises amplifiers 310, amplifier output node is connected to transistor McL, sense transistor MLs is connected to McL, Gated Averaging Sampling 291, transsitor M3i, M3o are connected to source of McL in Fig. 3 is withdrawn from consideration because it does not require all the limitations of an allowable claim.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Response to Arguments
Regarding claim 1, the rejection sent on Office Action mailed on 08/25/2025 has been withdrawn and new ground of rejection has been applied.
Regarding claims 14 and 20, applicant’s arguments filed on 11/25/2025 has been fully considered and are persuasive. Therefore the rejection sent on Office Action mailed on 08/25/2025 has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 7, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Sambucco et al. (Pub NO. US 2016/0124455 A1; hereinafter Sambucco) in view of Chen et al. (Pub NO. US 2019/0140630 A1; hereinafter Chen).
Regarding Claim 1, Sambucco discloses an apparatus, comprising:
a power converter (18-0 in Fig. 1) on a semiconductor die (See [0072] / note silicon die), the power converter comprises a switching transistor (18-2 in Fig. 1, See [0025] / note power transistor 18-2 in Fig. 1) ; and
a current sensor (12,14-1,18-1,18-3 in Fig. 1) comprising a first portion (18-3 in Fig. 1) on the semiconductor die and a second portion (12, 18-1 in Fig. 1) on a silicon die (See [0025], [0072] / note Sambucco reasonably implies that 18-0 can be on a die different than the current sense system),
wherein the first portion comprises a sense transistor (18-3 in Fig. 1, See [0025]), and
the second portion comprises an amplifier to control a current of the sense transistor based on a comparison of a voltage of the sense transistor to a voltage of the switching transistor (See [0025] / note the amplitude uses the voltage difference between 18-2 and 18-3 to control the load of 18-3 in Fig. 1, and thus control 18-3 in Fig. 1).
Sambucco describes that the circuitry can be formed on a single die or multiple dies (See [0072]),
However, Sambucco does not explicitly teach a power converter on a compound semiconductor die, a current sensor comprising a first portion on the compound semiconductor and a second portion on a silicon die.
Chen discloses a power converter (100) on a compound semiconductor die (See [0031] / note GaN die) (Figure 1), a current sensor (210,220, SW_SEN) comprising a first portion (SW_SEN) on the compound semiconductor and a second portion (210,220) on a silicon die (Fig. 1, See [0033]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date to modify Sambucco to separate the power converter from the remaining circuitry to therefore include a power converter on a compound semiconductor die, a current sensor comprising a first portion on the compound semiconductor and a second portion on a silicon die as taught by Chen in order to advantageously be able to keep cost low by using a low cost silicon device for the majority of the circuitry, but use a material that can handle higher voltages with less electrical breakdown and reduced energy losses as compared to Silicon for the power converter, thereby providing increased functionality as compared to silicon alone, as well as allowing the processing components of the current sensor and the other components on the GaN die to be able to process any signals faster.
Regarding Claim 2, Sambucco in view of Chen teaches the apparatus of claim 1. Sambucco further teaches wherein: the second portion comprises a control transistor (18-2 in fig. 1; See [0025]) coupled to the sense transistor (18-1 is coupled to 18-3 in fig. 1; See [0025]); the control transistor has a gate coupled to an output of the amplifier (gate of 18-1 is coupled to output of 12 in fig. 1); and to control the current of the sense transistor, the amplifier is to control a voltage at the gate of the control transistor (See [0025]-[0038]).
Regarding Claim 4, Sambucco in view of Chen teaches the apparatus of claim 2. Sambucco further teaches further comprising: a direct current level shifter coupled to the sense transistor and the control transistor (direct current level shifter 16-1 is coupled to 18-1 and 18-3 in Fig. 1; See [0043]).
Regarding Claim 7, Sambucco in view of Chen teaches the apparatus of claim 1. Sambucco further teaches wherein: a current of the sense transistor is scaled down relative to a current of the switching transistor by a scaling factor (current of 18-1 depends on current of 18-2, therefore these are related to scale down each other in Fig. 1; See [0049]-[0053]).
Regarding Claim 9, Sambucco in view of Chen teaches the apparatus of claim 1. Chen further teaches wherein: the compound semiconductor die comprises at least one of Gallium Nitride (GaN die; See [0031]), Silicon Carbide or Gallium Arsenide.
Regarding Claim 11, Sambucco in view of Chen teaches the apparatus of claim 1. Sambucco further teaches wherein: the silicon die comprises a gate driver for the switching transistor (gate driver 14-1 to drive gate voltage of 18-2 in Fig. 1).
Reason for Allowance/ Allowable Subject Matter
Claims 3, 6, 8, 10 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 3, none of the prior art fairly teaches or suggests the apparatus of claim 2, wherein: the current sensor comprises one or more current mirrors; the control transistor is coupled to an input path of the one or more current mirrors; an output path of the one or more current mirrors is coupled to a current processing circuit; and the current processing circuit comprises at least one of an averaging circuit or a sampling circuit.
Regarding Claim 6, none of the prior art fairly teaches or suggests the apparatus of claim 2, wherein: the switching transistor comprises a high-side switching transistor of the power converter; and a polarity of the control transistor is opposite to a polarity of the switching transistor.
Regarding Claim 8, none of the prior art fairly teaches or suggests the apparatus of claim 1, wherein: the current sensor is to apply a gate voltage to the sense transistor which is equal to a gate voltage of the switching transistor and to apply a drain voltage to the sense transistor which is equal to a drain voltage of the switching transistor.
Regarding Claim 10, none of the prior art fairly teaches or suggests the apparatus of claim 1, wherein: the compound semiconductor die has a bandgap greater than a bandgap of the silicon die.
Regarding Claim 12, none of the prior art fairly teaches or suggests the apparatus of claim 1, wherein: the sense transistor is coupled to an inverting input of the amplifier; and the switching transistor is coupled to a non-inverting input of the amplifier.
Claim 13 depends on claim 12, therefore claim 13 also have allowable subject matter.
Claims 14-21 are allowed. Examiner’s reasons for allowance are following:
a) Applicant amended independent claim 20 by adding limitation of previously objected claim 22 and overcome rejection. Applicant’s arguments filed on 11/25/2025 have been fully considered and are persuasive. Therefore the rejection sent on Office Action mailed on 08/25/2025 is withdrawn.
b) Any reference does not disclose nor fairly suggest each and every claimed limitation of independent claims 14 and 20:
As to claims 14-19 the present invention is direct to an apparatus, comprising: Independent claim 14 identifies the uniquely distinct features of “a first amplifier and a first control transistor, wherein the silicon die has a first interface to couple a non-inverting input of the first amplifier to a first node of the power converter; a second interface to couple an inverting input of the first amplifier to the first sense transistor; a third interface to couple the first control transistor to the first sense transistor, wherein the first amplifier, to modulate a voltage of the first sense transistor, is to modulate a control gate voltage of the first control transistor based on a voltage of the first node; and a current processing circuit to process a current of the first sense transistor”.
As to claims 20-21 the present invention is direct to a sense circuit, comprising: Independent claim 20 identifies the uniquely distinct features of “wherein: the amplifier, control transistor and current processing circuit are on a silicon die and the power converter is on a die having a bandgap greater than a bandgap of the silicon die”.
The closest prior art, CORBISHLEY et al. (Pub NO. Us 2023/0369974 A1), TAKADA et al. (Pub NO. US 2017/0089957 A1), Sato et al. (Patent NO. US 9,172,237 B2), Allen et al. (Patent NO. US 6,414,404 B1) teaches Method and system for Semiconductor Device, either singularly or in combination, fail to anticipate or render the above underlined limitations obvious, in combination with all other claimed limitations of claims 14 and 20.
As to claims 15-19; and 21 the claims are allowed for depending on claim 14 and 20 respectively.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance.
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached on Monday Friday 8am-5pm est.
16. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rodak Lee can be reached on 571 -270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZANNATUL FERDOUS/
Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858