DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-11 in the “Reply To Restriction Requirement” filed on January 6, 2025 is acknowledged. Newly submitted claims 32-36 are directed to inventions that are independent or distinct from the invention originally claimed in the elected invention of Group I, claims 1-11 for at least the following reasons. For example, the invention of newly added claim 32 requires “wherein the deep well region extends within the semiconductor substrate closer to the drift region than the shallow well region” which is a materially different design, mode of operation, function, or effect than the claimed invention of Group I, claims 1-11 which does not require this effect (please see, MPEP §806.05(j) and §802.01). As another example, the inventions of newly added claims 33 and 36 both require “further comprising performing an annealing process” which is a materially different design, mode of operation, function, or effect than the claimed invention of Group I, claims 1-11 which does not require this step. As an additional example, the inventions of newly submitted claims 34 and 35 require that the “second shallow well region” does “not extend within the semiconductor substrate under the second portion of the gate electrode after forming the second shallow well region using the third dopant” which is a materially different design, mode of operation, function, or effect than the claimed invention of Group I, claims 1-11 which does not require this effect. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for at least the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
(a) the inventions have acquired a separate status in the art in view of their different classifications;
(b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries); and/or
(d) the prior art applicable to one invention would not likely be applicable to another invention.
Because Applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, newly added claims 32-36 are withdrawn from consideration as being directed to a non-elected invention. See, 37 CFR §1.142(b) and §1.145, as well as MPEP §821.03.1
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, Applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should Applicant traverse on the ground that the inventions are not patentably distinct, Applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the Examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Allowable Subject Matter and Reasons for Allowance
Claims 1, 3-11, 37, and 38 are allowed over the combination of US 2021/0367073 A1 (Snyder) in view of US 2021/0036150 A1 (He) and further in view of US 2018/0350979 A1 (Reghunathan).2 The following is an Examiner’s statement of reasons for allowance.
Regarding amended independent claim 1, Snyder discloses, A method of fabricating an integrated circuit (402; FIG. 7; [0026]), the method comprising:
forming a first oxide layer (first oxide layer (424a and 424b); first annotated FIG. 7, below; [0027]) having a first thickness (first annotated FIG. 7, below) over a semiconductor substrate (substrate (404); FIG. 7; [0027]),
forming a second oxide layer (second oxide layer (424a and 424b); first annotated FIG. 7, below; [0027]) over the semiconductor substrate (404) and touching the first oxide layer (424a and 424b; first annotated FIG. 7, below), the second oxide layer (424a and 424b) having a greater second thickness (first annotated FIG. 7, below);
forming a gate structure (gate structure (422a and 422b); FIG. 7; [0027]) that extends over the first and second oxide layers (424a and 424b; FIG. 7);
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forming a patterned photoresist layer (patterned photoresist layer (561a and 561b); FIGs. 5 and 7; [0028]) that extends over the gate structure (422a and 422b) and second oxide layer (424a and 424b), and exposes a portion of the semiconductor substrate (404) and an uncovered portion of the gate structure (422a and 422b) between the substrate portion (404) and the second oxide layer (424a and 424b) (second annotated FIG. 7, below);
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forming a shallow well region (shallow well region (712); FIG. 7; [0050]) by implanting a first dopant (first dopant (772); FIG. 7; [0050]) such that the first dopant (772) penetrates the exposed substrate portion (second annotated FIG. 7, above) and is blocked by the uncovered portion of the gate structure (422a and 422b; second annotated FIG. 7, above); and
forming a deep well region (deep well region (714); FIG. 7; [0051]) having the first conductivity type (first conductivity type (p-type); [0032]) by implanting a second dopant (second dopant (772); FIG. 7; [0051]).
But, Snyder does not appear to explicitly disclose:
a semiconductor substrate having a first conductivity type;
the second dopant penetrates through the uncovered portion of the gate structure;
wherein implanting the second dopant includes implanting the second dopant at a first energy through the uncovered portion of the gate structure thereby producing a first deep well sub-region with a first peak dopant concentration under the gate structure, and implanting the second dopant at a greater second energy through the uncovered portion of the gate structure thereby producing a second deep well sub-region with a second peak dopant concentration under the gate structure, the first peak dopant concentration being between the second peak dopant concentration and the gate structure; and
wherein the patterned photoresist layer blocks the second dopant from being implanted into the semiconductor substrate positioned under the patterned photoresist layer during the implanting of the second dopant at the first and second energies such that the first and second deep well sub-regions do not extend within the semiconductor substrate under the patterned photoresist layer.
However, in analogous art, He discloses, a lateral double-diffused metal-oxide semiconductor device (FIG. 1A; [0038]) that includes a substrate (substrate (100); FIG. 1A; [0038]) having a first conductivity type (i.e., P-type), N-drift region (N-drift region (101); FIG. 1A; [0038]) formed on the substrate (100), and a P-type well region (P-type well region (102); FIG. 1A; [0038]) formed in the N-drift region (101).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Snyder and He before him/her, that the semiconductor substrate (404) of Snyder have a first conductivity type of p-type, as taught by He, which corresponds to the first conductivity type of deep well region (714) of Snyder, because a substrate can only have a finite number of predicably charge types (i.e., either p-type or n-type) and, absent this important teaching in Snyder, a person of ordinary skill in the art would be motivated to reach out to He to determine which of these conductivity types could be utilized to fabricate the integrated circuit of Snyder with a reasonable expectation of success. See MPEP 2143(E)—“Obvious To Try”—Choosing From a Finite Number of Identified, Predictable Solutions, With a Reasonable Expectation of Success.
But, Snyder in view of He does not appear to explicitly disclose:
the second dopant penetrates through the uncovered portion of the gate structure; and
wherein implanting the second dopant includes implanting the second dopant at a first energy through the uncovered portion of the gate structure thereby producing a first deep well sub-region with a first peak dopant concentration under the gate structure, and implanting the second dopant at a greater second energy through the uncovered portion of the gate structure thereby producing a second deep well sub-region with a second peak dopant concentration under the gate structure, the first peak dopant concentration being between the second peak dopant concentration and the gate structure; and
wherein the patterned photoresist layer blocks the second dopant from being implanted into the semiconductor substrate positioned under the patterned photoresist layer during the implanting of the second dopant at the first and second energies such that the first and second deep well sub-regions do not extend within the semiconductor substrate under the patterned photoresist layer.
However, in analogous art, Reghunathan, discloses, a method of fabricating an integrated circuit (FIG. 21) that includes forming a patterned photoresist layer (patterned photoresist layer (1705); FIG. 21; [0139]) that extends over a gate structure (gate structure (1745); FIG. 21; [0139]). Reghunathan also discloses that a shape of a deep well region (deep well region (1711); FIG. 21; [0143]-[0144]) can predicably be formed by implanting dopants such that the dopant penetrates through an uncovered portion of gate structure (1745) and is blocked by photoresist layer (1705) (first annotated FIG. 21, below).
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Reghunathan additionally discloses that dopants can be predicably implanted at a first energy through uncovered portion of gate structure (1745) thereby producing a first deep well sub-region (first deep well sub-region (1711b’); FIG. 21; [0144]) with a first peak dopant concentration (1711b’) ([0144]) under gate structure (1745). Reghunathan further discloses that dopants can be predicably implanted at a greater second energy level through uncovered portion of gate structure (1745) ([0144]) thereby producing a second deep well sub-region (second deep well sub-region (1711a’); FIG. 21; [0143]-[0144]) with a second peak dopant concentration (1711a’) ([0144) under gate structure (1745). Reghunathan also further discloses that first peak dopant concentration (1711b’) is between the second peak dopant concentration (1711a’) and gate structure (1745). Reghunathan additionally further discloses that patterned photoresist layer blocks3 the second dopant from being implanted into the semiconductor substrate (annotated Fig. 21, above) under the patterned photoresist layer during implanting the second dopant at the first and second energies (annotated FIG. 21, above).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Snyder, He, and Reghunathan before him/her, that deep well region (714) shape can predicably be formed by implanting second dopant (772) such that second dopant (772) penetrates through uncovered portion of gate structure (422a and 422b) of Snyder and He, as taught by Reghunathan; and that: (i) second dopant (772) can be predicably implanted at a first energy through uncovered portion of gate structure (422a and 422b) of Snyder and He, thereby producing a first deep well sub-region with a first peak dopant concentration under gate structure (422a and 422b), as also taught by Reghunathan, (ii) second dopant (772) can also be predicably implanted at a greater second energy though uncovered portion of gate structure (422a and 422b) of Snyder and He thereby producing a second deep well sub-region with a second peak dopant concentration under gate structure (422a and 422b), as additionally taught by Reghunathan, (iii) the first peak dopant concentration is between the second peak dopant concentration and gate structure (422a and 422b) of Snyder and He, as further taught by Reghunathan, to predicably control the depth of the first deep well sub-region with the first peak dopant concentration and the depth of the deep well sub-region with the second peak dopant concentration, as still further taught by Reghunathan, and (iv) the patterned photoresist layer (561a and 561b) of Snyder and He, blocks the second dopant (772) from being implanted into the semiconductor substrate (404) positioned under the patterned photoresist layer (561a and 561b) during the implanting of the second dopant (772) at the first and second energies, as additionally still further taught by Reghunathan.
But, the combination of Snyder in view of He and further in view of Reghunathan does not appear to explicitly disclose, such that the first and second deep well subregions do not extend within the semiconductor substrate under the patterned photoresist layer.
Claims 3-11, 37, and 38 depend from independent claim 1 and thus further define and/or limit the subject matter recited therein. Therefore, claims 3-11, 37, and 38 are also allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” The Examiner respectfully submits that the absence of his response to Applicant’s comments does not mean that the Examiner agrees with or acquiesces in the reasoning of such comments. Please see 37 CFR 1.104(e) and MPEP 1302.14(V).
Claim Objections
Claim 38 is objected to because of the following informality: on line 4, “performing annealing process” should be “performing an annealing process”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over Snyder in view of He and further in view of Reghunathan.
Regarding claim 29, Snyder discloses, A method of fabricating an integrated circuit (402; FIG. 7; [0026]), the method comprising:
forming a gate electrode (gate electrode (326a and 326b) and/or (1226a and 1226b); FIGs. 3 and 12; [0024], [0042], and [0046]) over a semiconductor substrate (substrate (304); FIG. 3; [0021] and/or substate (404); FIG. 7; [0027]; [0025]);
patterning a photoresist layer (patterned photoresist layer (561a and 561b); FIGs. 5 and 7; [0028]; [0025]) over the gate electrode ((326a and 326b) and/or (1226a and 1226b)), the patterning producing a photoresist portion (photoresist portion (561a and 561b); FIGs. 5 and 7; [0028]; [0025]) that covers a first portion of the gate electrode ((326a and 326b) and/or (1226a and 1226b)) (FIG. 3 and third annotated FIG. 7, below; [0025]) and exposes a second portion of the gate electrode ((326a and 326b) and/or (1226a and 1226b)) that overlies a gate dielectric layer (gate dielectric layer (422a and 422b); FIG. 7; [0027]) (FIG. 3 and third annotated FIG. 7, below; [0025]), and exposes a portion of the semiconductor substrate (404) (third annotated FIG. 7, below);
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forming a shallow well region (shallow well region (712); FIG. 7; [0050]) by implanting a first dopant (first dopant (772); FIG. 7; [0050]) such that the first dopant (772) penetrates the exposed portion of the semiconductor substrate (404) (third annotated FIG. 7, above) and is blocked by the exposed second portion of the gate electrode ((326a and 326b) and/or (1226a and 1226b)); third annotated FIG. 7, above) and the photoresist portion (561a and 561b; third annotated FIG. 7, above);
forming a deep well region (deep well region (714); FIG. 7; [0051]) having the first conductivity type (first conductivity type (p-type); [0032]) using a second dopant (second dopant (772); FIG. 7; [0051]) such that the second dopant (772) penetrates through the exposed second portion of the gate electrode ((326a and 326b) and/or (1226a and 1226b)); third annotated FIG. 7, above); and
forming a drift region (drift region (918a and 918b); FIG. 9; [0036]) that extends within the semiconductor substrate (404) under the gate electrode ((326a and 326b) and/or (1226a and 1226b)) prior to forming the deep well region (714) ([0046]—“The particular steps, order of steps, and combination of steps are shown in FIG. 15 for illustrative and explanatory purposes only. Other embodiments can implement different particular steps, orders of steps, and combinations of steps to achieve similar functions or results. The steps of FIG. 15 are described with reference to FIGS. 4-14.”).
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But, Snyder does not appear to explicitly disclose:
a semiconductor substrate having a first conductivity type;
a photoresist portion that completely covers a local oxidation of silicon (LOCOS) layer; and
the deep well region having a first peak dopant concentration under the gate electrode at a first depth and a second peak dopant concentration at a second depth between the first depth and the gate electrode.
However, in analogous art, He discloses, a lateral double-diffused metal-oxide semiconductor device (FIG. 1A; [0038]) that includes a substrate (substrate (100); FIG. 1A; [0038]) having a first conductivity type (i.e., P-type), N-drift region (N-drift region (101); FIG. 1A; [0038]) formed on the substrate (100), and a P-type well region (P-type well region (102); FIG. 1A; [0038]) formed in the N-drift region (101).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Snyder and He before him/her, that the semiconductor substrate (404) of Snyder have a first conductivity type of p-type, as taught by He, which corresponds to the first conductivity type of deep well region (714) of Snyder, because a substrate can only have a finite number of predicably charge types (i.e., either p-type or n-type) and, absent this important teaching in Snyder, a person of ordinary skill in the art would be motivated to reach out to He to determine which of these conductivity types could be utilized to fabricate the integrated circuit of Snyder with a reasonable expectation of success. See MPEP 2143(E)—“Obvious To Try”—Choosing From a Finite Number of Identified, Predictable Solutions, With a Reasonable Expectation of Success.
But, Snyder in view of He does not appear to explicitly disclose:
a photoresist portion that completely covers a local oxidation of silicon (LOCOS) layer; and
the deep well region having a first peak dopant concentration under the gate electrode at a first depth and a second peak dopant concentration at a second depth between the first depth and the gate electrode.
However, in analogous art, Reghunathan, discloses, a method of fabricating an integrated circuit (FIG. 21) that includes patterning a photoresist layer (photoresist layer (1705); FIG. 21; [0139]) over a gate structure (gate structure (1745); FIG. 21; [0139]) where the photoresist layer (1705) includes a photoresist portion (photoresist portion (1705); second annotated FIG. 21, below; [0139]) that completely covers a local oxidation of silicon (LOCOS) layer (local oxidation of silicon (LOCOS) layer (1720); second annotated FIG. 21, below; [0139]; [0078]) that is utilized to separate a substrate into various regions that will form different components and/or devices ([0091]).
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Reghunathan also discloses that a deep well region (deep well region (1711); FIG. 21; [0143]-[0144]) can be predicably formed to have a first peak dopant concentration (first peak dopant concentration (1711); FIG. 21; [0143]—[0144]) under the gate structure (1745) at a first depth (second annotated FIG. 21, above) and a second peak dopant concentration (second peak dopant concentration (1711b’); FIG. 21; [0144]) at a second depth (second annotated FIG. 21, above) between the first depth (second annotated FIG. 21, above) and the gate structure (1745). Reghunathan additionally discloses that the first and second depths are predicably controlled by selecting dopant implant energy levels such that second peak dopant concentration (1711b’) is implanted at a lower energy than first peak dopant concentration (1711) ([0144]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Snyder, He, and Reghunathan before him/her, that photoresist layer (561a and 561b) of Snyder and He can be predicably patterned to produce a photoresist portion to completely cover a local oxidation of silicon (LOCOS) layer to separate substrate (404) of Snyder and He into various regions that will form different components and/or devices, as taught by Reghunathan; and that: (i) deep well region (714) of Snyder and He can predicably be formed to have a first peak dopant concentration under gate electrode ((326a and 326b) and/or (1226a and 1226b)) at a first depth, as also taught by Reghunathan, and (ii) deep well region (714) of Snyder and He can also be predicably formed to have a second peak dopant concentration at a second depth between the first depth and the gate electrode (326a and 326b and/or (1226a and 1226b)), as additionally taught by Reghunathan, by selecting dopant implant energy levels such that second peak dopant concentration is implanted at a lower energy than first peak dopant concentration, as further taught by Reghunathan.
Regarding claim 30, Snyder in view of He and Reghunathan discloses, The method as recited in claim 29, wherein the first dopant is boron and the second dopant is boron ([0032] of Snyder).
Regarding claim 31, Snyder in view of He and Reghunathan discloses, The method as recited in claim 29, wherein the deep well region (714 of Snyder and 1711 of Reghunathan) extends from under the shallow well region (712 of Snyder) toward the LOCOS layer (1720 of Reghunathan; third annotated FIG. 21, below), and has a first depth under the shallow well (712; third annotated FIG. 21, below) region and a lesser second depth under the gate electrode (326a and 326b; third annotated FIG. 21, below).
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Response to Amendments and Arguments
Applicant’s amendment of claims 1 and 29 and remarks with respect thereto in the Response To Final Office Action Under 37 C.F.R. § 1.114 submitted with the Request for Continued Examination (RCE) application on November 21, 2025 (hereinafter collectively referred to herein as the “Reply”) have overcome the objection to claims 1 and 29 in the Final Office Action dated July 21, 2025 (hereinafter referred to herein as the “Final Office Action”). Also, Applicant’s amendment of claims 10 and 11 and remarks with respect thereto in the Reply have overcome the rejection of claims 10 and 11 under 35 U.S.C. 112(b) in the Final Office Action. Additionally, Applicants amendment of independent claim 1 and remarks with respect thereto on pages nine (9)-eleven (11) of the Reply (which have been relied on by the Examiner) have overcome the rejection of claims 1 and 3-11 under 35 U.S.C. 103 in the Final Office Action.
Regarding amended independent claim 29, pages 11-12 of the Reply state:
However, as shown above, the cited portions of Snyder do not disclose or suggest forming a drift region that extends within a semiconductor substrate under gate polysilicon 422a/b prior to forming deep p-well 714. Instead, as shown below in FIG. 9, Snyder discloses forming drift regions918a-b in a later processing step. See Snyder, para. [0036].
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Accordingly, Snyder at least fails to disclose or suggest "forming a drift region that extends within the semiconductor substrate under the gate electrode prior to forming the deep well region," as recited by amended claim 29.
The Examiner respectfully disagrees at least because paragraph [0046] of Snyder provides that the steps of the method of fabricating an integrating circuit disclosed therein are “for illustrative and explanatory purposes only. Other embodiments can implement different particular steps, orders of steps, and combinations of steps to achieve similar functions or results.” Therefore, the Examiner respectfully submits that Snyder does disclose forming a drift region that extends within the semiconductor substrate under the gate electrode prior to forming the deep well region, as discussed above.
Notwithstanding the above, to facilitate compact prosecution of the Application, the Examiner respectfully requests that Applicant please consider a telephone interview with the Examiner to discuss proposed amendments to the claims that overcome the rejection thereof under 35 U.S.C. 103, prior to submitting a written response to this Office Action. Perhaps Applicant could please consider amending independent claim 29 to recite “first and second deep well sub-regions that do not extend within the semiconductor substrate under the patterned photoresist layer”. The Examiner would welcome such an interview and is available at the telephone number provided, below, for a discussion of such proposed claim amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/
Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 The Examiner respectfully submits that claims 37 and 38 would have also been restricted and withdrawn because the claimed invention of claim 37 requires “wherein the first deep well sub-region is spaced apart from the second deep well sub-region after implanting the second dopant at the first and second energies” and the claimed invention of claim 38 requires “performing annealing process” which are both a materially different design, mode of operation, function, or effect than the claimed invention of Group I, claims 1-11 (please see, MPEP §806.05(j) and §802.01). However, claims 37 and 38 have not been restricted and withdrawn because of their dependence on allowable independent claim 1.
2 The Examiner respectfully notes that allowance of dependent claim 38 is contingent on Applicant’s correction thereof based on the objection thereto, as discussed more fully below.
3 The Examiner respectfully notes that amended independent claim 1 does not recite that the patterned photoresist layer completely blocks the second dopant from being implanted into the substrate. Rather amended independent claim 1 only recites that the patterned photoresist layer blocks the second dopant from being implanted into the substrate. The Examiner respectfully submits that under a broadest reason interpretation of this recited language of claim 1, as required by, for example, MPEP 2111, 2141, and 2143, “blocks” includes partial blocking as disclosed by Reghunathan.