DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other reference: Frayer (US 20150364215) – Low-Test memory stack for non-volatile storage with parallel memory operations on RAID stripe (0102).
Danilov (US 11023331) – Recovery of data in storage environment
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 –3, 5, 9 – 11,13, 14 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Wai et al. (US 20220058126) in view of Schuetz. (US 20130094271) and further in view of Hung (20070115731) and Wang (US 11443014)
Regarding claim 1, Wai a computing system comprising: a processor; and a storage subsystem comprising a plurality of memory banks configured in . . . memory banks comprising a plurality of sub-banks, Wai illustrates a memory storage system in Figure 5 and a plurality of memory sub-banks in Figures 1, 2 and 3. [0006] the addressing scheme defining a plurality of memory tiles, each memory tile among the plurality of memory tiles designated as belonging to a memory bank among a plurality of memory banks and a memory sub-banks.
wherein the processor is configured to store one or more whole sub- matrices comprising a plurality of slices in the memory banks, the plurality of slices comprising a plurality of data values,
Wai teaches [Abstract] mapping matrix to the memory, [0006] memory element as a first memory element for storing a first matrix element among a plurality of matrix elements, a quantity of matrix elements in the plurality of matrix elements being equivalent to a quantity of memory elements in the plurality of memory elements each memory line and accessing the second selected memory element as a second memory element for storing a second matrix element among a second plurality of matrix elements [0067] mappings of matrix elements of various matrices. ; figure 1 [0043] matrix element defined by a row and a column … row and the column of the matrix element to a specific bank and sub-bank
and wherein the plurality of slices include one or more row slices and one or more corresponding column slices (eg., 0094 Fig. 6 - requestor 600 provides, to the arbiter 506 of the external controller 502, the sub-parameters Rows50x, Rows10x, Rows1x=2, Start50x, Line50x, Line1x, Col40x and Col1x for the read operation.)
Wai does not teach; a plurality of memory banks configured in series … and, wherein a request to retrieve particular slices from one more particular sub- matrices sequentially moves between the plurality of memory banks to retrieve a predetermined amount of data.
However, Schuetz teaches; plurality of memory banks configured in series, Figures 1C and 3 and described in [0015-0017] plurality of memory devices is also interconnected in series by a serial chip enable link from a single enable output of the controller and each memory device may comprise a serial enable input and a serial enable output, and the serial enable link may connect each of the plurality of memory devices in series and [0023-0024]. Schuetz also teaches [0007] a serial arrangement can provide for higher data throughput and enable higher speed operation . . . and
Schuetz further teaches wherein a request to retrieve particular slices from one more particular sub- matrices sequentially moves between the plurality of memory banks to retrieve a predetermined amount of data. Figures 10 and 11 show memory devices accessed in sequence and [0089] devices . . . on the channel are sequentially accessed and [0092] flash devices … is individually accessed in sequence.
Wai and Schuetz are analogous art because they are from the same field of endeavor of memory access control and are disclosed before the effective filing date of the claimed inventions.
It would have been obvious to a person of ordinary skill in the art at the time of Applicant’s filing to incorporate the serially connected memory banks and subsequently accessing the memory banks sequentially as disclosed in Schuetz into Wai’s disclosure to provide the improved performance and reduced pin count of connecting memory in series (Schuetz [0037] single serial enable signal . . . significantly reducing the per channel pin count, along with enabling a higher data throughput and higher speed operation (Schuetz [0007]).
Wai in view of Schuetz does not disclose, but Hung discloses
memory tiles comprising a plurality of slices, the slices comprising a plurality of data values, wherein particular slices of the tile memory tiles are stored in corresponding sub-banks, such that different slices corresponding to a same memory tile are stored in different sub-banks (eg., 0035 Fig. 5 - logical address block indicated in the data read request is corresponding to the user data block UD.sub.12 drawn with oblique lines, and other data blocks located on the same stripe are drawn with dots. In step S32, stripe 1 is determined to be the target stripe according to the logical address block of the data read request. Thus, the user data block UD.sub.11 is decided to be accessed from plural data blocks of the storage device D1; the user data block UD.sub.12 is decided to be accessed from plural data blocks of the storage device D2; the user data block UD.sub.13 is decided to be accessed from plural data blocks of the storage device D3; the parity data block PD.sub.14 is decided to be accessed from plural data blocks of the storage device D4)
wherein the request retrieves two or more slices corresponding to different memory tiles from a same sub-bank in a single cycle (eg., 0039 - read request indicates the controller 121 to read data in the user data blocks UD.sub.12 and UD.sub.22 of the storage device D2,… the target data is distributed on two target stripes, so step S33 (equivalent to the flowchart of FIG. 4A, or in another embodiment, equivalent to the flowchart of FIG. 4B) needs to proceed for the two target stripes respectively and simultaneously… the controller 121 will simultaneously issue the first I/O requests and the second I/O requests to all storage devices D1, D2, D3 and D4)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory storage system having banks and sub-banks of Wai in view of Schuetz, with Hung, providing the benefit of data access methods and storage subsystems without waiting a read timeout (see Hung, 0007).
Wai in view of Schuetz, Hung does not disclose, but Wang discloses
and wherein the particular slices are selectively retrieved based on a multiplication result between numerical values of the one or more row slices and numerical values of the one or more corresponding column slices by determining, for a row slice, whether the multiplication result is a zero value or a non-zero value when multiplied with the one or more corresponding column slices, and refraining from retrieving the row slice upon determining that the multiplication result is the zero value. (eg., col 9:9-16 - pseudocode 290 runs on successive non-zero rows of the Sparse multiplier matrix in the loop starting at line 293. Within each row, the loop of lines line 294-298 is run once for each non-zero value in the row and products of the values vector elements and elements of each column of the corresponding row of the Dense multiplicand matrix are generated and accumulated to create a column in the Product matrix in lines 295-296; col 12:50-60 - pseudocode 290 runs on successive non-zero rows of the Sparse multiplier matrix in the loop starting at line 293. Within each row, the loop of lines line 294-298 is run once for each non-zero value in the row and products of the values vector elements and elements of each column of the corresponding row of the Dense multiplicand matrix are generated and accumulated to create a column in the Product matrix in lines 295-296)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory storage system having banks and sub-banks of Wai in view of Schuetz, with Hung, with Wang, providing the benefit of solving the problem in the art of Storing a matrix that is mostly zeros and then performing multiplication on vectors that are all zero is very inefficient (see Wang, col 2:3-4).
Regarding claim 2, Wai in view of Schuetz discloses the computing system of claim 1. Wai teaches wherein the predetermined amount of data comprises an amount of data stored in one whole tile, Wai teaches Figure 1 a diagram of memory segments including banks and sub-banks. [0005] Indeed, matrix elements in a data matrix may be mapped to the memory elements within the given memory segment in accordance with the addressing scheme, and [0006] first selected memory element as a first memory element for storing a first matrix element among a plurality of matrix elements. Where a collection of one or more matrix elements is analogous to a tile.
Regarding claim 3, Wai in view of Schuetz discloses the computing system of claim 1. Wai teaches wherein the request retrieves a plurality of different slices from a plurality of different tile stored in a plurality of different memory banks. Wai teaches retrieval of a plurality of different slices from a plurality of different tile stored in a plurality of different memory banks, where [0004] - [0006] A memory tile, in a local memory, may be considered to be a unit of memory that carries multiple memory elements, wherein each memory element is a one-dimensional memory structure . . . matrix elements in a data matrix may be mapped to the memory elements within the given memory segment. A memory tile and slice are synonymous.
Regarding claim 5, Wai in view of Schuetz discloses the computing system of claim 1. Wai further teaches wherein the request retrieves a plurality of same slices from a plurality of different tile stored in a same memory bank in a plurality of cycles. [0055] eight memory lines (up to 32E per memory line) to be accessed in a single clock cycle and [0061]- [0063] access to a maximum of 50 memory lines in a single clock cycle ... access 32 memory elements in a single clock cycle.
Regarding claim 9, Wai teaches A method of storing and retrieving data comprising: [0006] method . . . including, . . . accessing . . . for storing matrix element among a plurality of matrix elements, . . . matrix elements in the plurality of matrix elements being equivalent to a quantity of memory elements in the plurality of memory elements each memory line and accessing the second selected memory element as a second memory . . . storing a plurality of whole tile in memory banks of a memory computing system Figures 2 and 3 and [0067] mappings of matrix elements of various matrices to memory locations, as identified by memory entry and by bank . . . comprising a plurality of said memory banks configured . . ., the memory banks comprising a plurality of sub-banks, Figures 13 & 14 and [0035] A memory segment arranged … a two-dimensional memory array of B×SB memory tiles, where “B” is the number of rows of memory tiles, with each row referred to as a “bank,” and where “SB” is the number of columns of memory tiles, with each column referred to as a “sub-bank” and [0050] bank 0 and sub-bank 0 … bank 0, the memory tile 102-0/1 in the next sub-bank
and the tile comprising a plurality of slices, as previously identified, the term “slices” in synonymous with “elements or matrix elements” in [0006] in a single clock cycle, accessing the first selected memory element as a first memory element for storing a first matrix element among a plurality of matrix elements, a quantity of matrix elements in the plurality of matrix elements being equivalent to a quantity of memory elements in the plurality of memory elements each memory line and accessing the second selected memory element as a second memory element for storing a second matrix element among a second plurality of matrix elements.
the slices comprising a plurality of data values, Figures 1 and 2 show memory banks, sub-banks and tiles. Tile or groups of matrix elements can be stored sub-banks. [0062] eight 16-bit matrix elements are stored in the eight 16-bit memory elements in the memory line with index 0 in the memory tile 102-0/0 of memory entry 0, the matrix elements may be indexed as CO-7. The subsequent eight 16-bit matrix elements may be stored in eight 16-bit memory elements in a memory in a memory tile 102 in a bank different from bank 0 and may be indexed as C8-15. Similarly, each subsequent set of eight memory elements may be stored in a memory tile 102 in a bank distinct from the other banks.
receiving a request to retrieve particular slices from two or more particular tiles; [0002] memory tiles in a given memory segment, it may be shown that non-blocking, concurrent write and read accesses to the memory elements and [0096] read operation, the memory segment 100 provides requested matrix elements to a funnel module 608 via a data bus. The funnel module 608 provides the matrix elements, that have been read from the memory segment . . .
wherein the plurality of slices include one or more row slices and one or more corresponding column slices (eg., 0094 Fig. 6 - requestor 600 provides, to the arbiter 506 of the external controller 502, the sub-parameters Rows50x, Rows10x, Rows1x=2, Start50x, Line50x, Line1x, Col40x and Col1x for the read operation.)
Wai does not teach, … comprising a plurality of said memory banks configured in series, . . . and, . . .retrieving the particular slices for one or more particular tile sequentially from one or more of the plurality of memory banks to retrieve a predetermined amount of data.
However, Schuetz teaches . . . memory banks configured in series [0015] – [0017] plurality of memory devices is also interconnected in series … first and second memory devices may comprise a serial enable input and a serial enable output, the enable input of the first memory device being coupled to the enable output of the controller, and the enable output of the first memory device being coupled to a enable input of the second memory device in the series, for providing a single enable signal from the controller for enabling or disabling each of the plurality of memory devices … may connect each of the plurality of memory devices in series
Schuetz further teaches retrieving the particular slices for one or more particular tile sequentially from one or more of the plurality of memory banks to retrieve a predetermined amount of data [0089] devices 302-0 to 302-n on the channel are sequentially accessed
It would have been obvious to combine Schuetz with Wai for the same reasons as set forth in claim 1, above.
Wai in view of Schuetz does not disclose, but Hung discloses
memory tiles comprising a plurality of slices, the slices comprising a plurality of data values, wherein particular slices of the tile memory tiles are stored in corresponding sub-banks, such that different slices corresponding to a same memory tile are stored in different sub-banks (eg., 0035 Fig. 5 - logical address block indicated in the data read request is corresponding to the user data block UD.sub.12 drawn with oblique lines, and other data blocks located on the same stripe are drawn with dots. In step S32, stripe 1 is determined to be the target stripe according to the logical address block of the data read request. Thus, the user data block UD.sub.11 is decided to be accessed from plural data blocks of the storage device D1; the user data block UD.sub.12 is decided to be accessed from plural data blocks of the storage device D2; the user data block UD.sub.13 is decided to be accessed from plural data blocks of the storage device D3; the parity data block PD.sub.14 is decided to be accessed from plural data blocks of the storage device D4).
wherein the request retrieves two or more slices corresponding to different memory tiles from a same sub-bank in a single cycle (eg., 0039 - read request indicates the controller 121 to read data in the user data blocks UD.sub.12 and UD.sub.22 of the storage device D2,… the target data is distributed on two target stripes, so step S33 (equivalent to the flowchart of FIG. 4A, or in another embodiment, equivalent to the flowchart of FIG. 4B) needs to proceed for the two target stripes respectively and simultaneously… the controller 121 will simultaneously issue the first I/O requests and the second I/O requests to all storage devices D1, D2, D3 and D4).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory storage system having banks and sub-banks of Wai in view of Schuetz, with Hung, providing the benefit of data access methods and storage subsystems without waiting a read timeout (see Hung, 0007).
Wai in view of Schuetz, Hung does not disclose, but Wang discloses
and wherein the particular slices are selectively retrieved based on a multiplication result between numerical values of the one or more row slices and numerical values of the one or more corresponding column slices by determining, for a row slice, whether the multiplication result is a zero value or a non-zero value when multiplied with the one or more corresponding column slices, and refraining from retrieving the row slice upon determining that the multiplication result is the zero value. (eg., col 9:9-16 - pseudocode 290 runs on successive non-zero rows of the Sparse multiplier matrix in the loop starting at line 293. Within each row, the loop of lines line 294-298 is run once for each non-zero value in the row and products of the values vector elements and elements of each column of the corresponding row of the Dense multiplicand matrix are generated and accumulated to create a column in the Product matrix in lines 295-296; col 12:50-60 - pseudocode 290 runs on successive non-zero rows of the Sparse multiplier matrix in the loop starting at line 293. Within each row, the loop of lines line 294-298 is run once for each non-zero value in the row and products of the values vector elements and elements of each column of the corresponding row of the Dense multiplicand matrix are generated and accumulated to create a column in the Product matrix in lines 295-296)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory storage system having banks and sub-banks of Wai in view of Schuetz, with Hung, with Wang, providing the benefit of solving the problem in the art of Storing a matrix that is mostly zeros and then performing multiplication on vectors that are all zero is very inefficient (see Wang, col 2:3-4).
Regarding claim 10, it has substantially similar limitations as stated in claims 2; therefore, it is rejected under the same subject matter.
Regarding claim 11, it has substantially similar limitations as stated in claims 4; therefore, it is rejected under the same subject matter.
Regarding claim 13, Wai in view of Schuetz teaches the method of claim 9. Wai further teaches wherein the request retrieves a plurality of same slices from a plurality of different tile stored in a same memory bank in a plurality of cycles. Wai teaches [0055] eight memory lines (up to 32E per memory line) to be accessed in a single clock cycle and [0061]- [0063] access to a maximum of 50 memory lines in a single clock cycle ... access 32 memory elements in a single clock cycle.
Regarding claim 14. Wai in view of Schuetz teaches the method of claim 9. Wai further teaches wherein the request comprises a plurality of addresses for a corresponding plurality of tile and, for each tile, a corresponding slice mask specifying slices of each tile to be retrieved. Wai teaches an address translation computing system in Figures 5,6, 10,11 12 and 14 which are capable of address the memory banks, sub banks and tiles described. These memories can be used to access matrices and matrix elements [0005] – [0006] memory elements carried by the memory tiles in a given memory segment, it may be shown that non-blocking, concurrent write and read accesses to the memory elements may be achieved, for multiple requestors, with relatively high throughput. Indeed, matrix elements in a data matrix may be mapped to the memory elements within the given memory segment in accordance with the addressing scheme. The accesses may be either row-major or column-major when the data matrix is two-dimensional and a first memory element for storing a first matrix element among a plurality of matrix elements, a quantity of matrix elements in the plurality of matrix elements.
Regarding claim 16, Wai teaches computer storage subsystem storing a program executable by a computer for storing and retrieving data, the program comprising sets of instructions for: [0034] non-transitory computer/processor readable storage medium or media for storage of information, such as computer/processor readable instructions . . .
storing a plurality whole tile in memory banks of a memory computing system Figures 2 and 3 and [0067] mappings of matrix elements of various matrices to memory locations, as identified by memory entry and by bank . . . comprising a plurality of said memory banks configured . . ., the memory banks comprising a plurality of sub-banks, Figures 13 & 14 and [0035] A memory segment arranged … a two-dimensional memory array of B×SB memory tiles, where “B” is the number of rows of memory tiles, with each row referred to as a “bank,” and where “SB” is the number of columns of memory tiles, with each column referred to as a “sub-bank” and [0050] bank 0 and sub-bank 0 … bank 0, the memory tile 102-0/1 in the next sub-bank
and the tile comprising a plurality of slices, as previously identified, the term “slices” in synonymous with “elements or matrix elements” in [0006] in a single clock cycle, accessing the first selected memory element as a first memory element for storing a first matrix element among a plurality of matrix elements, a quantity of matrix elements in the plurality of matrix elements being equivalent to a quantity of memory elements in the plurality of memory elements each memory line and accessing the second selected memory element as a second memory element for storing a second matrix element among a second plurality of matrix elements.
the slices comprising a plurality of data values; Figures 1 and 2 show memory banks, sub-banks and tiles. Tile or groups of matrix elements can be stored sub-banks. [0062] eight 16-bit matrix elements are stored in the eight 16-bit memory elements in the memory line with index 0 in the memory tile 102-0/0 of memory entry 0, the matrix elements may be indexed as CO-7. The subsequent eight 16-bit matrix elements may be stored in eight 16-bit memory elements in a memory in a memory tile 102 in a bank different from bank 0 and may be indexed as C8-15. Similarly, each subsequent set of eight memory elements may be stored in a memory tile 102 in a bank distinct from the other banks.
receiving a request to retrieve particular slices from one or more particular sub- matrices; [0002] memory tiles in a given memory segment, it may be shown that non-blocking, concurrent write and read accesses to the memory elements and [0096] read operation, the memory segment 100 provides requested matrix elements to a funnel module 608 via a data bus. The funnel module 608 provides the matrix elements, that have been read from the memory segment . . .
wherein the plurality of slices include one or more row slices and one or more corresponding column slices (eg., 0094 Fig. 6 - requestor 600 provides, to the arbiter 506 of the external controller 502, the sub-parameters Rows50x, Rows10x, Rows1x=2, Start50x, Line50x, Line1x, Col40x and Col1x for the read operation.)
Wai does not teach, … comprising a plurality of said memory banks configured in series, . . . and, . . .retrieving the particular slices for one or more particular tile sequentially from one or more of the plurality of memory banks to retrieve a predetermined amount of data.
However, Schuetz teaches . . . memory banks configured in series [0015] – [0017] plurality of memory devices is also interconnected in series … first and second memory devices may comprise a serial enable input and a serial enable output, the enable input of the first memory device being coupled to the enable output of the controller, and the enable output of the first memory device being coupled to a enable input of the second memory device in the series, for providing a single enable signal from the controller for enabling or disabling each of the plurality of memory devices … may connect each of the plurality of memory devices in series
Schuetz further teaches retrieving the particular slices for one or more particular tile sequentially from one or more of the plurality of memory banks to retrieve a predetermined amount of data [0089] devices 302-0 to 302-n on the channel are sequentially accessed
It would have been obvious to combine Schuetz with Wai for the same reasons as set forth in claim 1, above.
Wai in view of Schuetz does not disclose, but Hung discloses
memory tiles comprising a plurality of slices, the slices comprising a plurality of data values, wherein particular slices of the tile memory tiles are stored in corresponding sub-banks (eg., 0035 Fig. 5 - logical address block indicated in the data read request is corresponding to the user data block UD.sub.12 drawn with oblique lines, and other data blocks located on the same stripe are drawn with dots. In step S32, stripe 1 is determined to be the target stripe according to the logical address block of the data read request. Thus, the user data block UD.sub.11 is decided to be accessed from plural data blocks of the storage device D1; the user data block UD.sub.12 is decided to be accessed from plural data blocks of the storage device D2; the user data block UD.sub.13 is decided to be accessed from plural data blocks of the storage device D3; the parity data block PD.sub.14 is decided to be accessed from plural data blocks of the storage device D4) (eg., 0039 - read request indicates the controller 121 to read data in the user data blocks UD.sub.12 and UD.sub.22 of the storage device D2,… the target data is distributed on two target stripes, so step S33 (equivalent to the flowchart of FIG. 4A, or in another embodiment, equivalent to the flowchart of FIG. 4B) needs to proceed for the two target stripes respectively and simultaneously… the controller 121 will simultaneously issue the first I/O requests and the second I/O requests to all storage devices D1, D2, D3 and D4)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory storage system having banks and sub-banks of Wai in view of Schuetz, with Hung, providing the benefit of data access methods and storage subsystems without waiting a read timeout (see Hung, 0007).
Wai in view of Schuetz, Hung does not disclose, but Wang discloses
and wherein the particular slices are selectively retrieved based on a multiplication result between numerical values of the one or more row slices and numerical values of the one or more corresponding column slices by determining, for a row slice, whether the multiplication result is a zero value or a non-zero value when multiplied with the one or more corresponding column slices, and refraining from retrieving the row slice upon determining that the multiplication result is the zero value. (eg., col 9:9-16 - pseudocode 290 runs on successive non-zero rows of the Sparse multiplier matrix in the loop starting at line 293. Within each row, the loop of lines line 294-298 is run once for each non-zero value in the row and products of the values vector elements and elements of each column of the corresponding row of the Dense multiplicand matrix are generated and accumulated to create a column in the Product matrix in lines 295-296; col 12:50-60 - pseudocode 290 runs on successive non-zero rows of the Sparse multiplier matrix in the loop starting at line 293. Within each row, the loop of lines line 294-298 is run once for each non-zero value in the row and products of the values vector elements and elements of each column of the corresponding row of the Dense multiplicand matrix are generated and accumulated to create a column in the Product matrix in lines 295-296)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory storage system having banks and sub-banks of Wai in view of Schuetz, with Hung, with Wang, providing the benefit of solving the problem in the art of Storing a matrix that is mostly zeros and then performing multiplication on vectors that are all zero is very inefficient (see Wang, col 2:3-4).
Claims 17-18, have substantially similar limitations as stated in claims 2-3, respectively; therefore, they are rejected under the same subject matter.
Claims 6, 7, 8, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wai et al. (US 20220058126) and Hung (cited above) and Wang (cited above) in view of Sade (US 20190102196).
Regarding claim 6, Wai in view of Schuetz and Hung and Wang discloses the computing system of claim 1. However, neither Wai nor Schuetz and Hung teaches wherein the request comprises a plurality of addresses for a corresponding plurality of tile and, for each tile, a corresponding slice mask specifying slices of each tile to be retrieved.
On the other hand, Sade discloses wherein the request comprises a plurality of addresses for a corresponding plurality of tile and, for each tile, a corresponding slice mask specifying slices of each tile to be retrieved. [0165] each J-element sub-column of the specified source matrix in row-major order into a K-wide submatrix of the specified destination matrix, the K-wide submatrix having K columns and enough rows to hold the J elements and ability to mask [0218] zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. and [0227] with the elements that are actually transferred is dictated by the contents of the vector mask that is selected as the write mask.
Sade describes matrices and tile, and masks (writemask) which is analogous to “slice mask”. It would have been obvious to combine Wai with Schuetz for reasons set forth in claim 1. In addition, Sade, Schuetz and Wai are considered to analogous arts, because they all relate to matrix manipulations in memories, therefore, it would have been obvious to combine Sade with the Wai-Schuetz combination for the benefit of using various masking techniques to isolate matrix elements, either row and/or line or non-zero matrix elements. Sade’s use of writemask advantageously select if a storage in memory occurs, which achieve performance gains for not storing when matrix elements are not needed. Sade also teaches operations that will zero desired rows and columns using vector masks.
Regarding claim 7, Wai in view of Schuetz and Hung and Wang in further view of Sade teach the computing system of claim 6. Sade further teaches wherein the slice mask comprises a plurality of bits corresponding to the plurality of slices of each tile. Sade teaches tile and sub-columns (slices) [0165] each J-element sub-column of the specified source matrix in row-major order into a K-wide submatrix of the specified destination matrix, the K-wide submatrix having K columns and enough rows to hold the J elements and ability to mask [0218] zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. and [0227] with the elements that are actually transferred is dictated by the contents of the vector mask that is selected as the write mask. Sade’s “J-element sub-column” is analogous to a slice in a tile, and Sade’s use of write mask in combination with sub-column yields the same capability as selecting a slice in a tile.
Regarding claim 8, Wai in view of Schuetz discloses the computing system of claim 1. Neither Wai nor Schuetz and Hung appear to specifically teach wherein the memory banks are configured to store one or more whole tile using low address interleaving. On the other hand, Sade teaches wherein the memory banks are configured to store one or more whole tile using low address interleaving. [0163] row-interleaved (RowInt) formatted matrix . . . In particular, a RowInt-formatted matrix can be used when performing fused multiply-add (FMA) operations (or other arithmetic) to perform the FMA and then combine (add together) the results of adjacent operations and [0165] processor is to transform the specified source matrix into the specified destination matrix having a row-interleaved . . . format. In particular, in response to the opcode, the processor is to interleave elements of . . . sub-column of the specified source matrix . . . into a . . . submatrix of the specified destination matrix. It would have been obvious to combine Wai with Schuetz and Hung and Wang for the reasons set forth in claim 1 above. However, Sade, which also relates to the same field of endeavor, does disclose systems and methods for manipulating matrices with interleaved format, and the feature is desirable for fused multiply -add (FMA) operations or other arithmetic operations. There for it would be obvious by a person of ordinary skill in the art to combine Sade’s feature with Wai-Schuetz to the benefit of interleaving matrices and associated operations.
Claim 15, has substantially similar limitations as stated in claims 6 and 7, it is rejected under that same subject matter.
Claim 20 has substantially similar limitations as stated in claims 6, it is rejected under the same subject matter.
Response to Arguments
Applicant's arguments filed 11/18/2025 have been fully considered but they are not persuasive.
For Claims 1, 8, 16, the present OA rejects these amended limitations that Applicant argues.
Specifically, Wai in view of Schuetz, Hung does not disclose, but Wang discloses
and wherein the particular slices are selectively retrieved based on a multiplication result between numerical values of the one or more row slices and numerical values of the one or more corresponding column slices by determining, for a row slice, whether the multiplication result is a zero value or a non-zero value when multiplied with the one or more corresponding column slices, and refraining from retrieving the row slice upon determining that the multiplication result is the zero value. (eg., col 9:9-16 - pseudocode 290 runs on successive non-zero rows of the Sparse multiplier matrix in the loop starting at line 293. Within each row, the loop of lines line 294-298 is run once for each non-zero value in the row (as indicated by the row's entry in nnzs_per_row) and products of the values vector elements and elements of each column of the corresponding row of the Dense multiplicand matrix are generated and accumulated to create a column in the Product matrix in lines 295-296; col 12:50-60 - pseudocode 290 runs on successive non-zero rows of the Sparse multiplier matrix in the loop starting at line 293. Within each row, the loop of lines line 294-298 is run once for each non-zero value in the row and products of the values vector elements and elements of each column of the corresponding row of the Dense multiplicand matrix are generated and accumulated to create a column in the Product matrix in lines 295-296)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory storage system having banks and sub-banks of Wai in view of Schuetz, with Hung, with Wang, providing the benefit of solving the problem in the art of Storing a matrix that is mostly zeros and then performing multiplication on vectors that are all zero is very inefficient (see Wang, col 2:3-4).
Applicant’s arguments for dependent claims are based on dependency from base claims, addressed above.
Conclusion
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135