DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed December 22nd, 2025. Claims 1-9, 11-19, and 21-23 are pending, of which claims 1, 5-9, 11, 15, and 21 are currently rejected. Claims 10 and 20 have been cancelled by Applicant. Claims 2-4, 12-19, and 22-23 are objected to.
Response to Arguments
The amendment filed December 22nd, 2025 has been entered. Claims 1-9, 11-19, and 21-23 remain pending in the application. Applicant’s amendments to the Claims have overcome every 112(b) rejection previously set forth in the Non-Final Office Action mailed September 25th, 2025.
Claim Rejections – 35 USC § 112
Applicant has amended claims and resolved the antecedent basis issues. Therefore, the previous rejections under 35 U.S.C. 112(b) as set forth in the Office Action mailed September 25th, have been withdrawn. However, new 112(b) rejections have been made as necessitated by the amendments.
See Claim Rejections – 35 USC § 112.
Claim Objections
Some new claim objections have been made as necessitated by amendments.
See Claim Objections.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are persuasive. New grounds of rejection have been made by Examiner that are necessitated by the amendments. See Claim Rejections - 35 USC § 103 and Claim Rejections - 35 USC § 102.
Claim Objections
Claim 1-9, 11-19 and 21-23 are objected to:
Claim 1 lines 14 “the analog-to-digital converter to receive” should be “the analog-to-digital converter configured to receive”.
Claims 2-9, 11 and 22-23 are objected to based on their dependence upon claim 1.
Claim 12 line 9 “coupled with to a respective capacitor” should be “coupled to a respective capacitor”.
Claims 13-19 and 21 are objected to based on their dependence upon claim 12.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5, 15, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “the first or second logical operand” on line 1. There is lack of antecedent basis for this limitation in the claim. For examination purposes, “the first or second logical operand” of claim 5 line 2 is construed to be “the first or second operand” as recited in claim 1 lines 9-10. Appropriate correction is required.
Claim 15 recites the limitation “the first or second logical operand” on line 1. There is lack of antecedent basis for this limitation in the claim. For examination purposes, “the first or second logical operand” of claim 5 line 2 is construed to be “the first operand” of claim 12 line 10-11 and “the second operand” of claim 12 line 18. Appropriate correction is required.
Claim 21 recites the limitation “the voltage level” on line 2. There is lack of antecedent basis for this limitation in the claim. For examination purposes, “the voltage level” of claim 21 line 2 is construed to be “the voltage” of claim 12 line 3. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-9, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Atallah et al. (12554976) (hereinafter “Atallah”).
Regarding claim 1, Atallah teaches:
A circuit for multiply-and-accumulate operations, comprising:
a plurality of analog multiplication circuits to generate a voltage representing a sum of activation-weight products of a neural network operation (Fig. 7 shows a plurality of compute lines in usage, each of the compute lines i.e., analog multiplication circuits having a plurality of capacitors and first and second switches; also discussed in Col. 1 Lines 55-66 discuss the usage of first and second compute lines i.e., plurality of analog multiplication circuits), an analog multiplication circuit comprising:
a plurality of capacitors (Fig. 1 capacitor C of each channel 105-110), each capacitor having a capacitance corresponding to a bit value of a logical bit in a plurality of logical bits (Col. 4 Lines 1-5 capacitor stores multiplication of activation and weight bits; Col. 5 Lines 35-56 describes charging of capacitors based on logical bits i.e., activation and weight bits),
a plurality of first switches, each first switch coupled to a corresponding capacitor and configured to connect the corresponding capacitor to a common interconnect or to a ground voltage (Fig 1 S3 of each of the channels) based at least in part on a first operand or a second operand (Col. 4 Lines 56-60 first and second switches (s2 and s3 switches as depicted in Fig. 1) that are responsive to an activation bit and weight bit i.e., operands) and
a second switch configured to selectively connect the common interconnect to a voltage source (Fig. 1 S2 of each of the channels connecting to VDD); and
an analog-to-digital converter coupled with the plurality of analog multiplication circuits (Fig. 1 115 shows output connected to ADC; Fig. 6 shows plurality of bit cells forming compute lines i.e., analog multiplication circuits being connected to ADC),
the analog-to-digital converter to receive the voltage from the plurality of analog multiplication circuits and generate a digital output from the voltage (Fig. 7 Step 705 and step 715 digitizing output upon receiving voltage from compute line; Col. 10 Lines 27-43 digitizing voltage received from analog multiplication circuits through ADC to provide digital output of multiply-accumulate result; Col. 4 Lines 1-17 ADC receives analog accumulation from capacitors and switches and digitizes to provide digital output).
Regarding claim 5, Atallah teaches:
The circuit of claim 1, wherein the first or second logical operand comprise binary logical bits (Col. 1 Lines 55-67 first and second operand are between activation bits and weight bits).
Regarding claim 6, Atallah teaches:
The circuit of claim 1, wherein the circuit is in a memory array (Fig 1 is each of the A cells of the memory array as depicted in Fig. 6).
Regarding claim 7, Atallah teaches:
The circuit of claim 6, wherein the digital output is stored to a location in the memory array (Col. 3 Lines 26-33 filter weight outputs of one layer are sent to next layer as operands, and operands are stored in the bit cell array as described in Col. 12 Lines 14-15 and Col. 3 39-48).
Regarding claim 8, Atallah teaches:
The circuit of claim 6, wherein the first operand or the second operand is stored in the memory array (Col. 12 Lines 14-15 filter weights stored in bit-cell array i.e. memory cell, depicted in Fig. 4, bit-cells are where the multiply-accumulate computation also takes place, as discussed in Col. 3 39-48).
Regarding claim 9, Atallah teaches:
The circuit of claim 1, wherein the first operand or the second operand is a weight or an activation value for a convolutional layer (Col. 2 Lines 66-67 and Col. 3 Line 1 circuit is in hybrid CIM array for a convolutional neural network, having layers as discussed in Col. 3 Lines 9-17; Col. 3 Lines 40-55 discusses the convolutional layers with operands of filter weight bits and activation bits).
Regarding claim 11, Atallah teaches:
The circuit of claim 1, wherein the common interconnect is further connected to a second plurality of capacitors, and the voltage is an accumulation of at least a first multiplication represented by a first charge of the plurality of capacitors and a second multiplication represented by a second charge of the second plurality of capacitors (Fig. 6 plurality of bit cells such as the configuration of Fig. 1 coupled together i.e., their common interconnects coupled, each bit cell having a corresponding product and being accumulated in a final digital sum as explained in Col 14 Lines 2-5).
Allowable Subject Matter
Claims 2-4 and 22-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Applicant claims a circuit for multiply-accumulate operations, comprising:
a plurality of analog multiplication circuits to generate a voltage representing a sum of activation-weight products of a neural network operation, an analog multiplication circuit comprising:
a plurality of capacitors, each capacitor having a capacitance corresponding to a bit value of a logical bit in a plurality of logical bits,
a plurality of first switches, each first switch coupled to a corresponding capacitor and configured to connect the corresponding capacitor to a common interconnect or to a ground voltage based at least in part on a first operand or a second operand, and
a second switch configured to selectively connect the common interconnect to a voltage source; and
an analog-to-digital converter coupled with the plurality of analog multiplication circuits, the analog-to-digital converter to receive the voltage from the plurality of analog multiplication circuits and to generate a digital output from the voltage.
Wherein claim 2 is dependent on claim 1 further comprising:
A control circuit configured to:
selectively charge the plurality of capacitors by switching the plurality of first switches to the common interconnect according to the first operand and switching the second switch to the voltage source;
after charging the plurality of capacitors, switching the second switch away from the voltage source and connecting the plurality of first switches to the common interconnect;
selectively reducing the charge of the plurality of capacitors by switching the plurality of first switches to the common interconnect or the ground voltage according to the second operand; and
after selectively reducing the charge, switching the plurality of first switches to the common interconnect.
The specific reason for indication of allowable subject matter is the switching of the first switches to the common interconnect according to the first operand as well as switching the plurality of first switches to the common interconnect to or the ground voltage according to the second operand. Atallah discloses the claimed invention according to the claim mappings above. Atallah does not explicitly disclose the switching of the first switches to the common interconnect according to the first operand as well as switching the plurality of first switches to the common interconnect to or the ground voltage according to the second operand as claimed.
Claim 3 dependent on claim 2 is therefore also allowable.
Wherein claim 4 is dependent on claim 1 further comprising:
wherein the second switch is further configured to selectively connect the common interconnect to the ground voltage.
The specific reason for indication of allowable subject matter is the switching of the second switch to selectively connect the common interconnect to the ground voltage. Atallah discloses the claimed invention according to the claim mappings above. Atallah does not explicitly disclose the switching of the second switch to selectively connect the common interconnect to the ground voltage as claimed.
Wherein claim 22 is dependent on claim 1 further comprising:
wherein the second switch is to be disconnected from an output of the analog multiplication circuit to the analog-to-digital converter for the analog multiplication circuit to determine a local voltage, wherein the voltage is generated based on the local voltage.
The specific reason for indication of allowable subject matter is switching the second switch to the analog-to-digital converter for the analog multiplication circuit to determine a local voltage. Atallah discloses the claimed invention according to the claim mappings above. Atallah does not explicitly disclose switching the second switch to the analog-to-digital converter for the analog multiplication circuit to determine a local voltage as claimed.
Wherein claim 22 is dependent on claim 1 further comprising:
wherein the second switch is to be connected to an output of the analog multiplication circuit of the analog-to-digital converter for charge sharing across at least some of the plurality of analog multiplication circuits.
The specific reason for indication of allowable subject matter is the connecting of the second switch to an output of the analog multiplication circuit and the analog-to-digital converter for charge sharing. Atallah discloses charge sharing across capacitors (Atallah: Col. 6 Lines 40-45) and the claimed invention according to the claim mappings above. Atallah does not explicitly disclose is the connecting of the second switch to an output of the analog multiplication circuit and the analog-to-digital converter for charge sharing as claimed.
Claims 12-14 and 17-19 are allowed.
Applicant claims a method for executing a multiply-and-accumulate operation, the method comprising:
A method for executing a multiply-and-accumulate operation, the method comprising:
generating, by a plurality of analog multiplication circuits, a voltage representing a sum of activation-weight products of a neural network operation, wherein generating the voltage comprises:
selectively charging a plurality of capacitors in an analog multiplication circuit, each capacitor having a capacitance corresponding to a bit value of a logical bit in a plurality of logical bits, by switching a plurality of first switches in the analog multiplication circuit, each first switch coupled with to a respective capacitor of the plurality of capacitors, to a common interconnect or a ground voltage according to a first operand and switching a second switch in the analog multiplication circuit, the second switch coupled to the common interconnect to a voltage source
after charging the plurality of capacitors, switching the second switch away from the voltage source and connecting the plurality of first switches to the common interconnect to average the charge across the plurality of capacitors,
selectively reducing the charge of the plurality of capacitors by switching the plurality of first switches to the common interconnect or the ground voltage according to a second operand and
after selectively reducing the charge, switching the plurality of first switches to the common interconnect;
receiving, by an analog-to-digital converter coupled with the plurality of analog multiplication circuits, the voltage from the plurality of analog multiplication circuits; and
generating, by the analog-to-digital converter a digital output from the voltage.
The specific reason for indication of allowable subject matter is for the highlighted limitations as indicated above. Atallah discloses a plurality of analog multiplication circuits, activation-weight products, a plurality of capacitors, a plurality of first switches and a second switch, a common interconnect, and a analog-to-digital converter as discussed with respect to claim 1 above. Atallah does not explicitly disclose is the above highlighted limitations as claimed.
Claims 13-14 and 17-19 are allowable dependent on claim 12 are therefore also allowable.
Claims 15 and 21 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and rewritten in independent form to include all of the limitations of the base claim and any intervening claims.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang (12487795) teaches in-memory computing using a plurality of cells comprising transistors for 1-bit multiplication utilized for MAC operations in a time-multiplexed manner.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151