Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specifically, the newly identified prior art of Nagrath (US 20170111158 A1) addresses the amendment language in light of the existing prior art.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
2. Claim 21 is rejected under 35 U.S.C. 112(a)as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Claim 21 refers to the generation of a first and a second logical switch processor object. However, Examiner review of the disclosure only reflects the creation of a single logical switch processor object within the disclosure. Specifically, [0026] discloses “it may generate a logical switch object 402” and further “When a second redundant switch processor is detected by hardware controller agent 401, the existing logical switch processor object 402 may be updated.” While [0026] suggest the existence of a plurality of logical switch processor objects, the disclosure only covers the generation or creation of a singular object.
As such, while the disclosure would support the presence of multiple objects, it does not provide support for a method including the generation of multiple logical processor objects.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-5, 9, 11-15, and 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable Guim Bernat et al. (US 20230205718 A1) in view of Nagrath (US 20170111158 A1) and in further view of Biggin et al. (20210304541 A1).
Claim 1 Guim Bernat teaches a method for managing switches comprising:
executing, by a processor of a computer system, (FIG. 2, System) one or more feature agents (FIG. 2, ¶0016, Orchestrator 200 comprising a feature agent; Examiner notes that as Orchestrator 200 comprises an agent as it does not depend upon user initiation) configured to perform a plurality of configuration operations on a plurality of switch processors residing in one or more network switches, (¶0016, wherein Orchestrator 200 performs configuration operations on switch processors, Processing Sockets 204) the plurality of configuration operations being defined in a plurality of configuration data in a first format that is maintained by the one or more feature agents; (¶0016, wherein the configuration operations are defined by topology information, Examiner notes that data inherently would be in at least one format)
executing, by the processor, a switch processor programming agent, (FIG. 2, ¶0017, Topology-based Scheduler 202 comprising a switch processor programming agent, as Topology-based Scheduler 202 configure switch processors) wherein the switch processor programming agent provides a logical interface for programming a particular subset of switch processors in the plurality of switch processors, (¶0017, wherein Scheduler 202 provides a logical interface, i.e. forming connections, for programming switch processors) and wherein a first subset of switch processors are of a different model or type than a second subset of switch processors; (Examiner interprets “model or type,” particularly the term type as indicating any distinction between one switch processor and another; ¶0016, wherein processor sockets are differentiated between one another for configuration) and
communicating, by the processor, the plurality of configuration data in the first format from the one or more feature agents to the respective switch processor programming agents. (FIG. 2, ¶0016, communicatively receiving topology information, i.e. a plurality of configuration data, from Orchestrator 200, i.e. one or more feature agents, to the Topology-based Scheduler 202, i.e. one or more respective switch programming agents)
However, Guim Bernat does not explicitly teach a first and second switch processor programming agent;
translating, by the processor via the switch processor programming agent, the plurality of configuration data from the first format into a second format understood by the subset of switch processors; and
automatically programming, by the processor via first switch processor programming agent, each switch processor in the first subset of switch processors with the configuration data in the second format.
But it would be an obvious iterations of the teachings of Guim Bernat to execute a first and second processor programming agents. While the first and second switch processor programming agents are associated with different subsets of switch processors, the first and second switch processors have no recited distinctions between each other and their processes are separate and unrelated (i.e. they separately translate configuration data for their respective subset of switch processors). Examiner also notes that the subset of switch processors themselves is outside of the scope of the method claims and further such a difference in model or type would not require any difference in switch processor programming agents.
However, Guim Bernat does not explicitly or by obvious combination teach translating, by the processor via the first switch processor programming agent, the plurality of configuration data from the first format into a second format understood by the subset of switch processors;
automatically programming, by the processor via first switch processor programming agent, each switch processor in the first subset of switch processors with the configuration data in the second format;
translating, by the processor via the second switch processor programming agent, the plurality of configuration data from the first format into a third format understood by the second subset of switch processors, the third format being different from the second format; and
automatically programming, by the processor via the second switch processor programming agent, each switch processor in the second subset of switch processors with the configuration data in the third format.
From a related technology, Nagrath teaches translating, by the processor via the first switch processor programming module, the data from the first format; (¶0011, wherein the translation module is able to translate data from one format to a second format) and
translating, by the processor via the second switch processor programming module, the data from the first format into a third format, the third format being different from the second format. (¶0011, wherein the translation module is able to translate data from one format to a third format)
It would be obvious to one of ordinary skilling the art to modify the teachings of Guim Bernat to incorporate multiple modules to perform translations in order to more effective utilize network resources by specializing tasks so they can be optimized individually.
However, Guim Bernat in view of Nagrath does not explicitly teach automatically programming, by the processor via the second switch processor programming module, each switch processor in the second subset of switch processors with the configuration data in the third format.
From a related technology, Biggin teaches translating, by the processor via the switch processor programming agent, the plurality of configuration data from the first format into a second format understood by the subset of switch processors; (FIG. 3, step S212, ¶0075, converting the configuration data into a second format for use in programming the network switch) and
automatically programming, by the processor via first switch processor programming agent, each switch processor in the first subset of switch processors with the configuration data in the second format. (FIG. 3, S214, ¶0076, automatically programming by a network switch management system with the configuration data in the second format)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Guim Bernat in view of Nagrath to incorporate the configuration translation techniques utilized in Biggin in order to more effectively utilize network resources.
Claim 2 Guim Bernat to in view of Nagrath and Biggin teaches Claim 1, and further teaches wherein the first switch processor programming agent maintains the first subset of switch processors in a same state, and wherein a second switch processor programming agent maintains the second subset of switch processors in a same state. (Guim Bernat, FIG. 2, Processor Sockets and 204 204-1; FIG. 2, ¶0015, wherein the processor sockets are maintained in a state of availability)
Claim 3 Guim Bernat to in view of Nagrath and Biggin teaches Claim 1, and further teaches wherein the first and second subsets of switch processors comprise a first switch processor configured to route network traffic (Guim Bernat, FIG. 2, Processor Socket 204-1) and a second switch processor (Guim Bernat, FIG. 2, Processor Socket 204-1) wherein the second switch processor maintains a same state as the first switch processor, (FIG. 2, ¶0015, wherein the processor sockets are maintained in a state of availability)
and wherein the second switch processor is configured to route network traffic when the first switch processor becomes inoperable. (Examiner notes that this is a contingent limitation, i.e. the second redundant switch processor is only configured to route network traffic when the first switch processor becomes inoperable, however, this contingency is not explicitly recited and therefore the claim does not have patentable weight)
Claim 4 Guim Bernat to in view of Nagrath and Biggin teaches Claim 1, and further teaches in response to a change in the configuration data in the first format, (Biggin, ¶0075, wherein the exporting of configuration data comprises a change in configuration data) the switch processor programming agent automatically translates the change in the configuration data from the first format to the second format and automatically programs the plurality of switch processors with the change in the configuration data in the second format. (Biggin, FIG. 3, S212, ¶0075, translating the configuration document into a second format)
Claim 5 Guim Bernat to in view of Nagrath and Biggin teaches Claim 1, wherein the switch processors are switch application specific integrated circuits (ASIC). (Biggin, ¶0104, wherein the switches comprise circuits which are application specific)
Claim 9 Guim Bernat to in view of Nagrath and Biggin teaches Claim 1, and further teaches wherein a plurality of feature agents send configuration data in the first format to a single switch processor programming agent. (Biggin, FIG. 3, S210, ¶0074, receiving a configuration document in a default format from the feature agents)
Claims 11-13 are taught by Guim Bernat in view of Nagrath and Biggin as described for Claims 1-3.
Claim 14 Guim Bernat in view of Nagrath and Biggin teaches Claim 11, and further teaches wherein the one or more switch processor programming agents receive a plurality of configuration data in a first format from a corresponding one or more feature agents (Biggins, FIG. 3, ¶0075, receiving configuration data into a first format for use in programming the network switch) and translate the plurality of configuration data into a second format, and wherein the one or more switch processor programming agents automatically program the first and second switch processors with the configuration data in the second format. translating the plurality of configuration data into a second format; (Biggins, FIG. 3, step S212, ¶0075, converting the configuration data into a second format for use in programming the network switch)
Claims 15 and 18 are taught by Guim Bernat in view of Nagrath and Biggin as described for Claims 4 and 9.
Claim 20 is taught by Guim Bernat in view of Nagrath and Biggin as described for Claim 1.
3. Claims 7-8 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Guim Bernat et al. (US 20230205718 A1) view of Nagrath (US 20170111158 A1) and Biggin et al. (US 20210304541 A1) and in further view of Ng et al. (US 20220283946 A1).
Claim 7 Guim Bernat in view of Nagrath and Biggins teaches Claim 1, but does not explicitly teach wherein the second format is a direct memory access (DMA) format and the one or more switch processor programming agents automatically program the plurality of switch processors using direct memory access (DMA) transactions over a bus coupled between the processor and the plurality of switch processors.
From a related technology, Ng teaches a direct memory access (DMA) format; (¶0007, direct memory access, DMA, format)
using direct memory access (DMA) transactions over a bus. (¶0028, using DMA transaction over a bus)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Guim Bernat in view of Nagrath and Biggins to incorporate well-known DMA techniques in order to more effectively utilize network resources.
Claim 8 Guim Bernat in view of Nagrath and Biggins teaches Claim 1, but does not explicitly teach wherein a first switch processor programming agent accesses a first table of data for a first feature agent, translates the first table of data into a second table of data in a direct memory access (DMA) format, and performs a first direct memory access (DMA) write between the processor and a first switch processor and performs a second direct memory access (DMA) write between the processor and a second switch processor.
From a related technology, Ng teaches translates the first table of data into a second table of data in a direct memory access (DMA) format; (¶0031, translating table data in a direct memory access, DMA, format) and
performing a direct memory access (DMA) write. (¶0031, performing DMA writes)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Guim Bernat in view of Nagrath and Biggins and Lee to incorporate well-known DMA techniques in order to more effectively utilize network resources.
Claims 16-17 are taught by Guim Bernat in view of Nagrath, Biggins, and Ng as described for Claims 7-8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER PALACA CADORNA whose telephone number is (571)270-0584. The examiner can normally be reached M-F 10:00-7:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Follansbee can be reached at (571) 272-3964. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER P CADORNA/Examiner, Art Unit 2444
/JOHN A FOLLANSBEE/Supervisory Patent Examiner, Art Unit 2444