DETAILED ACTION
AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-6, 8, 9, 11-14 and 16-20 are amended.
Claims 1-20 are pending.
Claims 1-20 are rejected (Final Rejection).
Response to Amendments
Applicant’s amendments to claims 4, 12, 17 and 19 (dated 03/19/2026) obviate the respective claim objections.
Applicant’s amendments to claim 1 (dated 03/19/2026) obviate the previous 35 U.S.C. § 112(b) rejections.
Applicant’s amendments to claims 8, 13 and 14 (dated 03/19/2026) obviate the previous 35 U.S.C. § 112(a) rejections.
Applicant’s amendment to claim 11 (dated 03/19/2026) obviates the previous 35 U.S.C. § 101 “software per se” rejection(s).
For these reasons, the previous claim objections, and previous 35 U.S.C. §§ 112(a) and (b) rejections have been withdrawn.
However, Applicant’s amendments to claims 11 and 16 include “new matter” (and corresponding 35 U.S.C. § 112(a) rejections are introduced) as discussed below.
Response to Arguments
Applicant’s arguments, at Pages 9 and 10, filed 03/19/2026, with respect to the rejections under 35 U.S.C. § 101 have been fully considered and are persuasive. Specifically, Applicant’s argument regarding the practical application of fabrication of a transistor structure. Applicant’s § 101 arguments, in conjunction with the relevant claim amendments, obviate the previous § 101 “abstract idea” rejections of all pending claims.
Regarding 35 U.S.C. § 103, Applicant’s arguments with respect to the rejections under 35 U.S.C. § 103 have been fully considered and are persuasive in part. Therefore, the previous prior art (§ 103) rejections have been withdrawn. However, upon further consideration, new ground(s) of rejection under § 103 are made.
In addition, Applicant’s argument, at Page 12, that “Lei’s prediction is for interpolation/extrapolation, not for missing test data” is unpersuasive because Claim 1 does not recite “missing test data”. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “missing test data”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claim Rejections - 35 U.S.C. § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 11-20 are rejected under 35 U.S.C. § 112(a), as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 11 has been amended to recite “[a] transistor modeling apparatus comprising: … a computing device configured to: … fabricate a transistor structure …”.
Applicant indicates that support for all claim amendments are provided in Paras. [0018], [0024], [0025], [0030] and [0054] of the published version (US 2023/0105438) of the original specification. However, none of the Applicant-supplied paragraphs states that the modeling apparatus is configured to perform both the modeling and the fabrication. Rather, the specification appears to indicate, e.g., at Para. [0054] of the as-filed specification, “modeling may be applied to processing and fabrication”.
Accordingly, Applicant has not particularly pointed out where each of the newly added claim limitations originate from in the original specification. There is no explanation in the original specification for the subject matter pertaining to: “[a] transistor modeling apparatus comprising: … a computing device configured to: … fabricate a transistor structure …”.
Accordingly, claim 11 is rejected for failing to comply with the written description requirement. Claim 16 has substantially similar limitations as recited in claim 11; therefore, it is rejected under 35 U.S.C. 112(a) for the same reasons. Claims 12-15 and 17-20 depend respectively from one or more of rejected claims 11 and 16. Therefore, claims 12-15 and 17-20 are also rejected under the same rationale since these claims inherit the respective deficiencies of claims 11 and 16, while failing to cure the respective deficiencies of claims 11 and 16.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 are rejected under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 1 recites both “third ET data measured from the test device” and “unmeasured data from the third ET data”, which is unclear and inconsistent. Particularly, it is not clear how third ET data can simultaneously be both measured and unmeasured data.
Accordingly, claim 1 is rejected for being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. Claims 2-10 depend from rejected claim 1. Therefore, claims 2-10 are also rejected under the same rationale since these claims inherit the deficiencies of claim 1, while failing to cure the deficiencies of claim 1.
For compact prosecution, Examiner has made an interpretation (as best understood), which is represented within the mapping of the claims under the 35 U.S.C. § 103 rejection (below). Specifically, Examiner has interpreted claim 1 similarly as the other independent claims 11 and 16 to avoid the inconsistency.
Examiner’s Note: Regarding the first, second and third ET data, the specification, as best understood, appears to indicate that: training a machine learning algorithm using previously stored mass electrical test (ET) data generated during a performance of electrical testing on a test element group (TEG), the TEG is fabricated by a fabrication process under the same conditions, environment, and apparatus as the semiconductor chip formed on the semiconductor substrate; acquiring actually measured electrical test data from a test device comprising a probe card, the sample of measured electrical test data originating from electrical tests performed on different sizes of a specific transistor (e.g., NMOS transistor of Para. [0035]); identifying one or more sizes of the transistor missing actually measured values (from the ET tests); predicting one or more representative electrical test value(s) for the missing values using the trained machine learning algorithm and the actually measured electrical test data. Examiner recommends considering this understanding when considering any claim amendments, and whether the representative value is necessary and/or part of the above.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 and 14 are rejected under 35 U.S.C. § 103 as being unpatentable over LEI et al. (U.S. Patent Application Publication No. 2019/0385047 A1) in view of GOLDBERGER (U.S. Patent Application Publication No. 2007/0111340 A1).
Regarding claim 1, LEI discloses a method of operating a transistor modeling apparatus (net list can then be simulated using a circuit simulator that uses a device model to simulate the operation of each of the transistors, Para. [0002] of LEI), the method comprising: acquiring sample data from a test device (measurements may be taken from test devices on a test chip manufactured with a new process, and these measurements used as training data 34 (Vgs, Vds, . . . ) and target data 38 (Ids), Para. [0057] of LEI; [Examiner’s Note: “sampled” data appears to include/correspond to measured test data that is a “target” based on Applicant’s as-filed specification at Para. [0030]; thus, the measured data from test devices used as target data in LEI is interpreted as corresponding to sample data from a test device]); performing machine learning on the sample data, which is third ET data measured from the test device, and first electrical test (ET) data obtained from a transistor mass production stage (training data 214 and test data 212 are measured data points, but training data 214 is input to the neural network to generate weights while test data 212 is used to test the accuracy of the neural network weights, Para. [0014] of LEI; [the measured/tested training data is interpreted as corresponding to the third ET data]; See also neural networks are an example of machine learning, since the neural network learns how to generate the expected outputs for the training data, Para. [0008] of LEI; See also simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; [the design stage is interpreted as a stage of transistor mass production]); generating second ET data, which is unmeasured data from the third ET data obtained through the electrical tests performed by the test device, using a result of performing the machine learning (training data 214 and test data 212 are measured data points, but training data 214 is input to the neural network to generate weights while test data 212 is used to test the accuracy of the neural network weights, Para. [0014] of LEI; [because the neural network [which performs machine learning] generates weights in LEI, the generated weights of LEI are interpreted to correspond to generated second ET data as a result of performing the machine learning]); setting a representative value for a transistor model among the second ET data (device model uses various parameters to predict the drain current Id that is produced as a function of Vg, Vd, Vb, Vs, Para. [0012] of LEI; [Examiner’s Note: Para. [0025] of Applicant’s as-filed specification appears to indicate that a predicted ET value is a representative value]); constructing the transistor model using the second ET data and the third ET data, in response to setting the representative value, the transistor model defining electrical characteristics and fabrication parameters of a transistor (goal of training is to find the values of the weights which can make the network output (predicted value) be the same as or closed to a fitting target (data), Para. [0037] of LEI), wherein each of the first ET data, the second ET data, and third ET data includes at least one electrical parameter associated with transistor operation (simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; [input data is interpreted as corresponding to the first ET data]; See also deep neural network 50 generates a transformed drain current X_Ids in response to the pre-processed inputs and the final weights, Para. [0054] of LEI; [the second ET data is interpreted as corresponding to the model/neural network output/generated data, i.e., not measured]).
LEI does not appear to explicitly disclose a test device comprising a probe card configured to perform electrical tests on a plurality of chips formed on a wafer; and fabricating a transistor structure on a semiconductor substrate based on the transistor model.
GOLDBERGER, however, is in the field of testing fabricated wafers (Abstract of GOLDBERFER) and teaches a test device comprising a probe card configured to perform electrical tests on a plurality of chips formed on a wafer (testing of the wafer, … this enables the application of various test signals at various levels and to various parts of the test circuit or the devices of the chip itself … more specifically, as shown in FIG. 4A, the metal layer Mx is patterned, so that different contact lines 430 are electrically coupled to different sections of the metal layer, e.g., Mx, Mx', Mx'' etc. … the testing is accomplished by the probe 440 contacting different locations, i.e., Mx, Mx', Mx'', or by using multiple probes on a probe card, Para. [0036] of GOLDBERGER); and fabricating a transistor structure on a semiconductor substrate based on the transistor model (reason layer M2 is important is that once fabrication of M2 is completed, every transistor on the substrate is connected to a metal line … design and process steps that are extensive, Para. [0011] of GOLDBERGER).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify the electrical parameter modeling based on transistor size of LEI with the probe card based design of GOLDBERGER for the purpose of enabling the application of various test signals at various levels and to various parts of the test circuit or the devices of the chip itself (Para. [0036] of GOLDBERGER).
Regarding claim 2, LEI as modified by GOLDBERGER teaches the method of claim 1, wherein the sample data includes various categories of ET data based on a size of the transistor (simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; See also measurements may be taken from test devices on a test chip manufactured with a new process, and these measurements used as training data 34 (Vgs, Vds, . . . ) and target data 38 (Ids), Para. [0057] of LEI; [Examiner’s Note: “sampled” data appears to include measured test data based on Applicant’s as-filed specification at Para. [0029]; In addition, voltage and temperature are interpreted as categories of ET data and “transistor width and length” are interpreted as transistor size]).
Regarding claim 3, LEI as modified by GOLDBERGER teaches the method of claim 1, wherein the second ET data includes ET data, which is not measured by the test device, based on a size of the transistor (deep neural network 50 generates a transformed drain current X_Ids in response to the pre-processed inputs and the final weights, Para. [0054] of LEI; [the second ET data is interpreted as corresponding to the model/neural network output/generated data, i.e., not measured]; As discussed above with reference to Para. [0053] of LEI, one of the data inputs is transistor width and length (i.e., transistor size values)]).
Regarding claim 4, LEI as modified by GOLDBERGER teaches the method of claim 1, wherein each of the first ET data and the second ET data includes a value of at least one of a threshold voltage, a saturation current, a linear region current, or ([Examiner notes: “or” is disjunctive and creates a choice between options) an off-leakage current (simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; [input data is interpreted as corresponding to the first ET data]; See also deep neural network 50 generates a transformed drain current X_Ids in response to the pre-processed inputs and the final weights, Para. [0054] of LEI; [the second ET data is interpreted as corresponding to the model/neural network output/generated data, i.e., not measured]; See also model 218 fails for sub-threshold voltages and currents, Para. [0014] of LEI; See also substrate leakage current could be modeled, Para. [0066] of LEI).
Regarding claim 5, LEI as modified by GOLDBERGER teaches the method of claim 1, further comprising: determining whether the transistor model should be changed; and changing the transistor model in response to determining that the transistor model should be changed (FIG. 10 shows a transistor simulator based on the models and parameters obtained by the deep neural network operating on pre-processed inputs and targeting transformed drain current … after deep neural network 50 has been used to obtain a set of weights that best models the transformed drain current, these final weights can be applied to deep neural network 50, Para. [0053] of LEI; See also goal of training is to find the values of the weights which can make the network output (predicted value) be the same as or closed to a fitting target (data) … optimization algorithm repeats this two phase cycle, forward calculation (propagation) and weights update, Para. [0037] of LEI; See also updated weights are applied to deep neural network and training data, Para. [0039] of LEI).
Regarding claim 6, LEI as modified by GOLDBERGER teaches the method of claim 5, wherein the acquiring the sample data comprises: sampling a target quantity in response to determining that the transistor model should be changed (as device sizes shrunk, the basic first-order device models failed to accurately estimate currents for the smaller devices … second-order effects caused by short channel lengths, buried layers, and sub-micron geometries required new parameters and more complex device modeling equations … more test devices having varying sizes and shapes were added and tested to obtain values for these additional parameters … automated measurement equipment allowed device model parameters to be extracted more quickly, Para. [0006] of LEI); and measuring the third ET data from the target quantity that was sampled (more test devices having varying sizes and shapes were added and tested to obtain values for these additional parameters … automated measurement equipment allowed device model parameters to be extracted more quickly, Para. [0006] of LEI; See also after discussion of problems with two-dimensional modeling for nanometer devices in Para. [0007] of LEI, LEI teaches Artificial Neural Networks (ANN) are being used to generate device models and to select parameters … Artificial Neural Networks are especially useful for processing large amounts of data in complex ways that are hard to define using traditional computer programs … instead of being programmed with instructions, training data is input to a neural network and compared to the expected output, then adjustments are made within the neural network and the training data is again processed and outputs compared to generate further adjustments to the neural network, Para. [0008] of LEI).
Regarding claim 7, LEI as modified by GOLDBERGER teaches the method of claim 6, wherein the performing the machine learning comprises performing the machine learning on the third ET data, and wherein the generating the second ET data is based on the performing the machine learning on the first ET data and the third ET data (after discussion of problems with two-dimensional modeling for nanometer devices in Para. [0007] of LEI, LEI teaches Artificial Neural Networks (ANN) are being used to generate device models and to select parameters … Artificial Neural Networks are especially useful for processing large amounts of data in complex ways that are hard to define using traditional computer programs … instead of being programmed with instructions, training data is input to a neural network and compared to the expected output, then adjustments are made within the neural network and the training data is again processed and outputs compared to generate further adjustments to the neural network, Para. [0008] of LEI).
Regarding claim 8, LEI as modified by GOLDBERGER teaches the method of claim 1, wherein the setting the representative value comprises: selecting, from among the second ET data, the representative value having a process variation in transistor mass production smaller than a process variation of other ET data in the second ET data (target transformer 44 may transform drain current by generating a derivative of the drain current … the derivative may be with respect to the gate, drain, or bulk input voltages, transistor size, temperature, etc., Para. [0031] of LEI; [bulk is interpreted as corresponding to mass production]; [Examiner’s Note: Based on Applicant’s FIGS. 3 & 4 and the corresponding description in the specification, “mass production” is interpreted as various transistors of varying sizes]; See also simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; See also measurements may be taken from test devices on a test chip manufactured with a new process, and these measurements used as training data 34 (Vgs, Vds, . . . ) and target data 38 (Ids), Para. [0057] of LEI; [Examiner’s Note: “sampled” data appears to include measured test data based on Applicant’s as-filed specification at Para. [0029]; In addition, voltage and temperature are interpreted as categories of ET data and “transistor width and length” are interpreted as transistor size]; See also “large amounts of data” discussed in the mapping of claim 7 with reference to Paras. [0007] & [0008] of LEI).
Regarding claim 9, LEI as modified by GOLDBERGER teaches the method of claim 1, further comprising: changing the transistor model using the representative value (after discussion of problems with two-dimensional modeling for nanometer devices in Para. [0007] of LEI, LEI teaches Artificial Neural Networks (ANN) are being used to generate device models and to select parameters … Artificial Neural Networks are especially useful for processing large amounts of data in complex ways that are hard to define using traditional computer programs … instead of being programmed with instructions, training data is input to a neural network and compared to the expected output, then adjustments are made within the neural network and the training data is again processed and outputs compared to generate further adjustments to the neural network, Para. [0008] of LEI; See also FIG. 10 shows a transistor simulator based on the models and parameters obtained by the deep neural network operating on pre-processed inputs and targeting transformed drain current … after deep neural network 50 has been used to obtain a set of weights that best models the transformed drain current, these final weights can be applied to deep neural network 50, Para. [0053] of LEI; See also goal of training is to find the values of the weights which can make the network output (predicted value) be the same as or closed to a fitting target (data) … optimization algorithm repeats this two phase cycle, forward calculation (propagation) and weights update, Para. [0037] of LEI; See also updated weights are applied to deep neural network and training data, Para. [0039] of LEI).
Regarding claim 10, LEI as modified by GOLDBERGER teaches the method of claim 1, wherein the first ET data includes measured ET data from the test device and predicted ET data from a machine learning technique (measurements may be taken from test devices on a test chip manufactured with a new process, and these measurements used as training data 34 (Vgs, Vds, . . . ) and target data 38 (Ids), Para. [0057] of LEI; See also goal of training is to find the values of the weights which can make the network output (predicted value) be the same as or closed to a fitting target (data) … optimization algorithm repeats this two phase cycle, forward calculation (propagation) and weights update, Para. [0037] of LEI; See also updated weights are applied to deep neural network and training data, Para. [0039] of LEI).
Regarding claim 11, LEI discloses a transistor modeling apparatus (net list can then be simulated using a circuit simulator that uses a device model to simulate the operation of each of the transistors, Para. [0002] of LEI) comprising: a test device configured to perform electrical tests on a plurality of chips formed on a wafer (measurements may be taken from test devices on a test chip manufactured with a new process, and these measurements used as training data 34 (Vgs, Vds, . . . ) and target data 38 (Ids), Para. [0057] of LEI); and a computing device configured to perform machine learning on first electrical test (ET) data of a transistor mass production stage and third ET data measured from the test device based on a size of a transistor (training data 214 and test data 212 are measured data points, but training data 214 is input to the neural network to generate weights while test data 212 is used to test the accuracy of the neural network weights, Para. [0014] of LEI; See also neural networks are an example of machine learning, since the neural network learns how to generate the expected outputs for the training data, Para. [0008] of LEI; See also simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; [transistor width & length are interpreted as transistor size(s)]), predict second ET data, which comprises unmeasured ET data by the test device during wafer-level testing, using a result of performing the machine learning (device model uses various parameters to predict the drain current Id that is produced as a function of Vg, Vd, Vb, Vs, Para. [0012] of LEI), construct a transistor model using the second ET data and the third ET data (goal of training is to find the values of the weights which can make the network output (predicted value) be the same as or closed to a fitting target (data), Para. [0037] of LEI), the transistor model defining electrical characteristics and fabrication parameters of the transistor (device model uses various parameters to predict the drain current Id that is produced as a function of Vg, Vd, Vb, Vs, Para. [0012] of LEI; See also the final weights applied to deep neural network 50 can be used to construct the final device model, Para. [0039] of LEI; See also goal of training is to find the values of the weights which can make the network output (predicted value) be the same as or closed to a fitting target (data), Para. [0037] of LEI), wherein each of the first ET data, the second ET data, and the third ET data includes at least one electrical parameter associated with transistor operation (simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; [input data is interpreted as corresponding to the first ET data]; See also deep neural network 50 generates a transformed drain current X_Ids in response to the pre-processed inputs and the final weights, Para. [0054] of LEI; [the second ET data is interpreted as corresponding to the model/neural network output/generated data, i.e., not measured]).
LEI does not appear to explicitly disclose a test device comprising a probe card configured to perform electrical tests on a plurality of chips formed on a wafer; and fabricate a transistor structure on a semiconductor substrate based on the transistor model.
GOLDBERGER, however, is in the field of testing fabricated wafers (Abstract of GOLDBERFER) and teaches a test device comprising a probe card configured to perform electrical tests on a plurality of chips formed on a wafer (testing of the wafer, … this enables the application of various test signals at various levels and to various parts of the test circuit or the devices of the chip itself … more specifically, as shown in FIG. 4A, the metal layer Mx is patterned, so that different contact lines 430 are electrically coupled to different sections of the metal layer, e.g., Mx, Mx', Mx'' etc. … the testing is accomplished by the probe 440 contacting different locations, i.e., Mx, Mx', Mx'', or by using multiple probes on a probe card, Para. [0036] of GOLDBERGER); and fabricate a transistor structure on a semiconductor substrate based on the transistor model (reason layer M2 is important is that once fabrication of M2 is completed, every transistor on the substrate is connected to a metal line … design and process steps that are extensive, Para. [0011] of GOLDBERGER).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify the electrical parameter modeling based on transistor size of LEI with the probe card based design of GOLDBERGER for the purpose of enabling the application of various test signals at various levels and to various parts of the test circuit or the devices of the chip itself (Para. [0036] of GOLDBERGER).
Claim 14 has substantially similar limitations as recited in claim 9; therefore, it is rejected under 35 U.S.C. § 103 for the same reasons.
Claims 12, 16, 17, 19 and 20 are rejected under 35 U.S.C. § 103 as being unpatentable over LEI et al. (U.S. Patent Application Publication No. 2019/0385047) in view of GOLDBERGER (U.S. Patent Application Publication No. 2007/0111340 A1) and PENG et al. (U.S. Patent No. 6,028,994).
Regarding claim 12, LEI as modified by GOLDBERG teaches the transistor modeling apparatus of claim 11, wherein (substrate leakage currents, Para. [0066] of LEI; See also simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; See also measurements may be taken from test devices on a test chip manufactured with a new process, and these measurements used as training data 34 (Vgs, Vds, . . . ) and target data 38 (Ids), Para. [0057] of LEI; [Examiner’s Note: “sampled” data appears to include measured test data based on Applicant’s as-filed specification at Para. [0029]; In addition, “transistor width and length” are interpreted as transistor size]).
LEI as modified by GOLDBERG does not appear to explicitly disclose all of each of the first ET data and the second ET data includes values corresponding to a threshold voltage and saturation current, respectively.
PENG, however, is in the field of predicting performance of ICs based on electrical parameter test data using a computer model (Col. 1, Lines 9-23) and teaches each of the first ET data and the second ET data includes values corresponding to a threshold voltage and saturation current, respectively (a large number of tests are typically performed to obtain parameters … these values include, for example, V.sub.TN (threshold voltage of NMOS field effect transistors), I.sub.DN (source/drain current of NMOS transistors in the linear and saturation regions), V.sub.TP (threshold voltage of PMOS transistors), Col. 1, Lines 32-41, of PENG).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify the electrical parameter modeling based on transistor size of LEI with the electrical transistor parameters of PENG for the purpose of detecting any defects as early as possible so that time will not be wasted performing additional fabrication steps on defective circuits (Col. 1, Lines 15-24, of PENG).
Regarding claim 16, LEI teaches a computing device (simulator 60, Para. [0056] of LEI) comprising: a processor configured to operate a transistor modeling tool (net list can then be simulated using a circuit simulator that uses a device model to simulate the operation of each of the transistors, Para. [0002] of LEI; See also simulator 60 can be constructed from input pre-processor 40, Para. [0056] of LEI); and a non-transitory memory configured to store computer program code of the transistor modeling tool (weights can be stored in weights memory 100. Since neural networks often have many nodes, there may be many weights to store in weights memory 100, Para. [0011] of LEI; See also Artificial Neural Networks are especially useful for processing large amounts of data in complex ways that are hard to define using traditional computer programs. Instead of being programmed with instructions, training data is input to a neural network and compared to the expected output, then adjustments are made within the neural network and the training data is again processed and outputs compared to generate further adjustments to the neural network, Para. [0008] of LEI) and first electrical test (ET) data obtained from a transistor mass production stage, wherein execution of the computer program code of the transistor modeling tool causes the processor to: acquire third ET data measured from a chip(measurements may be taken from test devices on a test chip manufactured with a new process, and these measurements used as training data 34 (Vgs, Vds, . . . ) and target data 38 (Ids), Para. [0057] of LEI; [Examiner’s Note: “sampled” data appears to include/correspond to measured test that is a “target” based on Applicant’s as-filed specification at Para. [0030]; thus, the measured data from test devices used as target data in LEI is interpreted as corresponding to sample data from a test device]), perform machine learning on the first ET data and the third ET data (training data 214 and test data 212 are measured data points, but training data 214 is input to the neural network to generate weights while test data 212 is used to test the accuracy of the neural network weights, Para. [0014] of LEI; See also neural networks are an example of machine learning, since the neural network learns how to generate the expected outputs for the training data, Para. [0008] of LEI; See also simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI), generate second ET data, which comprises unmeasured ET data by the test device during wafer-level testing, based on a result of performing the machine learning (training data 214 and test data 212 are measured data points, but training data 214 is input to the neural network to generate weights while test data 212 is used to test the accuracy of the neural network weights, Para. [0014] of LEI; [because “second ET data” is undefined and the neural network [which performs machine learning] generates weights in LEI, the generated weights of LEI are interpreted to correspond to generated second ET data as a result of performing the machine learning]), select a representative value for the transistor model among the second ET data (device model uses various parameters to predict the drain current Id that is produced as a function of Vg, Vd, Vb, Vs, Para. [0012] of LEI; [Examiner’s Note: Para. [0025] of Applicant’s as-filed specification appears to indicate that a predicted ET value is a representative value]; See also goal of training is to find the values of the weights which can make the network output (predicted value) be the same as or closed to a fitting target (data), Para. [0037] of LEI), change the transistor model using the second ET data and the third ET data, the transistor model defining electrical characteristics and fabrication parameters of a transistor (after discussion of problems with two-dimensional modeling for nanometer devices in Para. [0007] of LEI, LEI teaches Artificial Neural Networks (ANN) are being used to generate device models and to select parameters … Artificial Neural Networks are especially useful for processing large amounts of data in complex ways that are hard to define using traditional computer programs … instead of being programmed with instructions, training data is input to a neural network and compared to the expected output, then adjustments are made within the neural network and the training data is again processed and outputs compared to generate further adjustments to the neural network, Para. [0008] of LEI; See also FIG. 10 shows a transistor simulator based on the models and parameters obtained by the deep neural network operating on pre-processed inputs and targeting transformed drain current … after deep neural network 50 has been used to obtain a set of weights that best models the transformed drain current, these final weights can be applied to deep neural network 50, Para. [0053] of LEI; See also goal of training is to find the values of the weights which can make the network output (predicted value) be the same as or closed to a fitting target (data) … optimization algorithm repeats this two phase cycle, forward calculation (propagation) and weights update, Para. [0037] of LEI; See also updated weights are applied to deep neural network and training data, Para. [0039] of LEI), and wherein each of the first ET data, the second ET data, and the third ET data includes at least one electrical parameter associated with transistor operation (simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; [input data is interpreted as corresponding to the first ET data]; See also deep neural network 50 generates a transformed drain current X_Ids in response to the pre-processed inputs and the final weights, Para. [0054] of LEI; [the second ET data is interpreted as corresponding to the model/neural network output/generated data, i.e., not measured]).
LEI does not appear to explicitly disclose the chip is/includes a wafer and arguably does not explicitly disclose the computer program produces a computer model.
PENG, however, is in the field of predicting performance of ICs based on electrical parameter test data using a computer model (Col. 1, Lines 9-23) and teaches performing electrical testing on wafers, which are part of the IC chip fabrication process (Col. 1, Lines 15-32, of PENG) and the computer program (on a computer/memory) produces a computer model (returning to FIG. 1, a next step 28 of the present method is to provide a computer program which produces a computer model that implements a function relating outputs to inputs, and run the program on a digital computer with the parametric values as inputs and the performance values as outputs to produce a computer correlation model 32 as shown in FIG. 6, Col. 5, Lines 61 – 67, of PENG).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to realize IC chip testing and wafer testing refer to similar/the same testing and to incorporate the model producing computer program of PENG with the electrical parameter modeling based on transistor size of LEI for the purpose of detecting any defects as early as possible so that time will not be wasted performing additional fabrication steps on defective circuits (Col. 1, Lines 15-24, of PENG).
LEI as modified by PENG also does not appear to explicitly disclose a test device comprising a probe card configured to perform electrical tests on a plurality of chips formed on a wafer; and fabricating a transistor structure on a semiconductor substrate based on the transistor model.
GOLDBERGER, however, is in the field of testing fabricated wafers (Abstract of GOLDBERFER) and teaches a test device comprising a probe card configured to perform electrical tests on a plurality of chips formed on a wafer (testing of the wafer, … this enables the application of various test signals at various levels and to various parts of the test circuit or the devices of the chip itself … more specifically, as shown in FIG. 4A, the metal layer Mx is patterned, so that different contact lines 430 are electrically coupled to different sections of the metal layer, e.g., Mx, Mx', Mx'' etc. … the testing is accomplished by the probe 440 contacting different locations, i.e., Mx, Mx', Mx'', or by using multiple probes on a probe card, Para. [0036] of GOLDBERGER); and fabricating a transistor structure on a semiconductor substrate based on the transistor model (reason layer M2 is important is that once fabrication of M2 is completed, every transistor on the substrate is connected to a metal line … design and process steps that are extensive, Para. [0011] of GOLDBERGER).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify the electrical parameter modeling based on transistor size of LEI with the probe card based design of GOLDBERGER for the purpose of enabling the application of various test signals at various levels and to various parts of the test circuit or the devices of the chip itself (Para. [0036] of GOLDBERGER).
Regarding claim 17, LEI as modified teaches the computing device of claim 16, wherein the transistor modeling tool is configured to determine values corresponding to a threshold voltage, saturation current, linear region current, and off-leakage current based on a size of a transistor (substrate leakage currents, Para. [0066] of LEI; See also simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; See also measurements may be taken from test devices on a test chip manufactured with a new process, and these measurements used as training data 34 (Vgs, Vds, . . . ) and target data 38 (Ids), Para. [0057] of LEI; [Examiner’s Note: “sampled” data appears to include measured test data based on Applicant’s as-filed specification at Para. [0029]; In addition, “transistor width and length” are interpreted as transistor size]; See also modification of LEI by PENG; See also a large number of tests are typically performed to obtain parameters … these values include, for example, V.sub.TN (threshold voltage of NMOS field effect transistors), I.sub.DN (source/drain current of NMOS transistors in the linear and saturation regions), V.sub.TP (threshold voltage of PMOS transistors), Col. 1, Lines 32-41, of PENG).
Regarding claim 19, LEI as modified teaches the computing device of claim 16, wherein the transistor modeling tool is configured to set a representative value for a threshold voltage, saturation current, linear region current, or off-leakage current based on a size of a transistor (substrate leakage currents, Para. [0066] of LEI; See also simulation input data 54 includes the voltages, temperature, and transistor width and length that are input by a design engineer during the circuit design process, Para. [0053] of LEI; See also measurements may be taken from test devices on a test chip manufactured with a new process, and these measurements used as training data 34 (Vgs, Vds, . . . ) and target data 38 (Ids), Para. [0057] of LEI; [Examiner’s Note: “sampled” data appears to include measured test data based on Applicant’s as-filed specification at Para. [0029]; In addition, “transistor width and length” are interpreted as transistor size]; See also modification of LEI by PENG; See also a large number of tests are typically performed to obtain parameters … these values include, for example, V.sub.TN (threshold voltage of NMOS field effect transistors), I.sub.DN (source/drain current of NMOS transistors in the linear and saturation regions), V.sub.TP (threshold voltage of PMOS transistors), Col. 1, Lines 32-41, of PENG).
Regarding claim 20, LEI as modified teaches the computing device of claim 16, wherein the transistor modeling tool is configured to perform the machine learning to generate data, which is not generated based on a size of a transistor, as the second ET data (goal of training is to find the values of the weights which can make the network output (predicted value) be the same as or closed to a fitting target (data) … optimization algorithm repeats this two phase cycle, forward calculation (propagation) and weights update, Para. [0037] of LEI; See also updated weights are applied to deep neural network and training data, Para. [0039] of LEI).
Claims 13 and 15 are rejected under 35 U.S.C. § 103 as being unpatentable over LEI et al. (U.S. Patent Application Publication No. 2019/0385047) in view of GOLDBERGER (U.S. Patent Application Publication No. 2007/0111340 A1) and MITSUTAKE et al. (U.S. Patent Application Publication No. 2002/0053065).
Regarding claim 13, LEI as modified teaches the transistor modeling apparatus of claim 11 (as applied to claim 11 above), wherein representative values are selected from the second ET data by a transistor modeling tool (goal of training is to find the values of the weights which can make the network output (predicted value) be the same as or closed to a fitting target (data) … optimization algorithm repeats this two phase cycle, forward calculation (propagation) and weights update, Para. [0037] of LEI; See also updated weights are applied to deep neural network and training data, Para. [0039] of LEI) but appears to fail to explicitly disclose wherein representative values are selected
MITSUTAKE, however, is in the field of identifying faults/defects/abnormalities in the semiconductor/IC manufacturing process (Para. [0003] of MITSUTAKE) and teaches wherein representative values are selected (the frequency distribution of faults is used to estimate a probability of faults in a repair unit of not exceeding the number of redundant circuits contained in the repair unit, and based on the estimated probability, estimate a yield after repair at the completion of the transistor forming process, Para. [0202] of MITSUTAKE).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify the prediction/estimation of values (representative values) in LEI with the transistor process distribution-based prediction/estimation of values in MITSUTAKE for the purpose of finding and correcting abnormalities/defects in manufacturing processes, to improve the productivity of semiconductor devices (Para. [0003] of MITSUTAKE).
Regarding claim 15, LEI teaches the transistor modeling apparatus of claim 11 (as applied to claim 11 above), wherein the third ET data includes values measured from a test element group (TEG) (more test devices having varying sizes and shapes were added and tested to obtain values for these additional parameters … automated measurement equipment allowed device model parameters to be extracted more quickly, Para. [0006] of LEI; See also after discussion of problems with two-dimensional modeling for nanometer devices in Para. [0007] of LEI, LEI teaches Artificial Neural Networks (ANN) are being used to generate device models and to select parameters … Artificial Neural Networks are especially useful for processing large amounts of data in complex ways that are hard to define using traditional computer programs … instead of being programmed with instructions, training data is input to a neural network and compared to the expected output, then adjustments are made within the neural network and the training data is again processed and outputs compared to generate further adjustments to the neural network, Para. [0008] of LEI) but appears to fail to explicitly disclose a test element group (TEG) corresponding to at least one predetermined shot region of the wafer.
MITSUTAKE, however, is in the field of identifying faults/defects/abnormalities in the semiconductor/IC manufacturing process (Para. [0003] of MITSUTAKE) and teaches a test element group (TEG) corresponding to at least one predetermined shot region of the wafer (the "search target" is an object on which the presence of clustering faults is tested or located … example of the unit cell is a "block" formed by dividing a chip into at least two blocks, a "group" formed by gathering at least two chips together, a "shot area" serving as a lithography unit, a wafer, and a product lot. A unit cell must be smaller than a search target, Para. [0012] of MITSUTAKE; See also shot area(s), Paras. [0087], [0105], [0123] & [0191] of MITSUKAKE).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify the transistor/wafer testing group in LEI with the testing group corresponding to a shot region of a wafer in MITSUTAKE for the purpose of finding and correcting abnormalities/defects in manufacturing processes, to improve the productivity of semiconductor devices (Para. [0003] of MITSUTAKE).
Claim 18 is rejected under 35 U.S.C. § 103 as being unpatentable over LEI et al. (U.S. Patent Application Publication No. 2019/0385047) in view of PENG et al. (U.S. Patent No. 6,028,994) in view of GOLDBERGER (U.S. Patent Application Publication No. 2007/0111340 A1), and further in view of MITSUTAKE et al. (U.S. Patent Application Publication No. 2002/0053065).
Regarding claim 18, LEI as modified teaches the computing device of claim 16 (as applied to claim 16 above) and machine learning for generating expected outputs (Para. [0008] of LEI) but appears to fail to explicitly disclose wherein the transistor modeling tool is configured to output a prediction trend that indicates transistor process distribution or measurement noise
MITSUTAKE, however, is in the field of identifying faults/defects/abnormalities in the semiconductor/IC manufacturing process (Para. [0003] of MITSUTAKE) and teaches wherein the transistor modeling tool is configured to output a prediction trend that indicates transistor process distribution or measurement noise (the frequency distribution of faults is used to estimate a probability of faults in a repair unit of not exceeding the number of redundant circuits contained in the repair unit, and based on the estimated probability, estimate a yield after repair at the completion of the transistor forming process, Para. [0202] of MITSUTAKE).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify the transistor/semiconductor testing focused machine learning in LEI with the transistor process distribution-based prediction/estimation of values in MITSUTAKE for the purpose of finding and correcting abnormalities/defects in manufacturing processes, to improve the productivity of semiconductor devices (Para. [0003] of MITSUTAKE).
Conclusion
The prior art previously made of record and not relied upon is considered pertinent to applicant's disclosure:
BURCH et al. (U.S. Patent Publication No. 2021/0279388) teaches, at Para. [0014], “testing the scribe line structures, and before dicing up the wafer into individual dies, each integrated circuit formed on a die is subject to a variety of further tests … tests are parametric in nature, obtaining numerical values as responses for parametric tests of, e.g., ring oscillator frequencies, current/voltage values for a particular size transistor, etc.”
SCHOBER et al. (U.S. Patent Publication No. 2020/0395905) teaches, at Para. [0160], “single minimum sized iFET, with inputs from 1 pico-ampere to 10 micro-amperes, using the same circuit in simulation …. noise floor limits … iFETS can be constructed with different length to width proportions with very predictably differing results.”
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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JOHN P. HOCKER
Examiner
Art Unit 2189
/JOHN P HOCKER/Examiner, Art Unit 2189
/REHANA PERVEEN/Supervisory Patent Examiner, Art Unit 2189
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