DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The rejections from the Office Action of 6/6/2025 are hereby withdrawn. New grounds for rejection are presented below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Restaino et al., Optimization of Pre and Post Recipe Sensitivity for Unpatterned Wafer Defectivity Inspection, ASMC, 2016 [hereinafter “Restaino”], Machuca (US 20180158672 A1), Knoch et al. (US 20050065739 A1)[hereinafter “Knoch”], Nishiyama et al. (US 20070001132 A1)[hereinafter “Nishiyama”], Weng et al. (US 20060037941 A1)[hereinafter “Weng”], and Yang (US 6103430 A).
Regarding Claim 1, Restaino discloses a method for determining ultrafine particle defects [Page 206 – “As dimensions shrink with each successive semiconductor technology node, the critical size of defects that can impact yield also shrinks. Monitoring the health of process equipment rigorously and regularly for key sources of contamination must be performed.”], performed by a surface inspection device [Page 207, 1st column – “Dark field bare wafer inspection is well established methodology for tool and process monitoring in IC manufacturing labs. … In today’s state of the art chip fabrication plants, a methodology called Defect Source Analysis (DSA) is performed using commercially available software [2].”See Fig. 9.] comprising:
detecting first defects on a surface of a silicon wafer [See Fig. 1 on Page 207.Page 206 – “Getting accurate data of real added defects is complicated for processes that involve film deposition due to decoration effects caused by the film conforming over the pre-existing defects. In this study, we bring out a clear methodology in optimizing the pre/post monitoring sizes of defects in order to minimize the effect of false adders.”Page 208 – “The premeasurements are taken prior to deposition of the film, usually on a bare silicon substrate. Detecting as many preexisting defects as possible fundamentally reduces the likelihood that a defect that has “grown” as a result of the deposition of a film will be detected as an adder in the inspection post deposition. Using the minimum threshold available allows detection of the most pre-existing defects, which can then be filtered out using DSA when combined with the post scan.”];
forming a thin film on the silicon wafer; detecting second defects on the surface of the silicon wafer having the thin film formed thereon [See Fig. 2 on Page 207.Page 208 – “Once measured, the film to be monitored is deposited by the process tool, and then sent back to the dark field bare wafer inspection equipment.”];
comparing the first defects with the second defects to determine whether or not there are additional defects; removing noise from the additional defects (by a second defect detector); and displaying a map including, as the additional defects, ones of the second defects that do not correspond to the first defects and omitting other ones of the second defects that correspond to the first defects [See Fig. 3 on Page 207.Page 208 – “After the post inspection, a detailed sizing analysis is done to determine the growth of defects due to decoration effect.”Page 207 – “Defect Source Analysis (DSA) is performed using commercially available software [2]. DSA is the process where the post inspection is overlayed with the pre inspection in order to subtract out common defects and focus only on what was added by the process.”See Fig. 9.]; wherein sizes of the first defects formed before forming the thin film are smaller than sizes of the second defects after forming the thin film [Page 208 – “a defect that has “grown” as a result of the deposition of a film.”Page 208 – “the growth of defects due to decoration effect.”See Table 1 on Page 210 – “Measured Defect size growth (nm)”].
Restaino fails to disclose that the first defects and the second defects include bumps and are caused by the water itself or include particles and are caused by a wafer manufacture environment, and the thin film is a silicon nitride film(Si3N4) formed by low-pressure chemical vapor deposition(LPCVD).
However, Machuca discloses that these are a known type of defect produced in a known type of product by a known type of tool [See Paragraph [0023]]. It would have been obvious to perform the analysis relative to such a type of product in order to assess the extent of any defects present and to ascertain where such defects were produced.
Restaino fails to disclose that the step of determining whether or not there are additional defects comprises determining second defects located beyond a predetermined distance from the first defects to be additional defects.
However, Knoch discloses evaluating whether or not detected defects are additive in such a manner [See Fig. 5A and Paragraph [0066]]. It would have been obvious to take such an approach in order to more accurately detect adder defects.
Restaino fails to disclose that the step of removing noise from the additional defects comprises assigning a specific symbol to each of second defects based on characteristics of second defects by a second defect detector (although Restaino discloses multiple defect detectors, see Fig. 9).
However, Nishiyama discloses assigning different symbols to defects based on the size of the defect [See Fig. 8B and Paragraph [0146]]. It would have been obvious to do so in order to highlight the nature of the detected defects.
Nishiyama fails to disclose that the specific symbol assigned to each of the second defects is A, B, or C, and among the specific symbols A to C, the second defects having the specific symbol C are the largest and the second defects having the specific symbol B are the smallest.
However, Nishiyama discloses assigning different symbols to defects based on the size of the defect [See Fig. 8B and Paragraph [0146]]. It would have been obvious to assign letters as the symbols [Nishiyama uses “X” as a symbol, which is a letter. See also the use of letters in the “conventional” manner that corresponds to Fig. 1 of the instant Specification.] in order to highlight the nature of the detected defects as a design choice. Choosing the symbols in the manner recited amounts to an arbitrary and obvious design choice that has no functional effect and amounts to mere preference. For example, Restaino discloses that some defects were previously detected and grow larger in size [Page 208 of Restaino – “Often when a film is deposited on a wafer, preexisting defects on the substrate will be highlighted by that film which causes the original defect to scatter more light, and therefore appear to be larger.”]; it would have been obvious to arbitrarily label those defects “C” so that they can be tracked. Restaino also discloses that some defects are initially missed because they are too small to be detected [Page 207 – “While this methodology refines the particle detection process to allow the user to focus on the truly added defects, it is still common to have preexisting defects missed in the initial inspection show up as adders in the post inspection.”]; it would have been obvious to arbitrarily label those defects “B” so that they can be tracked. Weng teaches that some existing defects shrink after depositing a film on them [See Figs. 2 and 3]; it would have been obvious to arbitrarily label those types of defects “A” so that they can be tracked.
The combination would disclose that the second defects having the specific symbol C [Arbitrary and obvious design choice.] are determined to be noise [Exclusion of the pre-scan defects (which would be large in size per Fig. 6 of Restaino).Page 208 of Restaino – “Often when a film is deposited on a wafer, preexisting defects on the substrate will be highlighted by that film which causes the original defect to scatter more light, and therefore appear to be larger.”];
that the second defects having the specific symbol A [Arbitrary and obvious design choice.] comprise particle defects and bump defects [See Fig. 6 of Restaino, the picture of the particle that has been covered by the post-layer film in the shape of a bump.];
that the particle defects and the bump defects, among the second defects having the specific symbol A [Arbitrary and obvious design choice.], are determined to be noise [Exclusion of the pre-scan defects (which would be large in size per Fig. 6 of Restaino).Page 208 of Restaino – “Often when a film is deposited on a wafer, preexisting defects on the substrate will be highlighted by that film which causes the original defect to scatter more light, and therefore appear to be larger.”]; and
that the second defects having the specific symbol B [Arbitrary and obvious design choice.] comprise ultrafine particle defects and bump defects [Page 207 of Restaino – “While this methodology refines the particle detection process to allow the user to focus on the truly added defects, it is still common to have preexisting defects missed in the initial inspection show up as adders in the post inspection.”See Fig. 6 of Restaino, the picture of the particle that has been covered by the post-layer film in the shape of a bump.Page 208 of Restaino – “Often when a film is deposited on a wafer, preexisting defects on the substrate will be highlighted by that film which causes the original defect to scatter more light, and therefore appear to be larger.”].
Restaino also fails to disclose removing, from the silicon wafer, the ones of the additional defects remaining after removing noise. However, Yang discloses a manner of repairing identified bump and divot wafer defects [See Abstract]. It would have been obvious to remove identified wafer defects in order to repair the wafer.
Regarding Claim 10, the combination would disclose that the ultrafine particle defects [Page 207 of Restaino – “While this methodology refines the particle detection process to allow the user to focus on the truly added defects, it is still common to have preexisting defects missed in the initial inspection show up as adders in the post inspection.”], among the second defects having the specific symbol B [Arbitrary and obvious design choice.], have a smaller size than particle defects [See the sizing of potentially-missed “fence sitters” in Fig. 4 of Restaino.], among the second defects having the specific symbol A [Arbitrary and obvious design choice.].
Regarding Claim 11, the combination would disclose that the bump defects [Page 207 of Restaino – “While this methodology refines the particle detection process to allow the user to focus on the truly added defects, it is still common to have preexisting defects missed in the initial inspection show up as adders in the post inspection.”See Fig. 6 of Restaino, the picture of the particle that has been covered by the post-layer film in the shape of a bump.Page 208 of Restaino – “Often when a film is deposited on a wafer, preexisting defects on the substrate will be highlighted by that film which causes the original defect to scatter more light, and therefore appear to be larger.”], among the second defects having the specific symbol B [Arbitrary and obvious design choice.], have a smaller size [See the sizing of potentially-missed “fence sitters” in Fig. 4 of Restaino.] than bump defects [Exclusion of the pre-scan defects (which would be large in size per Fig. 6 of Restaino).], among the second defects having the specific symbol A [Arbitrary and obvious design choice.].
Response to Arguments
Applicant argues:
PNG
media_image1.png
131
789
media_image1.png
Greyscale
PNG
media_image2.png
416
784
media_image2.png
Greyscale
Examiner’s Response:
The corresponding rejections are hereby withdrawn.
Applicant argues:
PNG
media_image3.png
79
787
media_image3.png
Greyscale
PNG
media_image4.png
269
785
media_image4.png
Greyscale
Examiner’s Response:
The Examiner respectfully disagrees. Restaino discloses a map where second defects are displayed that do not correspond to the first defects [See Fig. 3 on Page 207.Page 208 – “After the post inspection, a detailed sizing analysis is done to determine the growth of defects due to decoration effect.”Page 207 – “Defect Source Analysis (DSA) is performed using commercially available software [2]. DSA is the process where the post inspection is overlayed with the pre inspection in order to subtract out common defects and focus only on what was added by the process.”].
Applicant argues:
PNG
media_image5.png
322
788
media_image5.png
Greyscale
PNG
media_image6.png
79
780
media_image6.png
Greyscale
…
PNG
media_image7.png
467
788
media_image7.png
Greyscale
PNG
media_image8.png
78
784
media_image8.png
Greyscale
Examiner’s Response:
The Examiner respectfully disagrees. Nishiyama discloses assigning different symbols to defects based on the size of the defect [See Fig. 8B and Paragraph [0146]]. It would have been obvious to assign letters as the symbols [Nishiyama uses “X” as a symbol, which is a letter. See also the use of letters in the “conventional” manner that corresponds to Fig. 1 of the instant Specification.] in order to highlight the nature of the detected defects as a design choice. Choosing the symbols in the manner recited amounts to an arbitrary and obvious design choice that has no functional effect and amounts to mere preference. For example, Restaino discloses that some defects were previously detected and grow larger in size [Page 208 of Restaino – “Often when a film is deposited on a wafer, preexisting defects on the substrate will be highlighted by that film which causes the original defect to scatter more light, and therefore appear to be larger.”]; it would have been obvious to arbitrarily label those defects “C” so that they can be tracked. Restaino also discloses that some defects are initially missed because they are too small to be detected [Page 207 – “While this methodology refines the particle detection process to allow the user to focus on the truly added defects, it is still common to have preexisting defects missed in the initial inspection show up as adders in the post inspection.”]; it would have been obvious to arbitrarily label those defects “B” so that they can be tracked. Weng teaches that some existing defects shrink after depositing a film on them [See Figs. 2 and 3]; it would have been obvious to arbitrarily label those types of defects “A” so that they can be tracked.
The referred-to features of Restaino are not relied on in the grounds for rejection. Nishiyama is not relied on as disclosing the evaluation of wafers formed before/after the formation of a film.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20100136717 A1 – APPARATUS AND METHOD TO INSPECT DEFECT OF SEMICONDUCTOR DEVICE
US 20040033632 A1 – METHOD OF CALCULATING THE REAL ADDED DEFECT COUNTS
US 20040084622 A1 – Specimen Current Mapper
US 20040246472 A1 – Method And Apparatus For Defect Detection
US 5971586 A – Identifying Causes Of Semiconductor Production Yield Loss
US 6407386 B1 – System And Method For Automatic Analysis Of Defect Material On Semiconductors
Carman et al., Isolating the Killer Defect, IEEE, 1993
US 20160033420 A1 – Inspection For Multiple Process Steps In A Single Inspection Process
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE ROBERT QUIGLEY whose telephone number is (313)446-4879. The examiner can normally be reached 11AM-9PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arleen Vazquez can be reached at (571) 272-2619. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KYLE R QUIGLEY/ Primary Examiner, Art Unit 2857