Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-4, 6-12, 14-17, and 19-23 are pending. Claims 5, 13, and 18 are canceled by Applicant. Claims 21-23 are newly added by Applicant.
Examiner Notes
Examiner cites particular paragraphs and/or columns and lines in the references as applied to Applicant’s claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The prompt development of a clear issue requires that the replies of the Applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Applicant’s Reply Not Fully Responsive
The communication filed on 01/26/2026 is not fully responsive to the prior Office action because Applicant failed to respond the claim objection to claim 14 which is repeated below. The response appears to be bona fide, but through an apparent oversight or inadvertence, consideration of some matter or compliance with some requirement has been omitted. Applicant is required to supply the omission or correction to thereby provide a full response to the prior Office action in the subsequent response.
Claim Objection
As per claim 14, in ll. 5, delete “been run”. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 6-12, 14-17, and 19-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (an abstract idea) without significantly more.
Step 1: The claim is a process, machine, manufacture, or composition of matter:
Claim 1. A method comprising.
Step 2A Prong One: The claim recites an abstract idea because it includes limitations that can be considered mental processes (concepts performed in the human mind including an observation, evaluation, judgment, and/or opinion). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind or via pen and paper, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea:
generating a performance indication that identifies how sensitive performance of the memory system is to the one or more timing parameters (abstract idea mental process i.e., see claim 2 below which further defines generating a performance indication as making a determination and/or claim 3 below which further defines generating a performance indication as ordering the multiple timing parameters).
Step 2A Prong Two: The abstract idea is not integrated into a practical application because the abstract idea is recited but for generically recited additional computer elements (i.e. data storage, processor, memory, computer readable medium, etc.) which do not add meaningful limitations to the abstract idea amounting to simply implementing the abstract idea on a generic computer using generic computing hardware and/or software (e.g. generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The generic computing components are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using the recited generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea:
executing, multiple times, at least one program that accesses physical memory of a memory system during execution using one or more timing parameters, wherein each of the multiple times includes executing the at least one program with a different value for the one or more timing parameters, the different value for the one or more timing parameters for each of the multiple times being automatically selected independent of user input (generic computing components performing extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea);
outputting the performance indication (generic computing components performing extra-solution activity of displaying data and/or sending/transmitting data).
Step 2B: The claim includes limitations which can be considered extra-solution activity (see MPEP 2106.05(g)) insufficient to amount to significantly more than the abstract idea because the additional limitations only perform at least one of collecting, gathering, displaying, generating, modifying, updating, storing, retrieving, sending, and receiving data/information data which are well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)II. The claim further includes limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). Therefore, the claim, and its limitations when considered separately and in combination, is directed to patent ineligible subject matter:
executing, multiple times, at least one program that accesses physical memory of a memory system during execution using one or more timing parameters, wherein each of the multiple times includes executing the at least one program with a different value for the one or more timing parameters, the different value for the one or more timing parameters for each of the multiple times being automatically selected independent of user input (extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea);
outputting the performance indication (extra-solution activity of displaying data and/or sending/transmitting data).
Claim 2. The method of claim 1, the generating the performance indication including generating the performance indication by determining how much each change of a particular value in each of the one or more timing parameters changes a performance value resulting from execution of the at least one program (abstract idea mental process).
Claim 3. The method of claim 1, the one or more timing parameters including multiple timing parameters (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea), the generating the performance indication comprising generating the performance indication by ordering the multiple timing parameters in an order from a timing parameter of the multiple timing parameters that resulted in a maximum change in a performance value resulting from execution of the at least one program to a timing parameter of the multiple timing parameters that resulted in a minimum change in the performance value resulting from execution of the at least one program (abstract idea mental process).
Claim 4. The method of claim 1, further comprising receiving user input identifying the at least one program (extra-solution activity of receiving data).
Claim 6. The method of claim 1, further comprising selecting, for each execution of the at least one program, a value for the one or more timing parameters that is within a range of values that do not result in the memory system becoming nonfunctional (abstract idea mental process).
Claim 7. The method of claim 1, further comprising:
receiving user input of a particular value for a particular timing parameter of the one or more timing parameters (extra-solution activity of receiving data);
predicting a performance value resulting from execution of the at least one program with the particular timing value (abstract idea mental process); and
displaying the predicted performance value (extra-solution activity of displaying data).
Claim 8. The method of claim 1, wherein the performance of the memory system comprises bandwidth of the memory system (abstract idea mental process).
Claim 9. The method of claim 1, wherein the performance of the memory system comprises latency of the memory system (abstract idea mental process).
Claim 10. The method of claim 1, wherein the performance of the memory system comprises power usage of the memory system (abstract idea mental process).
Step 1: The claim is a process, machine, manufacture, or composition of matter:
Claim 11. A system comprising.
Step 2A Prong One: The claim recites an abstract idea because it includes limitations that can be considered mental processes (concepts performed in the human mind including an observation, evaluation, judgment, and/or opinion). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind or via pen and paper, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea:
generate a performance indication that identifies a sensitivity of the memory system to the one or more timing parameters, based on at least one performance value obtained for each of the multiple executions, wherein the at least one performance value quantifies a performance of the memory system relative to the one or more timing parameters (abstract idea mental process i.e., see claim 12 below which further defines generating a performance indication as making a determination).
Step 2A Prong Two: The abstract idea is not integrated into a practical application because the abstract idea is recited but for generically recited additional computer elements (i.e. data storage, processor, memory, computer readable medium, etc.) which do not add meaningful limitations to the abstract idea amounting to simply implementing the abstract idea on a generic computer using generic computing hardware and/or software (e.g. generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The generic computing components are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using the recited generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea:
memory setting circuitry (generic computing components); and
a processor (generic computing components) configured to execute, multiple times, at least one program that accesses physical memory of a memory system during execution using one or more timing parameters, wherein each of the multiple times includes execution of the at least one program with a different value for the one or more timing parameters, the different value for the one or more timing parameters for each of the multiple times being automatically selected, independent of user input, from a range of values defined by a minimum safe value and a maximum safe value (generic computing components for performing extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea); and
evaluation circuitry (generic computing components) to: output the performance indication (generic computing components for performing extra-solution activity of displaying data and/or sending/transmitting data).
Step 2B: The claim includes limitations which can be considered extra-solution activity (see MPEP 2106.05(g)) insufficient to amount to significantly more than the abstract idea because the additional limitations only perform at least one of collecting, gathering, displaying, generating, modifying, updating, storing, retrieving, sending, and receiving data/information data which are well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)II. The claim further includes limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). Therefore, the claim, and its limitations when considered separately and in combination, is directed to patent ineligible subject matter:
memory setting circuitry; and
a processor configured to execute, multiple times, at least one program that accesses physical memory of a memory system during execution using one or more timing parameters, wherein each of the multiple times includes execution of the at least one program with a different value for the one or more timing parameters, the different value for the one or more timing parameters for each of the multiple times being automatically selected, independent of user input, from a range of values defined by a minimum safe value and a maximum safe value (extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea); and
evaluation circuitry to: and output the performance indication (extra-solution activity of displaying data and/or sending/transmitting data).
Claim 12. The system of claim 11, wherein to generate the performance indication is to generate the performance indication by determining how much each change of a particular value in each of the one or more timing parameters changes the at least one performance value resulting from execution of the at least one program (abstract idea mental process).
Claim 14. The system of claim 11, further comprising prediction circuitry (generic computing components) to receive user input of a particular value for a particular timing parameter of the one or more timing parameters (extra-solution activity of receiving data), predict a performance value resulting from executing the at least one program with the particular timing value (abstract idea mental process), and output the predicted performance value (extra-solution activity of displaying data and/or sending/transmitting data).
Claim 15. The system of claim 11, wherein the performance of the memory system comprises one or more of bandwidth of the memory system, latency of the memory system, or power usage of the memory system (extra-solution activity of displaying data and/or sending/transmitting data).
Step 1: The claim is a process, machine, manufacture, or composition of matter:
Claim 16. A computing device comprising.
Step 2A Prong One: The claim recites an abstract idea because it includes limitations that can be considered mental processes (concepts performed in the human mind including an observation, evaluation, judgment, and/or opinion). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind or via pen and paper, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea:
generate, for each of the multiple times, a performance indication that identifies how sensitive performance of the memory system is to a respective combination of values for the plurality of timing parameters by ordering the plurality of timing parameters based on a respective contribution to changes in a performance value resulting from execution of the at least one program the multiple times (abstract idea mental process i.e., see claim 17 below which defines generating the performance indication by making a determination).
Step 2A Prong Two: The abstract idea is not integrated into a practical application because the abstract idea is recited but for generically recited additional computer elements (i.e. data storage, processor, memory, computer readable medium, etc.) which do not add meaningful limitations to the abstract idea amounting to simply implementing the abstract idea on a generic computer using generic computing hardware and/or software (e.g. generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The generic computing components are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using the recited generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea:
a memory system (generic computing component); and
a processor (generic computing component) to:
execute, multiple times, at least one program that accesses physical memory of the memory system during execution using a plurality of timing parameters, wherein each of the multiple times includes executing the at least one program with a different value for the plurality of timing parameters, the different value for the plurality of timing parameters for each of the multiple times being automatically selected, independent of user input, from a range of values defined by a minimum safe value and a maximum safe value (generic computing component for performing extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea); and
output the performance indication (generic computing component for performing extra-solution activity of displaying data and/or sending/transmitting data).
Step 2B: The claim includes limitations which can be considered extra-solution activity (see MPEP 2106.05(g)) insufficient to amount to significantly more than the abstract idea because the additional limitations only perform at least one of collecting, gathering, displaying, generating, modifying, updating, storing, retrieving, sending, and receiving data/information data which are well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)II. The claim further includes limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). Therefore, the claim, and its limitations when considered separately and in combination, is directed to patent ineligible subject matter:
a memory system; and
a processor to:
execute, multiple times, at least one program that accesses physical memory of the memory system during execution using a plurality of timing parameters, wherein each of the multiple times includes executing the at least one program with a different value for the plurality of timing parameters, the different value for the plurality of timing parameters for each of the multiple times being automatically selected, independent of user input, from a range of values defined by a minimum safe value and a maximum safe value (extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea); and
output the performance indication (extra-solution activity of displaying data and/or sending/transmitting data).
Claim 17. The computing device of claim 16, wherein to generate the performance indication is to generate the performance indication by determining how much each change of a particular value in each of the plurality of timing parameters changes a performance value resulting from execution of the at least one program (abstract idea mental process).
Claim 19. The computing device of claim 16, wherein the processor is further to receive user input of a particular value for a particular timing parameter of the plurality of timing parameters (extra-solution activity of receiving data), predict a performance value resulting from executing the at least one program with the particular value for the particular timing parameter (abstract idea mental process), and output the predicted performance value (extra-solution activity of displaying data and/or sending/transmitting data).
Claim 20. The computing device of claim 16, wherein the performance of the memory system comprises one or more of bandwidth of the memory system, latency of the memory system, and power usage of the memory system (abstract idea mental process).
Claim 21. The computing device of claim 16, wherein the plurality of timing parameters include at least two of: an active to active delay time within a same bank group; an active to active delay time within a different bank group; or a four active window time (extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim 22. The computing device of claim 16, wherein the plurality of timing parameters include at least two of: a write recovery time; a time between sending a column address and a response; a row address strobe to column address strobe delay time; a row precharge delay time; an active to precharge delay time; or an active to active/refresh delay time (extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim 23. The computing device of claim 16, wherein the plurality of timing parameters include at least two of: a refresh recovery delay time in a normal refresh mode; a refresh recovery delay time in a fine granularity refresh mode; a refresh recovery delay time in a same bank refresh mode; a write to read command delay second within a same bank group; a write to read command delay second within a different bank group; or a read to precharge delay (extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-9, 11-12, 14, 16-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over
Irshad et al. (US 2020/0097201) (hereinafter Irshad as previously cited) in view of
Hou et al. (US 2021/0208819) (hereinafter Hou as previously cited) in view of
Borer et al. (US 7,594,208) (hereinafter Borer).
As per claim 1, Irshad primarily teaches the invention as claimed comprising:
executing, multiple times, at least one program that accesses physical memory of a memory system during execution using one or more timing parameters, wherein each of the multiple times includes executing the at least one program with a different value for the one or more timing parameters (Irshad fig. 3 receive user input to select updated memory timing parameter values and operate the system with the updated memory timing configuration/parameter values and repeat the process; [0027] the process of dynamic reconfiguration of the memory controller using updated memory timing parameter values is repeated for one or more iterations until the user has identified a satisfactory memory timing configuration for the corresponding workload; fig. 4 receive user input selecting a particular memory timing configuration, dynamically implement the selected memory timing configuration, evaluate stability/effectiveness of memory subsystem using the implemented memory timing configuration and repeat the process; and [0031]-[0032] dynamically implement the memory timing parameter values of the selected memory timing configuration, execute a workload using the memory timing parameter values, evaluate stability/effectiveness of memory subsystem for the workload and repeat the process using a different selected memory timing parameter value); and
outputting the performance indication (Irshad fig. 5 and [0030] GUI through which the user observes various parameters or configurations of a corresponding graphics subsystem; [0029] different memory timing configurations may be provided as options to the user on the basis of stability of degree of expected performance enhancement; and [0032] user evaluates stability/effectiveness of memory subsystem for selected workload using the selected memory timings).
Irshad does not explicitly teach:
the different value for the one or more timing parameters for each of the multiple times being automatically selected independent of user input;
generating a performance indication that identifies how sensitive performance of the memory system is to the one or more timing parameters.
However, Hou teaches generating a performance indication that identifies how sensitive performance of the memory system is to the one or more timing parameters (Hou [0032] calculate the sensitivity of each service module to a memory access delay based on various memory timing parameters).
Hou and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou because the larger the memory access delay sensitivity value, the more sensitive the service module is to the memory access delay. If the memory access delay of the service modules is appropriately reduced, the performance of the service modules may be effectively improved. Therefore, the system may determine the target service module based on the memory access delay sensitivity value. Specifically, the executing body may use a service module having a memory access delay sensitivity value greater than a preset threshold as the target service module, or use a service module having the largest memory access delay sensitivity value as the target service module.
Irshad in view of Hou does not explicitly teach the different value for the one or more timing parameters for each of the multiple times being automatically selected independent of user input.
However, Borer teaches the different value for the one or more timing parameters for each of the multiple times being automatically selected independent of user input (claim 1 performing a timing analysis on the placed and routed design; each compilation using a set of input parameters, each input parameter having a value from a series of automatically selected values; each compilation using the timing analysis to generate output values for an output metric of the placed and routed design).
Borer and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou in view of Borer because it would provide a way for optimizing placement and synthesis of a circuit design on a programmable integrated circuit. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. The compile with the best output metrics can be selected which allow a user to automatically trade off compile-time to get a better-optimized circuit.
As per claim 2, Irshad further teaches the generating the performance indication including generating the performance indication by determining how much each change of a particular value in each of the one or more timing parameters changes a performance value resulting from execution of the at least one program ([0028]-[0029] iterate through various permutations of memory timing parameter values, and from those identify combinations of memory timing parameter values that are consistent with each other and which provide at least a target degree of stability and/or a degree of expected performance enhancement).
As per claim 3, Irshad further teaches the one or more timing parameters including multiple timing parameters (abstract), the generating the performance indication comprising generating the performance indication by ordering the multiple timing parameters in an order from a timing parameter of the multiple timing parameters that resulted in a maximum change in a performance value resulting from execution of the at least one program to a timing parameter of the multiple timing parameters that resulted in a minimum change in the performance value resulting from execution of the at least one program ([0009] update memory timing parameters that are better tuned to a particular workload as compared to default memory timing parameters; [0027] user can identify the particular set of memory timing parameter values that provide the best or more optimal memory operation performance for a given workload; [0028] each memory timing configuration level represents a set of memory timing parameter values that provides minimally stable operation of the memory controller and graphics memory, with each successive level providing tighter timing margins for one or more corresponding memory timing parameters. Simulation software can iterate through various permutations of memory timing parameter values, and from those identify combinations of memory timing parameter values that are consistent with each other and which provide at least a target degree of stability; [0032] user executes a workload using the selected memory timings and then evaluates the stability and/or effectiveness of the memory subsystem for the selected workload. In the event that the user is not satisfied with the performance under the current memory timings, the user may return to the configuration GUI and repeat the process with another selected memory timing configuration level until the user identifies a most optimal, or most satisfactory, memory timing configuration).
As per claim 6, Irshad further teaches selecting, for each execution of the at least one program, a value for the one or more timing parameters that is within a range of values that do not result in the memory system becoming nonfunctional ([0014]-[0015] default timing parameters may lead to excess memory latency and degraded system performance i.e., which could lead the memory system to become nonfunctional, and therefore the user is allowed to reconfigure the memory timing parameters to better tune the memory versus the default timing parameters).
As per claim 7, Irshad further teaches:
receiving user input of a particular value for a particular timing parameter of the one or more timing parameters ([0009] receive user input indicating a set of one or more updated memory timing parameters);
predicting a performance value resulting from execution of the at least one program with the particular timing value ([0029] memory timing configuration levels can be selected on, for example, the degree of expected performance enhancement and/or expectation of likely workload types); and
displaying the predicted performance value (fig. 5 and [0030] GUI through which the user observes various parameters or configurations of a corresponding graphics subsystem; [0029] different memory timing configurations may be provided as options to the user on the basis of stability of degree of expected performance enhancement; and [0032] user evaluates stability/effectiveness of memory subsystem for selected workload using the selected memory timings).
As per claim 8, Hou teaches wherein the performance of the memory system comprises bandwidth of the memory system ([0044] analyze the monitoring data and determine at least one parameter including the memory access bandwidth).
As per claim 9, Irshad further teaches wherein the performance of the memory system comprises latency of the memory system ([0009] the user thus is permitted to fine tune the memory controller to provide reduced memory access latency, and thus increased system performance, for an anticipated workload or other system configuration).
As per claim 11, Irshad primarily teaches the invention as claimed comprising:
memory setting circuitry (Irshad [0033] integrated circuit packages and circuitry); and
a processor (Irshad fig. 1, block 102) configured to execute, multiple times, at least one program that accesses physical memory of a memory system during execution using one or more timing parameters, wherein each of the multiple times includes execution of the at least one program with a different value for the one or more timing parameters (Irshad fig. 3 receive user input to select updated memory timing parameter values and operate the system with the updated memory timing configuration/parameter values and repeat the process; [0027] the process of dynamic reconfiguration of the memory controller using updated memory timing parameter values is repeated for one or more iterations until the user has identified a satisfactory memory timing configuration for the corresponding workload; fig. 4 receive user input selecting a particular memory timing configuration, dynamically implement the selected memory timing configuration, evaluate stability/effectiveness of memory subsystem using the implemented memory timing configuration and repeat the process; and [0031]-[0032] dynamically implement the memory timing parameter values of the selected memory timing configuration, execute a workload using the memory timing parameter values, evaluate stability/effectiveness of memory subsystem for the workload and repeat the process using a different selected memory timing parameter value); and
evaluation circuitry (Irshad [0033] integrated circuit packages and circuitry) to: output a performance indication that identifies a sensitivity of the memory system to the one or more timing parameters (Irshad fig. 5 and [0030] GUI through which the user observes various parameters or configurations of a corresponding graphics subsystem; [0029] different memory timing configurations may be provided as options to the user on the basis of stability of degree of expected performance enhancement; and [0032] user evaluates stability/effectiveness of memory subsystem for selected workload using the selected memory timings), based on at least one performance value obtained for each of the multiple executions, wherein the at least one performance value quantifies a performance of the memory system relative to the one or more timing parameters (Irshad [0028]-[0029] iterate through various permutations of memory timing parameter values, and from those identify combinations of memory timing parameter values that are consistent with each other and which provide at least a target degree of stability and/or a degree of expected performance enhancement).
Irshad does not explicitly teach:
the different value for the one or more timing parameters for each of the multiple times being automatically selected, independent of user input, from a range of values defined by a minimum safe value and a maximum safe value;
generate a performance indication that identifies a sensitivity of the memory system to the one or more timing parameters
However, Hou teaches generate a performance indication that identifies a sensitivity of the memory system to the one or more timing parameters (Hou [0032] calculate the sensitivity of each service module to a memory access delay based on various memory timing parameters).
Hou and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou because the larger the memory access delay sensitivity value, the more sensitive the service module is to the memory access delay. If the memory access delay of the service modules is appropriately reduced, the performance of the service modules may be effectively improved. Therefore, the system may determine the target service module based on the memory access delay sensitivity value. Specifically, the executing body may use a service module having a memory access delay sensitivity value greater than a preset threshold as the target service module, or use a service module having the largest memory access delay sensitivity value as the target service module.
Irshad in view of Hou does not explicitly teach the different value for the one or more timing parameters for each of the multiple times being automatically selected, independent of user input, from a range of values defined by a minimum safe value and a maximum safe value.
However, Borer teaches the different value for the one or more timing parameters for each of the multiple times being automatically selected, independent of user input (claim 1 performing a timing analysis on the placed and routed design; each compilation using a set of input parameters, each input parameter having a value from a series of automatically selected values; each compilation using the timing analysis to generate output values for an output metric of the placed and routed design), from a range of values defined by a minimum safe value and a maximum safe value (col. 11, ll. 20-28 the values of the input parameter that provided the best results in the first set of compilations are used to better target a range of values to be tested in the second set of compilations. The second set of compilations helps to more closely identify ranges of the selected input parameter that provide the best values for one or more output metrics. Additional sets of compilations can be performed to more closely identify optimum ranges of the selected input parameter values).
Borer and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou in view of Borer because it would provide a way for optimizing placement and synthesis of a circuit design on a programmable integrated circuit. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. The compile with the best output metrics can be selected which allow a user to automatically trade off compile-time to get a better-optimized circuit.
As per claim 12, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
As per claim 14, it has similar limitations as claim 7 and is therefore rejected using the same rationale.
As per claim 16, Irshad primarily teaches the invention as claimed comprising:
a memory system (Irshad fig. 1, block 106); and
a processor (Irshad fig. 1, block 102) to:
execute, multiple times, at least one program that accesses physical memory of the memory system during execution using a plurality of timing parameters, wherein each of the multiple times includes executing the at least one program with a different value for the plurality of timing parameters (Irshad fig. 3 receive user input to select updated memory timing parameter values and operate the system with the updated memory timing configuration/parameter values and repeat the process; [0027] the process of dynamic reconfiguration of the memory controller using updated memory timing parameter values is repeated for one or more iterations until the user has identified a satisfactory memory timing configuration for the corresponding workload; fig. 4 receive user input selecting a particular memory timing configuration, dynamically implement the selected memory timing configuration, evaluate stability/effectiveness of memory subsystem using the implemented memory timing configuration and repeat the process; and [0031]-[0032] dynamically implement the memory timing parameter values of the selected memory timing configuration, execute a workload using the memory timing parameter values, evaluate stability/effectiveness of memory subsystem for the workload and repeat the process using a different selected memory timing parameter value);
generate, for each of the multiple times, a performance indication to a respective combination of values for the one or more timing parameters (Irshad [0028]-[0029] iterate through various permutations of memory timing parameter values, and from those identify combinations of memory timing parameter values that are consistent with each other and which provide at least a target degree of stability and/or a degree of expected performance enhancement);
generate, for each of the multiple times, a performance indication by ordering the plurality of timing parameters based on a respective contribution to changes in a performance value resulting from execution of the at least one program the multiple times (Irshad [0009] update memory timing parameters that are better tuned to a particular workload as compared to default memory timing parameters; [0027] user can identify the particular set of memory timing parameter values that provide the best or more optimal memory operation performance for a given workload; [0028] each memory timing configuration level represents a set of memory timing parameter values that provides minimally stable operation of the memory controller and graphics memory, with each successive level providing tighter timing margins for one or more corresponding memory timing parameters. Simulation software can iterate through various permutations of memory timing parameter values, and from those identify combinations of memory timing parameter values that are consistent with each other and which provide at least a target degree of stability; [0032] user executes a workload using the selected memory timings and then evaluates the stability and/or effectiveness of the memory subsystem for the selected workload. In the event that the user is not satisfied with the performance under the current memory timings, the user may return to the configuration GUI and repeat the process with another selected memory timing configuration level until the user identifies a most optimal, or most satisfactory, memory timing configuration); and
output the performance indication (Irshad fig. 5 and [0030] GUI through which the user observes various parameters or configurations of a corresponding graphics subsystem; [0029] different memory timing configurations may be provided as options to the user on the basis of stability of degree of expected performance enhancement; and [0032] user evaluates stability/effectiveness of memory subsystem for selected workload using the selected memory timings).
Irshad does not explicitly teach:
the different value for the plurality of timing parameters for each of the multiple times being automatically selected, independent of user input, from a range of values defined by a minimum safe value and a maximum safe value;
generate, for each of the multiple times, a performance indication that identifies how sensitive performance of the memory system is.
However, Hou teaches generate, for each of the multiple times, a performance indication that identifies how sensitive performance of the memory system is (Hou [0032] calculate the sensitivity of each service module to a memory access delay based on various memory timing parameters).
Hou and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou because the larger the memory access delay sensitivity value, the more sensitive the service module is to the memory access delay. If the memory access delay of the service modules is appropriately reduced, the performance of the service modules may be effectively improved. Therefore, the system may determine the target service module based on the memory access delay sensitivity value. Specifically, the executing body may use a service module having a memory access delay sensitivity value greater than a preset threshold as the target service module, or use a service module having the largest memory access delay sensitivity value as the target service module.
Irshad in view of Hou do not explicitly teach the different value for the plurality of timing parameters for each of the multiple times being automatically selected, independent of user input, from a range of values defined by a minimum safe value and a maximum safe value.
However, Borer teaches the different value for the plurality of timing parameters for each of the multiple times being automatically selected, independent of user input (claim 1 performing a timing analysis on the placed and routed design; each compilation using a set of input parameters, each input parameter having a value from a series of automatically selected values; each compilation using the timing analysis to generate output values for an output metric of the placed and routed design), from a range of values defined by a minimum safe value and a maximum safe value (col. 11, ll. 20-28 the values of the input parameter that provided the best results in the first set of compilations are used to better target a range of values to be tested in the second set of compilations. The second set of compilations helps to more closely identify ranges of the selected input parameter that provide the best values for one or more output metrics. Additional sets of compilations can be performed to more closely identify optimum ranges of the selected input parameter values).
Borer and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou in view of Borer because it would provide a way for optimizing placement and synthesis of a circuit design on a programmable integrated circuit. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. The compile with the best output metrics can be selected which allow a user to automatically trade off compile-time to get a better-optimized circuit.
As per claim 17, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
As per claim 19, it has similar limitations as claim 7 and is therefore rejected using the same rationale.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Irshad in view of Hou in view of Borer, and further in view of Bienkowski et al. (US 9,336,115) (hereinafter Bienkowski as previously cited).
As per claim 4, Irshad in view of Hou in view of Borer do not explicitly teach receiving user input identifying the at least one program.
However, Bienkowski teaches receiving user input identifying the at least one program (col. 10, ll. 37-38 a user may input information identifying the program).
Bienkowski and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou in view of Borer in view of Bienkowski because it would provide an indication of problematic program code portions, such as a program code portion that had the longest execution time and/or that consumed the most resources as compared to other program code portions included in the program. In this way, a user may discover problems with a program and/or may learn about a program so that the user may improve the program.
Claims 10, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Irshad in view of Hou in view of Borer, and further in view of Roberts (US 2022/0113881) (as previously cited).
As per claim 10, Irshad in view of Hou in view of Borer do not explicitly teach wherein the performance of the memory system comprises power usage of the memory system.
However, Roberts teaches wherein the performance of the memory system comprises power usage of the memory system ([0021] there is an energy cost associated with cooling the memory domain, which can be traded off against memory performance by adjusting the temperature e.g., cooling power level and [0073] the control algorithm may be configurable based on minimum levels of memory performance e.g., bandwidth or latency or power savings).
Roberts and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou in view of Borer in view of Roberts because it would provide for an adaptive controller which can increase performance of the memory such as when the performance demand of the memory exceeds performance provided by current operating conditions. In other cases, the adaptive controller can reduce energy consumption of the memory, such as when the performance demand is less than the performance provided by current operating conditions. Thus, the adaptive controller can balance memory performance and energy consumption of the temperature-controlled memory based the host's access of the memory to increase energy efficiency of the computing system relative to a given level of performance. The adaptive controller can control and optimize performance of the memory for short-term or long-term changes in memory access.
As per claim 15, it has similar limitations as claims 8-10 and is therefore rejected using the same rationale.
As per claim 20, it has similar limitations as claim 15 and is therefore rejected using the same rationale.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Irshad in view of Hou in view of Borer, and further in view of Jin (US 2021/0181951).
As per claim 21, Irshad in view of Hou in view of Borer do not explicitly teach wherein the plurality of timing parameters include at least two of: an active to active delay time within a same bank group; an active to active delay time within a different bank group; or a four active window time.
However, Jin teaches wherein the plurality of timing parameters include at least two of: an active to active delay time within a same bank group; an active to active delay time within a different bank group; or a four active window time ([0075] tRRD_S, tCCD_S, tCCD_L, tRRD_L, tFAW, tRC i.e., see instant specification [0034]).
Jin and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou in view of Borer in view of Jin because it would provide for a weight which may be stored in such a manner that the read bandwidth of the weights, which are simultaneously or within a limited period of time read for the operation, is maximized and thus the data read speed may be improved. An address converter may receive a physical address of each weight set including an input node ID and an output node ID associated with the weight set in the operation processing, and store the weight set in a memory region corresponding to the memory address by mapping the physical address of the host to the memory address in such a manner that the number of weights simultaneously or within a limited period of time read is maximized, for example, the maximum read bandwidth is guaranteed. Weights may be read using the maximum bandwidth of the memory device and thus the latency of the operation may be minimized. The memory address of a memory division having relatively fast access speed may be mapped to the physical address frequently changed and thus the read speed may be improved.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Irshad in view of Hou in view of Borer, and further in view of Richter et al. (US 2020/0210110) (hereinafter Richter).
As per claim 22, Irshad in view of Hou in view of Borer do not explicitly teach wherein the plurality of timing parameters include at least two of: a write recovery time; a time between sending a column address and a response; a row address strobe to column address strobe delay time; a row precharge delay time; an active to precharge delay time; or an active to active/refresh delay time.
However, Richter teaches wherein the plurality of timing parameters include at least two of: a write recovery time; a time between sending a column address and a response; a row address strobe to column address strobe delay time; a row precharge delay time; an active to precharge delay time; or an active to active/refresh delay time ([0015] tRAS, tRP, tRFC; [0062] tRCDWR, tWR, tRAS, tWR, tRP, tRC; [0136] timing threshold comprises a tRC, a tRAS, a tRCDRD, a tRCDWR, a tRTP, a tWR, a tRP, a tRFC, a tCCD, a tRTW, a tWTR, or any combination thereof i.e., see instant specification [0034]).
Richter and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou in view of Borer in view of Richter because it would provide for one or more error detection code channels. The error detection code channels may be configured to communicate error detection signals, such as checksums, to improve system reliability. The related timers and/or counters e.g., for closing open rows in each bank of the detection component may be selected and each bank of the memory device may be autonomously closed once the timings of these related timers and/or counters are met and the banks may be closed without a risk of losing data content. In some cases, the memory device may enter a locked state after determining that a command is illegal and after completing the previous command currently being executed by the memory device. The memory device may wait to receive an indication e.g., from the host device before unlocking and continuing normal operation. In some cases, the memory device may enter a self-refresh mode during the locked state, which may enable the memory device to retain the memory content without any further commands from the host device.
As per claim 23, Irshad in view of Hou in view of Borer do not explicitly teach wherein the plurality of timing parameters include at least two of: a refresh recovery delay time in a normal refresh mode; a refresh recovery delay time in a fine granularity refresh mode; a refresh recovery delay time in a same bank refresh mode; a write to read command delay second within a same bank group; a write to read command delay second within a different bank group; or a read to precharge delay.
However, Richter teaches wherein the plurality of timing parameters include at least two of: a refresh recovery delay time in a normal refresh mode; a refresh recovery delay time in a fine granularity refresh mode; a refresh recovery delay time in a same bank refresh mode; a write to read command delay second within a same bank group; a write to read command delay second within a different bank group; or a read to precharge delay ([0015] tRAS, tRP, tRFC and [0062]-[0063] tRCDWR, tWR, tRAS, tWR, tRP, tRC, tRCDRD, tRTP, tRAS, tRC i.e., see instant specification [0034]).
Richter and Irshad are both concerned with computer memory and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Irshad in view of Hou in view of Borer in view of Richter because it would provide for one or more error detection code channels. The error detection code channels may be configured to communicate error detection signals, such as checksums, to improve system reliability. The related timers and/or counters e.g., for closing open rows in each bank of the detection component may be selected and each bank of the memory device may be autonomously closed once the timings of these related timers and/or counters are met and the banks may be closed without a risk of losing data content. In some cases, the memory device may enter a locked state after determining that a command is illegal and after completing the previous command currently being executed by the memory device. The memory device may wait to receive an indication e.g., from the host device before unlocking and continuing normal operation. In some cases, the memory device may enter a self-refresh mode during the locked state, which may enable the memory device to retain the memory content without any further commands from the host device.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
In the Remarks on pg. 9, Applicant argues that the claims are allowable because they are directed to a statutory category (Step 1). The examiner respectfully disagrees. A claim is not allowable merely because it satisfies Step 1 of the subject matter eligibility test (see MPEP 21016 II.). Even after the claim is identified as being a process, machine, manufacture or composition of matter, it must be evaluated under at least Step 2A Thus, for at least the reasons provided above, Applicant’s arguments are unpersuasive and the rejections are sustained.
On pg. 9-11 of the Remarks, Applicant alleges that the human mind is not possibly equipped to at least perform the execute/executing step of the independent claims. The examiner respectfully submits that the execute/executing step of the independent claims is not being interpreted as an abstract idea limitation. Rather, it is being interpreted as extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea. Hence, for at least the rationale provided above, Applicant’s arguments are not persuasive and the rejections are maintained.
In the Remarks on pg. 11-13, Applicant provides duplicate arguments as those presented in the Remarks dated 04/30/2025 on pg. 10-12. For the sake of brevity, the examiner’s rebuttal will not be reproduced herewith because the Applicant can view the examiner’s response in the final rejection dated 05/14/2025 on pg. 11-15. Applicant fails to respond to and/or interact with any of the examiner’s previous rebuttals while appearing to simply ignore and/or overlook them. Thus, for at least the reasons provided above, Applicant’s arguments are unpersuasive and the rejections are sustained. It is readily apparent and clearly evident that Applicant has a deficient, erroneous, and improper understanding of the 35 U.S.C. 101 abstract idea subject matter eligibility examination process. In the Remarks, Applicant neglects to provide any arguments pertaining to Step 2B while also providing other unpersuasive arguments that are clearly refuted by various portions of the MPEP. The examiner highly encourages Applicant to review MPEP 2106 prior to submitting any subsequent response.
On pg. 14-16 of the Remarks, Applicant alleges that Irshad and Hou do not teach the instant claim limitations as most recently amended. The examiner respectfully traverses. Applicant's arguments have been considered but are moot in view of the new grounds of rejection necessitated by Applicant’s amendments because the new grounds of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (i.e., the Borer reference). Hence, for at least the rationale provided above, Applicant’s arguments are not persuasive and the rejections are maintained.
In the Remarks on pg. 16-19, Applicant argues that Irshad and Hou do not teach the limitations of claim 3. The examiner respectfully disagrees. Irshad in at least [0009] discloses updating the timing parameter values that are better tuned to a particular workload as compared to default memory timing parameters, and in at least [0027] discloses identifying the particular set of memory timing parameter values that provide the best or more optimized memory operation performance for a given workload. Initially, it should be noted that Applicant’s instant claims recite multiple/a plurality of timing parameters, which under the broadest reasonable interpretation only requires two timing parameters. Hence, there are only two possible orderings: either the first timing parameter followed by the second timing parameter or vice versa. In that case one of the timing parameters would necessarily have to result in a maximum change in a performance value and the other timing parameter would necessarily have to result in a minimum change in the performance value. Irshad in [0009] discloses updating the timing parameter values that are better tuned to a particular workload as compared to default memory timing parameters. Here the updated timing parameter values could refer to the claimed timing parameters resulting in a maximum change in the performance value while the default memory timing parameters could refer to the claimed timing parameters resulting in a minimum change in the performance value. Irshad in [0027] discloses multiple timing parameters that provide more optimized memory operation performance for a given workload. The phrase “more optimized” is in relation to some other value. Therefore, Irshad implicitly teaches at least one more optimized timing parameter resulting in a maximum change in the performance value as compared to at least one other less optimized timing parameter resulting in a minimum change in the performance value. Finally, Irshad in [0036] states “the order in which activities are listed are not necessarily the order in which they are performed” which thus teaches any ordering of the multiple timing parameters. Thus, for at least the reasons provided above, Applicant’s arguments are unpersuasive and the rejections are sustained.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Buck et al. (US 2017/0199953) in at least [0024] disclose automatically selecting a timing parameter.
Zhang et al. (US 2020/0348740) in at least [0064] disclose incrementing a timing parameter until a predetermined range of values for the timing parameter are completed, and selecting a value for the timing parameter, within the predetermined range, which minimizes the voltage droop.
Dageville et al. (US 7,539,608) disclose techniques for determining effects, on a system, of values for a parameter that is used to manage memory for the system include generating data that indicates a workload and an actual performance of the system. The data is generated while processing the workload within the system using a first value for the parameter. Based on the data, an estimated performance is generated. The estimated performance is a performance that the system would have experienced if a second value for the parameter had been used to process the workload. The second value is different from the first value for the parameter. Using these techniques, an administrator can determine what change in system performance could be achieved by changing a value of the memory management parameter. Therefore the system administrator can better determine whether to make the change in the value of the memory management parameter.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam Lee whose telephone number is (571) 270-3369. The examiner can normally be reached on M-TH 8AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached on 571-272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam Lee/Primary Examiner, Art Unit 2198 February 10, 2026