Prosecution Insights
Last updated: August 17, 2026
Application No. 17/733,089

SYSTEM AND METHOD FOR MULTI-MODE RECEIVER

Final Rejection §103
Filed
Apr 29, 2022
Priority
Nov 11, 2021 — provisional 63/278,172
Examiner
FOTAKIS, ARISTOCRATIS
Art Unit
2633
Tech Center
2600 — Communications
Assignee
Texas Instruments Incorporated
OA Round
8 (Final)
72%
Grant Probability
Favorable
9-10
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
542 granted / 758 resolved
+9.5% vs TC avg
Strong +31% interview lift
Without
With
+30.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
36 currently pending
Career history
797
Total Applications
across all art units

Statute-Specific Performance

§101
4.5%
-35.5% vs TC avg
§103
54.2%
+14.2% vs TC avg
§102
18.4%
-21.6% vs TC avg
§112
17.2%
-22.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 758 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s amendment, filed May 08, 2026, with respect to the rejections of claims have been fully considered. Applicant's amendment necessitated the new grounds of rejection presented below by the use of the previously cited references of Reay et al (US 7,656,216) and Lam (US 5,822,598). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 8 – 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Reay et al (US 7,656,216) in view of Lam (US 5,822,598). Re claim 8, Reay teaches of a circuit comprising: a multimode interface having a first input and a second input (two input pins 510 and 515, Fig.5); a first receiver (#525, Fig.5, single-ended mode, Col 1, Lines 59 – 65, Col 4, Lines 13 – 40) having a signal input coupled to the first input of the multimode interface (CLK+ on pin #510, Fig.5) and a control input (from #520, Fig.5); a second receiver (#530, Fig.5, differential mode, Col 1, Lines 59 – 65, Col 4, Lines 13 – 40) having a first signal input (CLK+, Fig.5) coupled to the first input of the multimode interface (CLK+ on pin #510, Fig.5), a second signal input coupled to the second input of the multimode interface (CLK- on pin #515, Fig.5), and a control input (from #520, Fig.5), the first signal input coupled to the signal input of the first receiver (CLK+ is input to both receivers, Fig.5), and the control input of the second receiver coupled to the control input of the first receiver (output from 520 is coupled to both receivers, Figures 6 and 8); and a mode detector (#520, Fig.5) having an input (CLK-, Fig.5), coupled to the second input of the multimode interface (pin #515, Fig.5), and an output (as shown in Figures 5 – 6 and 8), the output coupled to the control input of the first receiver and to the control input of the second receiver (output from 520 is coupled to the control input of both receivers, Figures 6 and 8), the mode detector comprising: circuitry coupled to the multimode interface, the circuitry configured to determine a threshold voltage (predetermined relationship or condition, reference signal voltage, Col 2, Lines 62 – 67 to Col 3, Lines 1 – 17 and Col 4, lines 40 – 67, It would inherent that a circuitry would be required to generate the reference signal or voltage); and a comparator (#410, Fig.4 and #610, Fig.6) having a first input configured to receive the threshold voltage, a second input coupled to the first input of the multimode interface, and an output as the output of the mode detector (as shown in Figures 4 and 6); the mode detector configured to automatically detect a transmission mode of a received input signal, based on a comparison of the threshold voltage to a signal received from the first input of the multimode interface (differential or single-ended mode, Fig.6) and produce a selection signal at the output of the mode detector (output from #520, Figures 5 – 6), the selection signal being input to the control input of the first receiver and to the control input of the second receiver (as shown in Fig.5). However, Reay does not specifically teach of the selection signal being a single selection signal. Reay does not specifically teach of the circuitry configured to determine a threshold voltage is coupled between first and second voltage nodes. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have rearranged the inverter from the mode detector to the input of the DE receiver, since it has been held that rearranging parts of an invention involves routine skill in the art. In re Japikse, 86 USPQ 70. Lam teaches of a comparator (U2, Fig.2) that includes a second comparator input coupled to a circuitry that includes a voltage divider (R5, R4, Fig.2) coupled between first and second voltage nodes (as shown in Fig.2), and wherein a reference voltage of the voltage divider provides the threshold voltage (Col 5, Lines 45 - 60). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the circuitry coupled between first and second voltage nodes to generate the threshold voltage and perform an efficient voltage comparison. Re claim 9, Reay teaches of wherein the mode detector configured to enable the first receiver and disable the second receiver responsive to the detected transmission mode of the received input signal being the single-ended transmission mode (Col 4, lines 30 – 40). Re claim 10, Reay teaches of wherein the mode detector is further configured to enable the second receiver and disable the first receiver responsive to the detected transmission mode of the received input signal being the differential transmission mode (Col 4, lines 40 – 60). Re claim 11, Reay teaches of wherein the mode detector is further configured to automatically detect the transmission mode of the received input signal using a voltage received at the input (a voltage compared to the threshold voltage, Col 2, Lines 62 – 67 to Col 3, Lines 1 – 17 and Col 4, lines 40 – 67). Re claim 14, Reay and Lam teach all the limitations of claim 8 as well as Lam teaches of wherein the circuitry includes a voltage divider circuit (R5, R4, Fig.2). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the circuitry include a voltage divider so as to generate the threshold voltage and perform an efficient voltage comparison. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Reay in view of Devam et al (US 2011/0131356). Re claim 12, Reay teaches all the limitations of claim 8 except of wherein a value of the threshold voltage is based on an input voltage range of the differential transmission mode. Devam teaches of a value of the threshold voltage is based on an input voltage range of the differential transmission mode (Paragraph 0012). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the threshold voltage is based on an input voltage range of the differential transmission mode, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. Allowable Subject Matter Claims 1 – 7, 21 – 24 and 27 – 28 are allowed Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARISTOCRATIS FOTAKIS whose telephone number is (571)270-1206. The examiner can normally be reached M-F 8:30am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sam K Ahn can be reached on (571) 272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ARISTOCRATIS FOTAKIS/ Primary Examiner, Art Unit 2633
Read full office action

Prosecution Timeline

Show 11 earlier events
Apr 23, 2025
Non-Final Rejection mailed — §103
Aug 25, 2025
Response Filed
Oct 16, 2025
Final Rejection mailed — §103
Jan 16, 2026
Request for Continued Examination
Jan 28, 2026
Response after Non-Final Action
Feb 10, 2026
Non-Final Rejection mailed — §103
May 08, 2026
Response Filed
Jul 28, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

9-10
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+30.9%)
2y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 758 resolved cases by this examiner. Grant probability derived from career allowance rate.

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