DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 15, 16, 17,18, 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Likharev et al. Published in: IEEE Transactions on Applied Superconductivity
( Volume: 1, Issue: 1, March 1991), cited by applicants.
Re claim 1: The reference to Likharev et al , see figure (14) below, shows a superconducting multi-stage synchronous logic circuit structure, see top figure: a first clocked logic gate(LOGIC 1) that comprises Josephson junctions(X)(see fig 14 details of the logic) and has a single first clocked logic gate output(L1); a second clocked logic gate(LOGIC2) that comprises Josephson junctions (SAME CONFIG AS LOGIC1, see fig 14)and has a single second clocked logic gate output(L2); and an unclocked logic gate(AND) that comprises Josephson junctions and that has a first input connected in electrical communication with the first clocked logic gate output and has a second input connected in electrical communication with the second clocked logic gate output, wherein the Josephson junctions of the unclocked logic gate are arranged such that, in a single clock cycle that drives the first clocked logic gate and the second clocked logic gate, the unclocked logic gate produces a single signal(F) in response to the inputs of the first and second clocked logic gates.
Re claim 15: the unclocked logic gate is an asynchronous AND.
Re claim 16: RSFQ logic with the JJ allows for the inherent SFQ pulse development as is inherent(See page 8, second column and figure 9)
Re claim 17:the total inputs on the LOGIC 1,2 gates is equal to 4.
Re claim 18: the method steps being inherent to the above structure.
Re claim 19: the logic elements are Boolean, in that they can accept one of two possible values(0,1, or true, false) logic.
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Re claim 4: The structure above shows first clocked logic gate(LOGIC1) is a synchronous OR, and the second clocked logic gate (LOGIC2)is a synchronous OR.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2,3 and 5-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Likharev et al as applied to claim 1, above.
The reference to Likharev et al , see figure (14) below, shows a superconducting multi-stage synchronous logic circuit structure, see top figure: a first clocked logic gate(LOGIC 1) that comprises Josephson junctions(X)(see fig 14 details of the logic) and has a single first clocked logic gate output(L1); a second clocked logic gate(LOGIC2) that comprises Josephson junctions (SAME CONFIG AS LOGIC1, see fig 14)and has a single second clocked logic gate output(L2); and an unclocked logic gate(AND) that comprises Josephson junctions and that has a first input connected in electrical communication with the first clocked logic gate output and has a second input connected in electrical communication with the second clocked logic gate output, wherein the Josephson junctions of the unclocked logic gate are arranged such that, in a single clock cycle that drives the first clocked logic gate and the second clocked logic gate, the unclocked logic gate produces a single signal(F) in response to the inputs of the first and second clocked logic gates.
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Re claims 2,3, 5-13:
The reference does not list several conventional synchronous logic type elements where
first clocked logic gate is a synchronous AND/XOR, and the second clocked logic gate is a synchronous AND. Or, the first clocked logic gate is a synchronous XOR, and the second clocked logic gate is a synchronous OR. Or, the first clocked logic gate is a synchronous XOR, and the second clocked logic gate is a synchronous XOR.
Or, the first clocked logic gate is a synchronous inverter, and the second clocked logic gate is a synchronous AND. Or, the first clocked logic gate is a synchronous inverter, and the second clocked logic gate is a synchronous OR.
Or, the first clocked logic gate is a synchronous inverter, and the second clocked logic gate is a synchronous XOR. Or, the first clocked logic gate is a synchronous D- flip-flop, and the second clocked logic gate is a synchronous AND.
Or, the first clocked logic gate is a synchronous D- flip-flop(storage element), and the second clocked logic gate is a synchronous OR.
Or, the first clocked logic gate is a synchronous D- flip-flop, and the second clocked logic gate is a synchronous XOR.
With regards these combinations of logic elements being used instead of the ones shown by Likharev et al, that is, in place of the two OR gates, this is a simple matter of design consideration as these are conventional(basic logic gates and storage) Boolean logic elements that are combined together to derive a particular output as needed. They are all clocked/synchronous logic implementations or storage elements and conventional choices, for one of ordinary skill in the art, when designing from Boolean algebra truth tables, for example.
In light of the above it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have recognized that the OR gates shown by Likharev et al may be replaced with a combination of other logic type elements, as noted above, with latch type D FF’s also being part of the clocked logic elements as desired. A simple matter of design consideration for one of ordinary skill in the art to provide a more power efficient design.
Allowable Subject Matter
Claims 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The reference to Volkmann et al below show the use of the confluence buffer, however, it is clocked.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
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ARNOLD M. KINKEAD
Primary Examiner
Art Unit 2849
/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2849