DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The Amendment filed on 04/30/2025, responding to the Office action mailed on 02/04/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this office action are claims 1-10 and 16-25.
Information Disclosure Statement
The information disclosure statement submitted on 05/16/2025 has been considered by the Examiner. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 6, 8, and 10 are objected to because of the following informalities:
Claim 6, lines 12 and 13 recites “the well”, these should be corrected to -the semiconductor well- for claim consistency.
Claim 8, line 1 recites “the well”, it should be corrected to -the semiconductor well- for claim consistency.
Claim 10, line 7 recites “the structure gate”, it should read -the gate structure-.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-6, 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Verhaar (US 6,174,759).
Regarding Claim 1, Verhaar teaches an integrated circuit (Fig. 18), comprising: a non-volatile memory of an electrically erasable and programmable type (i.e., EEPROM, Col. 2, lines 53-56) including memory cells (EEPROM cell, A, Col. 4, lines 27-29), each memory cell including:
a state transistor (i.e. memory transistor in region A) including a gate structure (19, 21, 23) including:
a control gate (27) having a first surface (i.e., upper surface) opposite a second surface (i.e., bottom surface) along a first direction (i.e., vertical direction), the first surface having a first portion (i.e. portion of 27 next the floating gate 21) and a second portion (i.e., portion of 27 over the floating gate 21); and a floating gate (21) disposed on a face of a semiconductor well (i.e., upper surface of 1), the floating gate being between the control gate and the face of the semiconductor well along the first direction, the first surface being further from the floating gate along the first direction than the second surface, the first portion of the first surface having a first distance from the face of the semiconductor well along the first direction and the second portion of the first surface having a second distance from the face of the semiconductor well along the first direction that is greater than the first distance (the distance from the top surface of 27 to the surface of semiconductor well 1 in the second portion is greater than the distance between the two surfaces in the first portion); and
a source region and a drain region (either side of the memory transistor in area A) in the semiconductor well, the drain region including a first capacitive implant region (10) positioned predominantly under the gate structure and a lightly doped region (24 in middle of area A; since 38 is heavily doped, it makes region 24 next to it a lightly doped region, also served as n-type LDD region of HV access transistor) positioned predominantly outside the gate structure, the source region including a second capacitive implant region (24 in left of area A; see Fig. 9, col. 5 line 66 to col. 6 line 3) positioned predominantly outside the gate structure, the source region not including a lightly doped region.
Regarding Claim 3, Verhaar teaches the integrated circuit according to claim 1, wherein a channel region (portion of region 7 between region 24 and 10 in area A) of the well located under the gate structure, is delimited on either side by the first capacitive implant region and by the second capacitive implant region.
Regarding Claim 4, Verhaar teaches the integrated circuit according to claim 3, wherein the gate structure includes a dielectric layer (12 and 17, see col. 5 lines 10-13, 35-40) between the floating gate and the semiconductor well, the dielectric layer having a first thickness (12, approx. 25nm) and a second thickness (17, approx. 7.5nm) less than the first thickness, the channel region being positioned opposite to the first thickness, and the first capacitive implant region being positioned predominantly opposite to the second thickness. (see Fig. 18)
Regarding Claim 5, Verhaar teaches the integrated circuit according to claim 1, each memory cell further including: an access transistor (HV access transistor in area A) including a gate structure (22, 19, 23), and a source region (24) and a drain region (24) in the semiconductor well, the drain region of the access transistor including a lightly doped region positioned predominantly outside the gate structure of the access transistor, (see Fig. 9, col. 5 line 66 to col. 6 line 3)
and the source region of the access transistor including the same lightly doped region as the drain region of the state transistor, (see Fig. 18, HV access transistor shared a S/D region with the memory transistor, it is centrally located in region A between the two transistors) positioned predominantly outside the structure gate of the access transistor.
Regarding Claim 6, Verhaar teaches A device (Fig. 18, EEPROM cell area A), comprising:
a semiconductor substrate having a semiconductor well (1); a first transistor including a gate structure, the gate structure (21, 19, 23) including:
a floating gate (21) on the semiconductor well, the floating gate including a first portion (i.e., portion of 21 over channel portion) spaced apart from a surface of the well by a first distance (i.e., thickness of layer 12, approx. 25nm) and a second portion (i.e., portion of 21 over region 10) spaced apart from the surface of the well by a second distance (i.e., thickness of layer 17, approx. 7.5nm) the first distance being greater than the second distance;
a control gate (27) on the floating gate, the floating gate disposed between the semiconductor well and the control gate; the control gate having a first surface (i.e. top surface) opposite a second surface (i.e. bottom surface) along a first direction (i.e. vertical direction), the second surface being closer to the floating gate than the first surface along the first direction, the first surface having a first portion (i.e., portion of 27 next to 21) spaced apart from the surface of the well along the first direction by a third distance and a second portion (i.e., portion of 27 over 21) spaced apart from the surface of the well along the first direction by a fourth distance greater than the third distance
a source region and a drain region in the semiconductor well (region 24 on either side of the memory transistor), the drain region including a first capacitive implant region (10) extending under the gate structure and a lightly doped region (24) extending laterally outward beyond the gate structure, the source region including a second capacitive implant region (24) extending laterally outward beyond the gate structure, the source region not including a lightly doped region (24 in left of area A; see Fig. 9, col. 5 line 66 to col. 6 line 3.)
Regarding Claim 8, Verhaar teaches the device according to claim 6, wherein a channel region of the well located under the gate structure, (portion of region 7 between region 24 and 10 in area A) is delimited on either side by the first capacitive implant region and by the second capacitive implant region.
Regarding Claim 9, Verhaar teaches the device according to claim 8, wherein the gate structure includes a dielectric layer (12 and 17) between the floating gate and the semiconductor well, the dielectric layer having a first thickness (thickness of 12, approx. 25nm) and a second thickness (thickness of 17, approx. 7.5nm) less than the first thickness,
the channel region being positioned opposite to the first thickness, and the first capacitive implant region being positioned predominantly opposite to the second thickness. (See Fig. 18)
Regarding Claim 10, Verhaar teaches the device according to claim 6, further comprising: an access transistor (HV access transistor) including a gate structure (22, 19, 23) disposed on the semiconductor well, and a source region and a drain region in the semiconductor well, (region 24 on either side of HV access transistor), the drain region of the access transistor including a lightly doped region extending laterally outward beyond the gate structure of the access transistor, (see Fig. 9, col. 5 line 66 to col. 6 line 3) and the source region of the access transistor including the same lightly doped region as the drain region of the state transistor (see Fig. 18, HV access transistor shared a S/D region with the memory transistor, it is centrally located in region A between the two transistors), the source region extending laterally outward beyond the structure gate of the access transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 7 are rejected under 35 U.S.C. 103(a) as being unpatentable over Verhaar.
Initially, and with respect to claims, 2 and 7 note that a limitation in a claim with respect to the manner in which a claimed device is intended to be used does not differentiate the claimed device from a prior-art device if the prior art device teaches all structure limitations in the claims and the functional limitations are found to be inherent in the prior art device. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See Hewlett-Packard Co. v. Bausch & Lomb Inc. and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a device claim, and not the patentability of its functions (909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990)). As stated in Best, where the claimed and prior art product are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 f.2d 1252 1255, 195 USPQ 430, 433 (CCPA 1977).
NOTE that the applicant has burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
Verhaar disclose an integrated circuit, according to claim 1 and 6. In reference to the functional/intended use languages recited in claims 2 and 7, it is noted that Verhaar shows all aspects of the EEPROM memory device according to the instant invention and that limitations “wherein, in a nominal position of the gate structure and the second capacitive implant region, a minor portion of the second capacitive implant region is positioned under the gate structure, the minor portion having a substantially minimum size allowing compensating for a tolerance of variations in the dimensions and alignment of the gate structure, and a tolerance of variations in the dimensions and alignment of the capacitive implant regions.” are functions and intended usages of the device that does not affect the structure of the final device. Furthermore, device of Verhaar is capable of performing the claimed functions and intended usages.
Functional language must result in a structure difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963); Ex parte Masham, 2USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). In the instant case and as explained above, Verhaar shows all structure limitations specifically cited in the claim and it appears that the recited functional and intended usage limitations does not affect the structure of the device disclosed by Verhaar.
Claims 16-18, 20-25 are rejected under 35 U.S.C. 103 as being unpatentable over Verhaar in view of Tailliet (US 20200035304, previously cited).
Regarding Claim 16, Verhaar teaches a device, comprising:
a substrate with a semiconductor well (1);
a state transistor (i.e. memory transistor in EEPROM cell area A) overlapping the semiconductor well along a first direction (vertical direction), the state transistor including:
a control gate spaced from the semiconductor well along the first direction, the control gate including:
a first portion with a first thickness along the first direction (i.e. portion of 27 next to floating gate 21), the first portion being a first distance from the semiconductor well along the first direction; and a second portion with a second thickness along the first direction (i.e. portion of 27 over floating gate 21) equal to the first thickness (i.e. layer 27 is patterned layer 26, is of unform thickness via conformal deposition of layer 26, see Fig. 10 and 11), the second portion being a second distance from the semiconductor well along the first direction smaller than the first distance; and
a floating gate (21) between the control gate and the semiconductor well along the first direction;
a drain region in the semiconductor well, the drain region including a first capacitive implant region (10);
an access transistor (HV access transistor) coupled to the state transistor, the access transistor including: a first conductive gate (22) spaced from the semiconductor well along the first direction;
and a bit line, the access transistor being coupled in series between the drain of the state transistor and the bit line (col. 2, lines 2-5).
Verhaar does not provide teaching of a second conductive gate between the first conductive gate and the semiconductor well along the first direction for the access transistor.
Tailliet in the same field of endeavor provides a teaching for an EEPROM memory device with access transistor (22, Fig. 3), where the access transistor includes a second conductive gate (62) between the first conductive gate (64) and the semiconductor well (12) along the first direction (i.e., vertical direction).
Since Verhaar and Tailliet are in the same field of endeavor, a person having ordinary skill in the art at the time of invention would have readily recognized the desirability and advantages of modifying Verhaar, as suggested by Tailliet, by incorporating a second gate in the access transistor, sandwiched between the first gate and the semiconductor well. It is conventional to have dual gate design for access transistor in EEPROM cell, where it can also serve as the wordline or wordline contact in order to apply and/or transmit electric signals to/from the device. Tailliet's second gate electrode would have performed the same functions as in the combination, and no unexpected results would have arisen from the combination. All the claim elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1395 (Supreme Court 2007) (KSR).
Regarding Claim 17, Verhaar in view of Tailliet teaches the device according to claim 16, further comprising a first dielectric layer (Verhaar, 19) between the control gate and the floating gate.
Regarding Claim 18, Verhaar in view of Tailliet teaches the device according to claim 17, further comprising a second dielectric layer (Verhaar, 12 and 17) between the floating gate and the semiconductor well.
Regarding Claim 20, Verhaar in view of Tailliet teaches the device according to claim 16, further comprising: a third dielectric layer (Tailliet, 126, Fig. 6K) between the first and second conductive gates; and a fourth dielectric layer (66, Fig. 3) between the second conductive gate and the semiconductor well.
Regarding Claim 21, Verhaar in view of Tailliet teaches the device according to claim 16, wherein the control gate and the floating gate belong to a first gate structure of the state transistor (Verhaar, memory transistor, Fig. 18, EEPROM cell area A) and the first and second conductive gates belong to a second gate structure of the access transistor. (Tailliet, FIG. 3, word line 64 as the first conductive gate, and gate electrode 62 as the second conductive gate of access transistor 22.)
Regarding Claim 22, Verhaar in view of Tailliet teaches the device according to claim 21, wherein the first gate structure is separated from the drain region of the state transistor along the first direction. (Verhaar, FIG. 18)
Regarding Claim 23, Verhaar in view of Tailliet teaches the device according to claim 16, wherein the control gate and the floating gate overlap the first capacitive implant region (Verhaar, 10) along the first direction.
Regarding Claim 24, Verhaar in view of Tailliet teaches the device according to claim 16, wherein the floating gate includes: a first portion spaced along the first direction from a surface of the semiconductor well by a third distance (i.e., Verhaar portion of 21 over region 10 and layer 17); and a second portion spaced along the first direction from the surface of the semiconductor well by a fourth distance (i.e., Verhaar portion of 21 over channel region and layer 12) the third distance being greater than the fourth distance. (see Verhaar, Fig. 18)
Regarding Claim 25, Verhaar in view of Tailliet teaches the device according to claim 24, wherein both the first portion and the second portion of the floating gate overlap the first capacitive implant region along the first direction. (Verhaar, Fig. 18, a small portion of layer 21 over lapping with region 10 and layers 12 and 17).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Verhaar in view of Tailliet, and further in view of Lee (US 20200013787 A1, previously cited).
Regarding Claim 19, Verhaar in view of Tailliet teaches the device according to claim 16, however, does not teach further comprising a metal contact pillar between the bit-line and a drain region of the access transistor.
On the other hand, Lee teaches a metal contact pillar for transistor connection. (Lee, FIG. 3, ¶[0056], The first bit lines BL1_1 to BL1_3 may be electrically connected to the drain contacts DR through contact plugs (not shown).)
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate a metal contact pillar into the semiconductor device as taught by Lee because Verhaar, Tailliet, and Lee are directed to methods for manufacture of semiconductor devices. Furthermore, the incorporation of a metal contact pillar would yield the predictable benefits of reduced electrical resistance for the device to reduce power requirements and improve reliability of the device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eva Yan Montalvo whose telephone number is (571) 270-3829. The examiner can normally be reached M-TH 9AM-7PM ET.
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/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818
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