DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is Final and is in response to the claims filed 12/08/2025. Claims 1-24 are currently pending, of which claims 1, 5, 7, 12, 14-21, 23, and 24 are currently rejected, and claims 2-4, 6, 8-11, 13, and 22 are currently objected.
Response to Arguments
Applicant’s arguments filed 12/08/2025 have been fully considered.
Specification Objection: Objection to the specification has been withdrawn necessitated by amendment.
Drawing Objection: Objection to the drawings has been withdrawn necessitated by amendments.
35 U.S.C. 102: Applicant’s argument regarding the 35 U.S.C. 102 rejection have been fully considered.
Applicant argues that Seok does not teach amended claim 1. Specifically, Applicant argues “In particular, Seok is directed to a Capacitive-Coupling Computing SRAM method (C3SRAM) for in-memory computing. The C3SRAM system receives ternary inputs of -1, 0, +1 and purposely maintains these values throughout its operation. The system's MWL decoder/driver translates these digital values to corresponding analog voltage levels. For example, +1 input drives MWL to VDR and MWLB to OV; -1 input drives MWL to OV and MWLB to VDR; and 0 input maintains both MWL and MWLB at VRST. In other words, the original sequence structure and values are preserved in Seok's C3SRAM system voltage mapping process.”
Examiner determines arguments are persuasive. Therefore, the rejection has been withdrawn. However, see new grounds of rejection below necessitated by amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 7, 12, 14-21, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Seok et al. (U.S. Patent No.: US 11355167 B2), hereinafter “Seok”, further in view of Lee et al. (U.S. Patent Application Publication No.: US 20190228307 A1), hereinafter “Lee”.
Regarding Claim 1, Seok teaches:
A multiplier-accumulator comprising:
a plurality of exclusive negative OR (XNOR) gates provided along one or more input lines (Column 5 Lines 36-40, e.g., bitcells perform bitwise XNOR computation (XNOR gates); Fig. 1, e.g., shows bitcell array (plurality of XNOR gates) provided input lines MWL[0], MWLB[0]; . . . ; MWL[255], MWLB[255] and BL[0], BLB[0]; . . . ; BL[255], BLB[255]) and configured to receive signals corresponding to an input bit sequence and a weight bit sequence corresponding to each of the one or more input lines (Fig. 1, e.g., Bitcells receive input lines (MWL and MWLB) and weight lines (BL, BLB, and WL). Shift registers 102 show input data as a bit sequence; Column 6 Lines 37-39, e.g., Node Q represents Weight data; Fig. 2A, e.g., shows node Q; Column 7 Lines 35-40, e.g., multi-bit weights (weight bit sequence)) and to output partial product results between the input bit sequence and the weight bit sequence (Column 8 Lines 21-23, e.g., ADCs receive partial sums (partial product results); Figs. 1 and 2A, e.g., MBL receives output from bitcells (XNOR gates));
an encoder configured to apply, to the plurality of XNOR gates, a signal corresponding to a sequence in which a logical value of a most significant bit (MSB) is [converted] from an original sequence expressed in 2's complement of a corresponding sequence for either one or both of the input bit sequence and the weight bit sequence (Fig. 1, e.g., shows MWL Decoder/Driver 104 and R/W Address Decoder 108 (encoder) providing inputs through lines MWL, MWLB, and WL. MWL decoder receives signal containing bit sequences from shift registers, and outputs signals to bitcells (XNOR gates); Column 4 Lines 18-23, e.g., MWL decoder/driver 104 receives two's complement numbers and produces voltage ramping for MSB and for the rest of the bits); and
an outputter configured to generate an output in which a correction value is applied to operation results (Fig. 1, e.g., shows ADCs 112 and shift-and-add components 114 (outputter) receiving outputs from bitcells (XNOR gates) to generate 8-bit outputs; Column 5 Lines 1-6, e.g., Adder adds shifted value (correction value) to the output of the ADC (operation results)) in which the partial product results output from the plurality of XNOR gates are summed (Fig. 1, e.g., Shift-and-add components 114 include adder 132 that adds partial product results coming from bitcells (XNOR gates)).
Seok does not teach:
an encoder configured to apply, to the plurality of XNOR gates, a signal corresponding to a sequence in which a logical value of a most significant bit (MSB) is inverted from an original sequence expressed in 2's complement of a corresponding sequence for either one or both of the input bit sequence and the weight bit sequence;
However, in the field of endeavor, Lee teaches how encoding weights to be represented using an inverted two’s complement fixed point format instead of a general two’s complement fixed point format will result in quick determination of a negative result in the sum-of-products operation without needing to complete it. Lee explains “However, when the weight is encoded in the inverted two's complement fixed-point format, in a case where the final resultant value of the operation is the negative number, a sign of S may change to negative at a certain point during the operation from a MSB to a LSB of the weight. That is, in a case 620, it can quickly be determined where a sign of the final resultant value of the sum-of-products operation is a negative number without needing to complete the sum-of-products operation.”(Lee: ¶0103)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the encoding of weights to be represented in inverted two’s complement fixed point as taught by Lee with the MWL Decoder/Driver as taught by Seok. One would have been motivated to combine these references because both references disclose encoding of two’s complement values for a sum-of-products operation, and Lee enhances the model of Seok by reducing the computational amount by quickly determining if a value will be negative before completing sum-of-products operation. See Lee: ¶0078 and 0103.
Regarding Claim 5, Seok in view of Lee teach:
The multiplier-accumulator of claim 2, wherein the input encoder is configured to sequentially transmit a signal corresponding to a logical value of an input bit sequence having a same number of bits as a number of bits of the original input sequence to the plurality of XNOR gates during a cycle corresponding to the number of bits of the original input sequence (Seok: Fig. 1, e.g., MWL Decoder/Driver outputs signals using MWL and MWLB lines to bitcells (XNOR gates); Column 3 Lines 65-67 - Column 4 Lines 1-3, e.g., MWL decoder/driver 104 (input encoder) outputs signals corresponding to bit value (logical value) of the inputs in shift register 102; Column 3 Lines 35-39, e.g., multiple cycles are needed to compute from MSB to LSB, hence MWL Decoder/Driver sequentially outputs signals corresponding to each bit position (having the same number of bits as a number of bits of the original input sequence)).
Regarding Claim 7, Seok in view of Lee teach:
The multiplier-accumulator of claim 1, wherein the plurality of XNOR gates is provided along an input line of the one or more input lines for the input bit sequence for each bit position allocated to a plurality of output lines grouped for a single operation of multiplication and accumulation (Seok: Fig. 1, e.g., Bitcells (XNOR gates) receive inputs through lines MWL and MWLB (input lines) from MWL Decoder/Driver based on the input bit sequences stored in Shift Registers 102; Column 3 Lines 25-28, e.g., vector-matrix multiplication (multiplication and accumulation) in a single cycle (single operation)), and
the encoder comprises a weight encoder configured to set the weight bit sequence to an XNOR gate provided along the input line for each bit position (Seok: Fig. 1, e.g., R/W Address Decoder 108 (weight encoder) provides Wordline (weight) through WL signal (input line) to bitcells (XNOR gates); Column 7 Lines 35-40, e.g., multi-bit weights (weight bit sequence)).
Regarding Claim 12, Seok in view of Lee teach:
The multiplier-accumulator of claim 1, wherein the outputter is configured to apply a third correction value based on a number of inputs to the operation results (Seok: Fig. 1, e.g., adder 132 accumulates values corresponding to partial product results base on each bit of the input values. Shift Registers 102 contain 4-bit inputs, hence a third shifted value (third correction value) would be needed for the accumulation operation; Column 3 Lines 49-51, e.g., Shift registers 102 hold 4-bit input values), when the encoder comprises an input encoder configured to encode an original input sequence and a weight encoder configured to encode an original weight sequence (Seok: Fig. 1, e.g., MWL Decoder/Driver 104 (input encoder) and R/W Address Decoder 108 (weight encoder) output input signals through lines MWL and MWBL and weight signals through lines WL, respectively).
Regarding Claim 14, Seok in view of Lee teach:
The multiplier-accumulator of claim 1, wherein the multiplier-accumulator is configured to receive P inputs through P input lines (Seok: Fig. 1, e.g., MWL and MWBL lines (P input lines) range from 0-255, hence there are 256 inputs (P inputs); Column 3 Lines 49-51, e.g., Shift register holds 256 inputs (P inputs)) and to set a weight logical value corresponding to each bit position of a weight set for each of the P inputs to a corresponding XNOR gate (Seok: Column 4 Lines 44-48, e.g., Binary weights (weight logical value corresponding to each bit position) are used to convolve the values received on lines MWL and MWBL (P inputs); Fig. 1, e.g., MWL and MWBL Lines are connected to bitcells (XNOR gates)).
Regarding Claim 15, Seok in view of Lee teach:
The multiplier-accumulator of claim 1, wherein for each completion of calculation of an output for a node of a subsequent layer in a layer of a neural network, the multiplier- accumulator is configured to set a weight for an output for another node of the subsequent layer to the plurality of XNOR gates (Seok: Column 5 Lines 14-16, e.g., outputs at the bottom of the shift-and-add components 114 can be outputs of a layer in a neural network, hence each output corresponds to a node. Outputs can be fed back into a new layer; Column 8 Lines 9-13, e.g., weights are set for each layer).
Regarding Claim 16, Seok in view of Lee teach:
The multiplier-accumulator of claim 1, wherein the multiplier-accumulator further includes one or more output lines grouped for each of a plurality of nodes of a subsequent layer connected to a layer of a neural network (Seok: Column 5 Lines 14-16, e.g., outputs at the bottom of the shift-and-add components 114 (output lines) can be outputs of a layer in a neural network, hence each output corresponds to a node. Outputs can be fed back into a new layer; Fig. 1), and is configured to set a weight logical value for an XNOR gate for each of the one or more output lines, and to perform multiplication and accumulation in a plurality of nodes of the subsequent layer in parallel (Seok: Column 8 Lines 9-13, e.g., weights are set for each layer; Column 7 Lines 5-7, e.g., memory array performs MAC operations).
Regarding Claim 17, Seok in view of Lee teach:
The multiplier-accumulator of claim 1, wherein the multiplier-accumulator is configured to perform a summation of a partial product corresponding to a bit position corresponding to a corresponding output line by accumulating an analog signal representing XNOR results output from an XNOR gate connected to a same output line among the plurality of XNOR gates in a single cycle (Seok: Fig. 1, e.g., adder 132 accumulates values corresponding to partial product results base on each bit of the input values. Analog signal corresponding to each MBL line (output line) is converted to digital, then accumulated).
Regarding Claim 18, Seok in view of Lee teach:
The multiplier-accumulator of claim 1, wherein the encoder is configured to apply a signal corresponding to a logical value corresponding to a single cycle among logical values of an input bit sequence input to a corresponding input line of the one or more input lines to an XNOR gate provided along the corresponding input line (Seok: Fig. 1, e.g., MWL Decoder/Driver outputs signals using MWL and MWLB lines to bitcells (XNOR gates); Column 3 Lines 65-67 - Column 4 Lines 1-3, e.g., MWL decoder/driver 104 (encoder) outputs signals corresponding to bit value (logical value) of the inputs in shift register 102; Column 3 Lines 35-39, e.g., multiple cycles are needed to compute from MSB to LSB, hence MWL Decoder/Driver outputs signals corresponding to each bit position).
Regarding Claims 19 and 20, they are a method and media claims practiced by the apparatus of claim 1. It is rejected for the same reasons as claim 1.
With regards to Claimed 21, 23, and 24, they are similar to the claimed multiplier-accumulator above (claims 1 and 5 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Allowable Subject Matter
Claims 2-4, 6, 8-11, 13, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior Art Made of Record
US 12481867 B2 – teaches a CIM array that performs analog MAC operations by converting digital inputs to analog. See Figs. 3A-4B and corresponding descriptions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182