Prosecution Insights
Last updated: October 25, 2026
Application No. 17/736,071

TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§112
Filed
May 03, 2022
Priority
Apr 13, 2022 — CN 202210386850.4
Examiner
GUPTA, RAJ R
Art Unit
2800
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
3 (Non-Final)
69%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
433 granted / 630 resolved
+0.7% vs TC avg
Moderate +13% lift
Without
With
+13.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
35 currently pending
Career history
655
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
54.5%
+14.5% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
17.0%
-23.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 630 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/25/2026 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With regard to claim 6, the claim recites, “having the single thickness,” in the final line of the claim. It is unclear if this merely requires the third gate dielectric to have a single thickness, if it requires the third gate dielectric to have the same thickness as the first gate dielectric layer’s “a single thickness” from line 5 of claim 1, or both a single thickness that is the same as that of the first gate dielectric layer, rendering the claim indefinite. For the purposes of examination with regard to the prior art, this limitation will be read as if requiring the third gate dielectric to have a single thickness that is independent of the single thickness of the first gate dielectric layer in order to comport with the disclosure and claims 7 and 8 depending from claim 6. Claims 7 and 8 depend from claim 6 and inherit its deficiencies. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 3, 4, and 6-10 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ding et al. (US 2015/0187957). With regard to claim 1, Ding teaches, in Figs 7A-7D and 8A-8D, a transistor structure, comprising: a substrate (712); a first gate (734) and a second gate (742) located on the substrate; a first gate dielectric layer (relevant portion of 724) located between the first gate and the substrate and having a single thickness; and a second gate dielectric layer (relevant portion of 724, 726) located between the second gate and the substrate and having a plurality of thicknesses, wherein a maximum thickness of the first gate dielectric layer is the same as a maximum thickness of the second gate dielectric layer ([0036]), the second gate dielectric layer comprises at least one protruding portion (724), and an entire top surface of the protruding portion is covered by the second gate (see Fig 8D). With regard to claim 3, Ding teaches, in Figs 7A-7D and 8A-8D, that the protruding portion has a top surface and a sidewall, and the sidewall is connected to the top surface (see figures). With regard to claim 4, Ding teaches, in Figs 7A-7D and 8A-8D, that the sidewall is not perpendicular to the top surface (see figures). With regard to claim 6, Ding teaches, in Figs 7A-7D and 8A-8D, a third gate (738) located on the substrate; and a third gate dielectric layer (relevant portion of 726) located between the third gate and the substrate and having the single thickness. With regard to claim 7, Ding teaches, in Figs 7A-7D and 8A-8D, that a maximum thickness of the second gate dielectric layer is greater than a maximum thickness of the third gate dielectric layer ([0036], see figures). With regard to claim 8, Ding teaches, in Figs 7A-7D and 8A-8D, that a minimum thickness of the second gate dielectric layer is equal to a maximum thickness of the third gate dielectric layer (thickness of 726). With regard to claim 9, Ding teaches, in Figs 7A-7D and 8A-8D, that the first gate and the second gate are separated from each other (see figures). With regard to claim 10, Ding teaches, in Figs 7A-7D and 8A-8D, that the first gate dielectric layer and the second gate dielectric layer are separated from each other (see figures). Response to Arguments Applicant’s arguments with respect to all claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAJ R GUPTA whose telephone number is (571)270-5707. The examiner can normally be reached 9:30AM-4PM, 8PM-10PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 5712721236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RAJ R GUPTA/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 2 earlier events
May 29, 2025
Response Filed
May 26, 2026
Final Rejection mailed — §102, §112
Jul 17, 2026
Interview Requested
Aug 05, 2026
Applicant Interview (Telephonic)
Aug 05, 2026
Examiner Interview Summary
Aug 25, 2026
Request for Continued Examination
Aug 26, 2026
Response after Non-Final Action
Oct 01, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
69%
Grant Probability
82%
With Interview (+13.4%)
3y 0m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 630 resolved cases by this examiner. Grant probability derived from career allowance rate.

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