DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 8-10 have been withdrawn.
Claim 5 has been canceled.
Claim 1 has been amended; support for the amendment can be found in Fig. 1.
Claims 1-4, 6, 7 have been examined on the merits.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Aziz is now relied on to teach the amended limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Scott (US 20090061302 A1) in view of Aziz (Aziz, MS Abdul, et al. "Influence of pin offset in PCB through-hole during wave soldering process: CFD modeling approach." International Communications in Heat and Mass Transfer 48 (2013): 116-123 ), Saito (JP-H0883966-A, machine translation used for rejection below, previously cited) and Liskow (DE102011086898A1, machine translation used below, previously cited).
Regarding claim 1, Scott discloses a battery module (Fig. 1; element 100), comprising:
a plurality of battery cores (Fig. 1; element 120-124);
a plurality of metal sheets (Fig. 3; element 300, 305), electrically connected ([0026]) to the plurality of battery cores (120-124),
wherein each of the metal sheets (300, 305) comprises a metal bump (Fig. 3; element 315A-315D; 325A-325B), and the metal bump (315, 325) has an upper surface (annotated Fig. 3; US), a first side (annotated Fig. 3; 1S) and a second side (annotated Fig. 3; 2S) opposite to each other (Fig. 3), wherein the upper surface (US) connects the first side (1S) and the second side (2S);
a circuit board (Fig. 4; element 135), disposed on the plurality of metal sheets (300, 305) and having a plurality of openings (Fig. 4; openings of 135 wherein 315 and 325 are inserted; “O”), wherein the plurality of openings (O) respectively expose the metal bump (315, 325) of each of the metal sheets (300, 305).
PNG
media_image1.png
610
906
media_image1.png
Greyscale
Scott fails to disclose wherein the metal bump divides each of the openings into a first cavity and a second cavity; and
a solder, covering the upper surface of the metal bump of each of the metal sheets and each of the openings, wherein the solder fills the first cavity, and the solder completely covers the first side and exposes the second side such that there is an air gap in the second cavity.
Aziz discloses wherein a metal bump (annotated Fig. 10; MB) divides an opening (annotated Fig. 10; O) into a first cavity (annotated Fig. 10; 1C) and a second cavity (annotated Fig. 10; 2C includes a faint red line indicating filling of solder; and AG); and
a solder (annotated Fig. 10; S), covering the opening (O), wherein the solder (S) fills the first cavity (1C), and the solder (S) completely covers (in annotated Fig. 10, solder rises to the height of 1S at L, thus solder covers 1S completely in the X direction) the first side (1S) and exposes (annotated Fig. 10 shows dark blue at AG, indicating 0 volume fraction of the solder) the second side (2S) such that there is an air gap (annotated Fig. 10; AG) in the second cavity (2C).
PNG
media_image2.png
381
357
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Scott by employing the solder and pin configuration taught by Aziz, such that the metal bump divides each of the openings into a first cavity and a second cavity; and a solder, covers each of the openings, wherein the solder fills the first cavity, and the solder completely covers the first side and exposes the second side such that there is an air gap in the second cavity, because offset metal bumps (Saito “lead of the component”; [0012]; Fig. 1; 3) such as that disclosed by Aziz are known in the art to produce a reliable circuit board by reducing the amount of cracks generated in the soldered portion (Saito [0016]) as evidenced by Saito.
Scott in view of Aziz and Saito still fails to disclose covering the upper surface of the metal bump of each of the metal sheets.
Liskow discloses a solder (Fig. 8; element 30), covering an upper surface (Fig. 8; element 44) of a metal bump (Fig. 8; 8) and an opening (Fig. 8; 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified Scott in view of Aziz and Saito by covering the upper surface of the metal bump of each of the metal sheets as taught by Liskow in order to prevent the formation of sharp edges on the soldering side of the circuit board and avoid the risk of the metal bump piercing other components of the circuit board (Liskow ([0041]).
Regarding claim 2, Scott in view of Aziz, Saito and Liskow fail to explicitly disclose wherein the upper surface of the metal bump is lower than a top surface of the circuit board.
Liskow discloses wherein an upper surface (Fig. 8; 44) of a metal bump (Fig. 8; 8) is lower (Fig. 8) than a top surface (Fig. 8; surface at 12) of a circuit board (Fig. 8; 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified Scott in view of Aziz, Saito and Liskow by making the upper surface of the metal bump lower than a top surface of the circuit board as taught by Liskow in order to prevent the formation of sharp edges on the soldering side of the circuit board and avoid the risk of the metal bump piercing other components of the circuit board (Liskow ([0041]).
Regarding claim 3, Scott in view of Aziz, Saito and Liskow fails to disclose wherein the circuit board has a solder bonding area surrounding a periphery of each of the openings, and the solder extends from the upper surface of the metal bump to the solder bonding area to cover each of the openings.
Liskow discloses wherein a circuit board (Fig. 8; 4) has a solder bonding area (Fig. 8; 52) surrounding a periphery (Fig. 8; periphery of 20) of an opening (Fig. 8; 20), and a solder (Fig. 8; 30) extends from an upper surface (Fig. 8; 44) of a metal bump (Fig. 8; 8) to the solder bonding area (52) to cover the opening (20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified Scott in view of Aziz, Saito and Liskow by adding the solder bonding area taught by Liskow such that the circuit board has a solder bonding area surrounding a periphery of each of the openings, and the solder extends from the upper surface of the metal bump to the solder bonding area to cover each of the openings in order to prevent the formation of sharp edges on the soldering side of the circuit board and avoid the risk of the metal bump piercing other components of the circuit board (Liskow ([0041]).
Regarding claim 4, Scott in view of Aziz, Saito and Liskow fails to disclose wherein a surface of the solder is aligned with the top surface of the circuit board.
Liskow discloses wherein a surface (Fig. 8; 54) of a solder (Fig. 8; 30) is aligned (Fig. 8) with a top surface (Fig. 8; surface of 22 directly contacting 54) of a circuit board (Fig. 8; 4 and 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified Scott in view of Aziz, Saito and Liskow by making a surface of the solder aligned with the top surface of the circuit board as taught by Liskow in order to prevent the formation of sharp edges on the soldering side of the circuit board and avoid the risk of the metal bump piercing other components of the circuit board (Liskow ([0041]).
Regarding claim 6, Scott in view of Aziz, Saito and Liskow discloses wherein each of the metal sheets (300, 305) further comprises a connecting portion (annotated Fig. 3; element CP) and a support portion (annotated Fig. 3; element SP), the support portion (SP) vertically connects (Fig. 3) the connecting portion (CP) and the metal bump (315, 325), the connecting portion (CP) of each of the metal sheets (300, 305) is connected to the plurality of battery cores (120-124), and the circuit board (135) is disposed (Fig. 4) on the support portion (SP) of each of the metal sheets (300, 305).
PNG
media_image3.png
573
700
media_image3.png
Greyscale
PNG
media_image4.png
381
357
media_image4.png
Greyscale
Regarding claim 7, Scott in view of Aziz, Saito and Liskow discloses wherein a size (Aziz annotated Fig. 10; size of 1C) of the first cavity (Aziz 1C) is different (Aziz annotated Fig. 10; size of 1C is larger than size of 2C) from a size (Aziz annotated Fig. 10; size of 2C) of the second cavity (Aziz 2C).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE A KENLAW whose telephone number is (571)272-1253. The examiner can normally be reached M-F 9:00 AM-6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tiffany Legette-Thompson can be reached at (571) 270-7078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/G.A.K./Examiner, Art Unit 1723 /TIFFANY LEGETTE/Supervisory Patent Examiner, Art Unit 1723