DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-8, 10-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over JI 20210134597 in view of Chang et al. 20090261424.
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Regarding claim 1, fig. 2I of Ji discloses a semiconductor memory device comprising:
a substrate 11 comprising an NMOS region R1 and a PMOS region R2;
a first gate pattern NG on the NMOS region of the substrate; and
a second gate pattern PG on the PMOS region of the substrate,
wherein the first gate pattern NG comprises a first high-k layer 16N, and a first gate electrode 21N/22N, which are sequentially stacked on the substrate,
the second gate pattern PG comprises a second high-k layer 16P and a second gate electrode 21P/22P which are sequentially stacked on the substrate,
a stacked structure of the first gate electrode, the stacked structure comprising at least two stacked films 21N/22N, wherein the stacked structure above the first high-k layer 16N is same in composition and in film thickness as that of the second gate electrode (see fig. 2H of Ji), and the second gate pattern does not comprise an N-type work function pattern.
Ji does not disclose that the first gate pattern comprises a diffusion mitigation pattern, an N-type work function pattern, the diffusion mitigation pattern is in contact with the first high-k layer and comprises titanium nitride, and wherein the stacked structure is above a conductive pattern.
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However, fig. 7 of Chang semiconductor memory device comprising:
a substrate 100 comprising an NMOS region 101 (par [0087]) and a PMOS region 102;
a first gate pattern 111 on the NMOS region of the substrate; and
a second gate pattern 112 on the PMOS region of the substrate,
wherein the first gate pattern comprises a first high-k layer 105 (par [0083]), a diffusion mitigation pattern 107 (par [0091]), an N-type work function pattern 108 (par [0096] - tuning the first effective work function - DyO layer), and a first gate electrode 109, which are sequentially stacked on the substrate,
the second gate pattern comprises a second high-k layer 105 and a second gate electrode 109 which are sequentially stacked on the substrate,
the diffusion mitigation pattern is in contact with the first high-k layer and comprises titanium nitride (the barrier metal layer 107 comprises TiN),
the first gate electrode 109 above a conductive pattern 106 is same in composition as that of the second gate electrode 109,
the second gate pattern 112 does not comprise the N-type work function pattern 105 (which is DyO layer as per [0096] and bottom of par [0096] AlO layer will thus determine the effective work function, which is suitable for an PMOS transistor).
Note that Chang structure discloses the missing limitations which modify Ji structure would be beneficial.
As such it would have been obvious to form a device of Ji further comprising a diffusion mitigation pattern, an N-type work function pattern, the diffusion mitigation pattern is in contact with the first high-k layer and comprises titanium nitride, and wherein the stacked structure is above a conductive pattern such as a taught by Chang in order to tune the first gate electrode threshold volage.
The resulting structure would have been one meeting the claimed invention.
Regarding claim 2, fig. 7 of Chang disclose wherein the first gate pattern comprises a first conductive pattern (interface pattern between 108 and 109) between the N-type work function pattern and the first gate electrode, and the second gate pattern comprises a second conductive pattern 108 between the second high-k layer and the second gate electrode.
As such it would have been obvious to form a device comprising wherein the first gate pattern comprises a first conductive pattern between the N-type work function pattern and the first gate electrode, and the second gate pattern comprises a second conductive pattern between the second high-k layer and the second gate electrode such as taught by Chang in order to obtain a desired threshold voltage.
Regarding claim 4, fig. 7 of Chang does not discloses wherein a vertical length of the first conductive pattern is less than a vertical length of the second conductive pattern.
However, it would have been obvious to form a device comprising wherein a vertical length of the first conductive pattern is less than a vertical length of the second conductive pattern in order to form an NMOS for one and a PMOS for the other.
Regarding claim 5, fig. 7 of Chang discloses wherein the second conductive pattern is a single layer 108, and the second conductive pattern is shared with at least a part of the first conductive pattern (which 108 and 109 interface and share 108).
The resulting structure would have been one meeting the claimed invention.
Regarding claim 6, fig. 7 of Chang disclose wherein the second gate pattern comprises a P-type work function pattern 106 (par [0096] AlO layer will thus determine the effective work function, which is suitable for an PMOS transistor) between the second high-k layer and the second gate electrode.
It would have been obvious to form a device as claimed in order to form a device having a desire PMOS threshold voltage.
Regarding claim 7, fig. 7 of Chang discloses wherein the first gate pattern comprises the P-type work function pattern (both DYO and ALO share an O which is a pattern).
It would have been obvious to form a device as claimed in order to form a device having a desire in order to use same process for both NMOS and PMOS.
Regarding claim 8, fig. 7 of Chang discloses wherein the first gate pattern comprises a boundary pattern (interface pattern) at a boundary between the N-type work function pattern and the diffusion mitigation pattern.
The resulting structure would have been one meeting the claimed invention.
Regarding claim 10, fig. 7 of Chang discloses wherein the diffusion mitigation pattern is in contact with the N-type work function pattern, and is a single layer.
The resulting structure would have been one meeting the claimed invention.
Regarding claim 11, fig. 7 of Chang discloses wherein the N- type work function pattern comprises at least one of lanthanum (La), lanthanum oxide (LaO).
The resulting structure would have been one meeting the claimed invention.
Regarding claim 13, Ji discloses further comprising, in the PMOS region, a channel layer between the substrate and the second high-k layer and comprising silicon germanium (par [0049]).
Allowable Subject Matter
Claims 21-27 are allowed.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893