DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 01/12/2026. Claims 1-20 are currently pending, of which claims 1-20 are currently rejected.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/13/2026 has been entered.
Response to Arguments
Applicant’s arguments filed 04/13/2026 have been fully considered.
35 U.S.C. 112(f): Applicant’s arguments regarding the claim interpretation under 35 U.S.C. 112(f) have been fully considered, but they are not persuasive.
Applicant argues in pages 9-10 that the claim limitations “Multiplication unit”, “Addition unit”, and “Electrical signal adjustment subunit” should not invoke 35 U.S.C. 112(f). Applicant specifically argues “Regarding "addition unit," "multiplication unit," and "electrical signal regulation subunit", Applicant respectfully traverses the Office's finding that these claim limitations invoke 35 U.S.C. § 112(f). Applicant submits that these terms are well-recognized structural terms of art in the analog/digital computing and circuit arts, not mere functional language.” Applicant then explains the specific structure disclosed in the specification and drawings for each of the units.
Examiner respectfully disagrees. Applicant’s argument regarding the claim interpretation under 35 U.S.C. 112(f) does not comply 37 CFR 1.111(b) as it does not indicate errors in the 112(f) invocation analysis. As indicated in the non-final rejection filed on 10/10/2025, the limitations indicated invoking 112(f) meet the 3-prong analysis for the invocation of 112(f). See MPEP 2181 and claim interpretation section below. As also stated in the non-final rejection, if applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Applicant relies on the drawings and specification to point to specific structure of these units, but Applicant also argues these units are well-recognized structural elements. It is not apparent what point the applicant is making. Whether these units are known units commonly known in the art, or units reciting specific structure. Still, Applicant does not address how the claim language fail to meet the 3-prong analysis for the invocation of 112(f).
35 U.S.C. 102: Applicant’s arguments regarding the 35 U.S.C. 102 rejection have been fully considered, but they are not persuasive.
Applicant argues in pages 10-14 that Rasch does not teach amended claim 1. Specifically, Applicant argues “Therefore, the technical concepts between claim 1 and Rasch are completely different, and Rasch fails to disclose or suggest at least wherein row matrix elements of a same row of the first matrix are to be processed by the same one multiplication unit, since electrical signals representing the row matrix elements sequentially inputted in the plurality of predetermined timing sequences to the same one multiplication unit" and "wherein a number of the row matrix elements of the same row is greater than or equal to two," as recited in claim 1. Applicant submits that while Rasch discloses a "parallel computing resistor cross array" technology, the present application focuses on a row-column computing architecture that time- multiplexes a single multiplication unit. The two are substantially different in terms of computing principles, hardware configuration, and workflow.”
Examiner respectfully disagrees. As indicated in the 35 U.S.C. 102 rejection in the non-final rejection filed on 10/10/2025, Rasch teaches performing vector-matrix multiplication (first and second matrix), where each value of the input vector is represented by a pulse duration of voltage pulse (electrical signal). Forward cycle of inputting vectors to each RPU cell is repeated, hence values are sequentially inputted, and where the control signal circuitry controls the clocking signal (predetermined timing sequence) for controlling the input of vector data. Further, there are not limitations in amended claim 1 that prevent the row-column multiplication unit to only include one multiplication unit. Examiner points to one of the variable resistors of the computing system to be one multiplication unit. See 35 U.S.C. 102 rejection below.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“Multiplication unit”, and “Addition unit”
First recited in Claim 1.
“Electrical signal adjustment subunit”
First recited in Claim 7.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
The corresponding structure as described in the specification is identified as follows:
The “Multiplication unit” is included in the row-column calculation unit as in Figs. 1-3 and is coupled to the “Addition unit” as further disclosed in ¶0006, interpreted to include either a first load (variable resistor), as disclosed in Fig. 4, ¶0034-0041 and ¶0084-0086, or an electrical signal adjustment subunit coupled to a second load (constant load resistor), as disclosed in Fig. 5, ¶0042.
The “Addition unit” is included in the row-column calculation unit as in Figs. 1-3 and is coupled to the “Multiplication unit” as further disclosed in ¶0006, and is interpreted to include a capacitor as disclosed in ¶0036, ¶0043, and ¶0089.
The “Electrical signal adjustment subunit” is included in the Multiplication unit as disclosed in Fig. 5 and is coupled to the second load (constant load resistor) as further disclosed in ¶0042 and ¶0047, interpreted to include a voltage signal duty cycle adjustment unit, where the voltage signal duty cycle adjustment unit may include a switching circuit for controlling voltage signal input to the second load and a pulse width modulation (PWM) circuit for controlling the switching circuitry as disclosed in ¶0044 and ¶0045.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rasch et al. (U.S. Patent Application No.: US 12112264 B2), hereinafter “Rasch”.
Regarding Claim 1, Rasch teaches:
A circuit module for performing matrix multiplication, comprising a row-column calculation unit for performing a row-column multiplication calculation, wherein the row-column calculation unit comprises one multiplication unit and an addition unit (Fig. 3A, e.g., shows computing system 300 (circuit module) comprising variable resistor array 305 (where one of the variable resistors is a multiplication unit) and current integrator 332 (addition unit), where multiplication unit and addition unit form a row-column multiplication calculation unit; Column 10 Lines 33-41, e.g., each variable resistor (multiplication unit) receives row and column elements for multiplication operation), and an output end of the multiplication unit is connected to an input end of the addition unit (Fig. 3A, e.g., shows current line I1 receiving output from variable resistor in RPU cell (multiplication unit) then inputted to current integrator 332-1 (addition unit));
the multiplication unit is configured to perform a multiplication calculation based on a row matrix element of a first matrix and a column matrix element of a second matrix (Column 11 Lines 46-53, e.g., computing system in fig. 3A performs vector-matrix multiplication (multiplication of first matrix and second matrix) of a voltage vector and conductance matrix G (second matrix); Column 3 Lines 54-57, e.g., array receives input vector (first matrix) transmitted as voltage pulses through each row (row matrix elements), and stored conductance in the 2D array form a matrix (second matrix); Fig. 3A, e.g., shows input vector inputs x1-xm (row matrix elements) and variable resistors with stored conductance G (column matrix element)), and receive at least one electrical signal sequentially inputted in a plurality of predetermined timing sequences via an input end of the multiplication unit, wherein the electrical signal represents the row matrix element of the first matrix (Column 5 Lines 57-61, e.g., Each value of the input vector is represented by a pulse duration of voltage pulse (electrical signal); Column 3 Lines 47-50, e.g., forward cycle is repeated, hence values are inputted sequentially; Column 4 Lines 61-67, e.g., Control signal circuitry 140 can controls clocking signal (predetermined timing sequence) for operation of peripheral circuitry 120 and 130, which provide inputs to RPU Cell (multiplication unit); Fig. 1); and
the addition unit is configured to accumulate a product, obtained by the multiplication unit based on the inputted electrical signal, to perform the row-column multiplication calculation (Column 5 Line 65 - Column 6 Line 1, e.g., current integrator (addition unit) accumulates outputs (electrical signals) of RPU cells (products)),
wherein row matrix elements of a same row of the first matrix are to be processed by the same one multiplication unit, since electrical signals representing the row matrix elements sequentially inputted in the plurality of predetermined timing sequences to the same one multiplication unit (Column 3 Lines 47-50, e.g., forward cycle is repeated, hence values are inputted sequentially to each RPU cell (multiplication unit); Column 4 Lines 61-67, e.g., Control signal circuitry 140 can controls clocking signal (predetermined timing sequence) for operation of peripheral circuitry 120 and 130, which provide inputs to RPU Cell (multiplication unit); Fig. 3A), and wherein a number of the row matrix elements of the same row is greater than or equal to two (Column 3 Lines 47-50, e.g., forward cycle is repeated, hence values are inputted sequentially, hence at least two electrical signals (row matrix elements) are inputted)).
Regarding Claim 2, Rasch teaches:
The circuit module according to claim 1, wherein the circuit module comprises one row-column calculation unit, and the row-column calculation unit is configured to perform a row-column multiplication calculation corresponding to a row of the first matrix (Fig. 3A, e.g., Variable resistor in RPU cell 310 performs multiplication of row and column elements, each voltage inputted corresponds to a row (row of a first matrix)).
Regarding Claim 3, Rasch teaches:
The circuit module according to claim 1, wherein the number of the row-column calculation units comprised in the circuit module is equal to the number of a row of the first matrix (Fig. 3A, e.g., inputs have m rows (first matrix). Readout circuitry comprises of n current integrators (addition units) to receive signals from RPU cells (multiplication units); Fig. 3B, e.g., Readout circuitry is now configured for backward pass and consists of m current integrators (addition units), which is the same as the rows of the first matrix),
and a row-column calculation unit corresponding to the row of the first matrix performs a row-column multiplication calculation corresponding to the row (Fig. 3A, e.g., RPU cell (multiplication unit) outputs result of row-column multiplication to current integrator (addition unit) (RPU cell and current integrator form a row-column calculation unit)).
Regarding Claim 4, Rasch teaches:
The circuit module according to claim 1, wherein the multiplication unit comprises a first load for implementing the column matrix element (Fig. 3A, e.g., each RPU cell (multiplication unit) contains a variable resistor (first load); Column 1 Lines 23-27, e.g., weights (column matrix element) are represented by conductance of RPU cell (multiplication unit)).
Regarding Claim 5, Rasch teaches:
The circuit module according to claim 4, wherein the first load comprises a resistor and the addition unit comprises a capacitor (Fig. 3A, e.g., RPU cell (multiplication unit) contains a variable resistor; Fig. 6, e.g., shows current integrator circuit 640 (addition unit) comprising one capacitor).
Regarding Claim 6, Rasch teaches:
The circuit module according to claim 4, wherein the first load is configured to have an adjustable load value (Column 10 Lines 33-39, e.g., Conductance (load) in variable resistors is tunable (adjustable)).
Regarding Claim 7, Rasch teaches:
The circuit module according to claim 1, wherein the multiplication unit comprises an electrical signal adjustment subunit and a second load, the electrical signal adjustment subunit is configured to adjust the electrical signal, and the second load is configured to have a constant load value (Fig. 3A, e.g., RPU cell (multiplication unit)).
Regarding Claim 8, Rasch teaches:
The circuit module according to claim 7, wherein the electrical signal comprises a voltage signal, and the electrical signal adjustment subunit comprises a voltage signal duty cycle adjustment unit (Figs. 1, and 3A).
Regarding Claim 9, Rasch teaches:
The circuit module according to claim 1, wherein the circuit module is configured to perform a convolution calculation based on a feature matrix outputted by a neuron of a neural network and a weight matrix (Column 5 Lines 6-13).
Regarding Claim 10, Rasch teaches:
A method for performing matrix multiplication, applied to the circuit module for performing matrix multiplication according to claim 1, wherein the method comprises performing a row-column multiplication calculation by the row-column calculation unit, and the row-column calculation unit comprises the multiplication unit and the addition unit (Fig. 3A, e.g., shows computing system 300 (circuit module) comprising variable resistor array 305 (where one of the variable resistors is a multiplication unit) and current integrator 332 (addition unit), where multiplication unit and addition unit form a row-column multiplication calculation unit; Column 10 Lines 33-41, e.g., each variable resistor (multiplication unit) receives row and column elements for multiplication operation), wherein the performing a row-column multiplication calculation comprises:
obtaining row matrix elements of a target row of the first matrix and column matrix elements of a target column of the second matrix, wherein the row matrix elements are represented by electrical signals (Fig. 3A, e.g., shows RPU cells receiving row matrix elements of a target row of a first matrix (shown at the bottom of Fig. 3A.), and column elements from a second matrix);
sequentially inputting the electrical signals representing the row matrix elements of the target row to the same one multiplication unit comprised in the row-column calculation unit (Column 3 Lines 47-50, e.g., forward cycle is repeated, hence values are inputted sequentially (same one variable resistor)),
obtaining, by the multiplication unit, products of the row matrix elements and column matrix elements in the target column corresponding to the row matrix elements, and inputting, by the multiplication unit, the products to the addition unit (Fig. 3A, e.g., RPU cell 310 (multiplication unit) multiply row and column values to be inputted to current integrator (addition unit)), wherein the row matrix elements of the target row of the first matrix are to be processed by the same one multiplication unit (Column 3 Lines 47-50, e.g., forward cycle is repeated, hence values are inputted sequentially to each RPU cell (multiplication unit); Column 4 Lines 61-67, e.g., Control signal circuitry 140 can controls clocking signal (predetermined timing sequence) for operation of peripheral circuitry 120 and 130, which provide inputs to RPU Cell (multiplication unit); Fig. 3A), and wherein a number of the row matrix elements of the target row is greater than or equal to two (Column 3 Lines 47-50, e.g., forward cycle is repeated, hence values are inputted sequentially, hence at least two electrical signals (row matrix elements) are inputted)); and
accumulating, by the addition unit, the products corresponding to the matrix elements of the target row, and determining a result of the row-column multiplication calculation performed on the target row and the target column based on an accumulation result (Column 5 Line 65 - Column 6 Line 1, e.g., current integrator (addition unit) accumulates outputs (electrical signals) of RPU cells (products)).
Regarding Claim 11, Rasch teaches:
The method according to claim 10, wherein the circuit module for performing matrix multiplication comprises one row-column calculation unit (Fig. 3A, e.g., shows RPU cells and current integrator (row-column calculation unit)), and the method further comprises:
determining row timing sequences respectively corresponding to rows of the first matrix (Column 5 Lines 57-61);
for each of the row timing sequences, determining column timing sequences respectively corresponding to columns of the second matrix (Fig. 3A, e.g. inputs in rows are multiplied by weights stored in RPU Cells (multiplication units))
in each of the column timing sequences in each of the row timing sequence, performing, by the row-column calculation unit, the row-column multiplication calculation (Fig. 3A, e.g. inputs in rows are multiplied by weights stored in RPU Cells (multiplication units)), and
determining, by the row-column calculation unit, a result of the row-column multiplication calculation based on an output of the addition unit (Fig. 3A, e.g., current integrator 332 (addition unit) outputs results); wherein
in the row-column multiplication calculation, the target row corresponds to a row timing sequence, and the target column corresponds to a column timing sequence in the row timing sequence (Fig. 3A, e.g., RPU cells receive input vectors and weight data; Column 4 Lines 61-67, e.g., Control signal circuitry 140 can controls clocking signal (timing sequence) for operation of peripheral circuitry 120 and 130, which provide inputs to RPU Cell (multiplication unit)).
Regarding Claim 12, Rasch teaches:
The method according to claim 10, wherein the number of the row-column calculation unit comprised in the circuit module for performing matrix multiplication is equal to the number of rows of the first matrix (Fig. 3A, e.g., inputs have m rows (first matrix). Readout circuitry comprises of n current integrators (addition units) to receive signals from RPU cells (multiplication units); Fig. 3B, e.g., Readout circuitry is now configured for backward pass and consists of m current integrators (addition units), which is the same as the rows of the first matrix), and the method further comprises:
determining column timing sequences respectively corresponding to columns of the second matrix (Fig. 3A, e.g., RPU cells receive input vectors and weight data; Column 4 Lines 61-67, e.g., Control signal circuitry 140 can controls clocking signal (timing sequence) for operation of peripheral circuitry 120 and 130, which provide inputs to RPU Cell (multiplication unit));
in each of the column timing sequences, performing, by a row-column calculation unit corresponding to each of rows of elements, the row-column multiplication calculation, wherein in the row-column multiplication calculation, the target column comprises column elements of the second matrix corresponding to the column timing sequence (Column 3 Lines 54-57, e.g., array receives input vector (first matrix) transmitted as voltage pulses through each row (row matrix elements), and stored conductance in the 2D array form a matrix (second matrix)); and
sequentially obtaining, from addition units of the row-column calculation units, results of row-column multiplication calculations respectively corresponding to the rows of the first matrix (Fig. 3A, e.g., current integrator 332 (addition unit) outputs results of row-column multiplication calculations).
Regarding Claim 13, Rasch teaches:
The method according to claim 11, wherein the multiplication unit comprises a first load for implementing the column matrix elements, and the first load has an adjustable load value (Fig. 3A, e.g., each RPU cell (multiplication unit) contains a variable resistor (first load); Column 10 Lines 33-39, e.g., Conductance (load) in variable resistors is tunable (adjustable)); and
the sequentially inputting the electrical signals respectively representing the row matrix elements of the target row to the multiplication unit comprised in the row-column calculation unit (Fig. 3A, e.g., shows RPU cells receiving row matrix elements of a target row of a first matrix (shown at the bottom of Fig. 3A.), and column elements from a second matrix),
obtaining, by the multiplication unit, products of the row matrix elements and column matrix elements in the target column corresponding to the row matrix elements, and inputting, by the multiplication unit (Fig. 3A, e.g., RPU cell (multiplication unit) multiply row and column values to be inputted to current integrator (addition unit)), the products to the addition unit comprises:
determining row matrix element timing sequences respectively corresponding to the row matrix elements (Column 5 Lines 57-61);
for each of the row matrix element timing sequences, adjusting the load value of the first load based on column matrix elements corresponding to the row matrix element timing sequence (Fig. 3A, e.g., RPU cells receive input vectors and weight data; Column 4 Lines 61-67, e.g., Control signal circuitry 140 can controls clocking signal (timing sequence) for operation of peripheral circuitry 120 and 130, which provide inputs to RPU Cell (multiplication unit));
and determining a first response signal, obtained by applying electrical signals representing row matrix elements corresponding to the row matrix element timing sequence on the first load after adjusting the load value, as the products (Fig. 3A, e.g., RPU cells output products (first response signal) of row and column elements).
With regards to Claim 14, this is similar to the claimed method above (claim 13 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Regarding Claim 15, Rasch teaches:
The method according to claim 13, wherein the first load comprises a variable resistor, the addition unit comprises a capacitor, and
the first response signal is a current signal (Fig. 3A, e.g., RPU cell (multiplication unit) contains a variable resistor and outputs current signal (first response signal); Fig. 6, e.g., shows current integrator circuit 640 (addition unit) comprising one capacitor);
and the accumulating, by the addition unit, the products corresponding to the matrix elements of the target row, and determining, based on an accumulation result (Column 5 Lines 65-67 and Column 6 Lines 1-3), a result of the row-column multiplication calculation performed on the target row and the target column comprises:
accumulating, by the capacitor, the current signals representing the products corresponding to the matrix elements of each of the rows to obtain accumulated charges (Fig. 6, e.g., capacitor accumulates charges for accumulation operation), and determining the result of the row-column multiplication calculation based on the accumulated charges (Fig. 6, e.g., capacitor accumulates charges for accumulation operation).
With regards to Claim 16, this is similar to the claimed method above (claim 15 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Regarding Claim 17, Rasch teaches:
The method according to claim 11, wherein the multiplication unit comprises an electrical signal adjustment subunit and a second load, the electrical signal adjustment subunit is configured to adjust the electrical signals, and the second load has a constant load value (Fig. 3A, e.g., RPU cell (multiplication unit)); and
the sequentially inputting the electrical signals respectively representing the row matrix elements of the target row to the multiplication unit comprised in the row-column calculation unit, obtaining, by the multiplication unit, products of the row matrix elements and column matrix elements in the target column corresponding to the row matrix elements, and inputting, by the multiplication unit (Fig. 3A, e.g., shows RPU cells receiving row matrix elements of a target row of a first matrix (shown at the bottom of Fig. 3A.), and column elements from a second matrix), the products to the addition unit comprises:
determining row matrix element timing sequences respectively corresponding to the row matrix elements (Column 5 Lines 57-61);
for each of the row matrix element timing sequences, determining a control signal for controlling the electrical signal adjustment subunit based on column matrix elements corresponding to the row matrix element timing sequence (Fig. 3A, e.g., RPU cells receive input vectors and weight data; Column 4 Lines 61-67, e.g., Control signal circuitry 140 can controls clocking signal (timing sequence) for operation of peripheral circuitry 120 and 130, which provide inputs to RPU Cell (multiplication unit)); and
inputting the electrical signals to the multiplication unit, wherein in the multiplication unit, the electrical signal adjustment subunit adjusts the electrical signals based on the control signal and applies the adjusted electrical signals to the second load to obtain a second response signal representing the products (Fig. 3A, e.g., RPU cell (multiplication unit) receives electrical signals and outputs product (second response signal)).
With regards to Claim 18, this is similar to the claimed method above (claim 17 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Regarding Claim 19, Rasch teaches:
The method according to claim 10, wherein the first matrix is a feature matrix outputted by a neurons of a neural network, and the second matrix is a weight matrix (Column 5 Lines 6-13).
Regarding Claim 20, Rasch teaches:
An integrated circuit, comprising at least one circuit module for performing matrix multiplication according to claim 1 (Fig. 3A).
Prior art made of record
US 12547373 B2 – teaches a variable resistor array that perform multiply and accumulate calculations. See Fig. 1 and corresponding description. The variable resistor array contains individual variable resistors, which are pertinent to the multiplication unit 11 shown in Fig. 4 and disclosed in paragraphs 0024-0026, 0029, 0034, and 0084.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182
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