Detailed Action
The instant application having Application No. 17/737,406 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 7/31/25. Claims 1-20 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-11 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Moshayedi in view of Sawheny et al. (U.S. Patent Application Publication No. 2018/0121129), herein referred to as Sawheny et al., and in view of Lee (U.S. Patent Application Publication No. 2019/0121741), herein referred to as Lee and Joo et al. (U.S. Patent Application Publication No. 2013/0117634), herein referred to as Joo et al.
Referring to claim 1, Moshayedi disclose as claimed, a storage device comprising: a plurality of nonvolatile NAND flash memory devices configured to store data and including a plurality of memory blocks (see para. 25-26, where a flash array that stores data may include multiple flash chips that may include both SLC and MLC flash, both which would include memory blocks); and a controller configured to control the plurality of nonvolatile memory devices, wherein the plurality of memory blocks are divided into a plurality of banks that include a first bank and a second bank (see para. 25-27, where the flash array is controlled by a controller and where the data is divided into a plurality of logical data blocks, which would be the plurality of banks. See para. 49, where a first bank would be an SLC block where data is being moved from, and a second bank would be the MLC block where data is being copied to), the controller is configured to receive a read request from an external device (see para. 25 and 46-47 where the controller receives read/write requests from the host).
Moshayedi discloses the claimed invention except for the controller being configured to receive the read request while migrating first data from the first bank to the second bank, and configured to execute a read command on the first bank and execute a program command or an erase command on the second bank while migrating the first data from the first bank to the second bank, when the controller applies the read command to the first bank at a first time period, applies the erase command to the second bank at a second time period and receives the read request at the second time period, the first bank accepts the read request to provide a corresponding data to the controller, and when the controller applies the read command to the first bank at a third time period, applies the program command to the second bank at a fourth time period and receives the read request at the third time period, the second bank accepts the read request to provide the corresponding data to the controller; and where an erase command is applied to reset memory cell voltages and a program command is applied to set memory cell voltages; and where the read command is executed by applying a read voltage to a selected word-line and applying a read-pass voltage to unselected word-lines and a program command is executed by applying a program voltage to the selected word-line and a program pass voltage to the unselected word-lines and an erase command is executed by applying an erase voltage to a well of the plurality of memory blocks and applying a ground voltage to entire word-lines of the plurality of memory block; and each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop.
However, Sawhney et al. disclose for the controller being configured to receive the read request while migrating the first data from the first bank to the second bank (see para. 103, where during a migration, read operations may be received and directed toward both the source and destination components) and configured to execute a read command on the first bank and execute a program command or an erase command on the second bank while migrating the first data from the first bank to the second bank (see para. 88, where a migration is from a source storage component or bank to a destination storage component or bank. Therefore a read command would be executed on the source bank to read the data that is being transferred to the destination storage where the same data would then be programmed or loaded), when the controller applies the read command to the first bank at a first time period, applies the erase command to the second bank at a second time period and receives the read request at the second time period, the first bank accepts the read request to provide a corresponding data to the controller, and when the controller applies the read command to the first bank at a third time period, applies the program command to the second bank at a fourth time period and receives the read request at the third time period, the second bank accepts the read request to provide the corresponding data to the controller (see para. 103 and 111, where during a migration operation, read requests may be directed toward both the source and destination storage component, which would be the first and second banks. Para. 98 states that the object pointers would point to the source storage component before migration, both components during migration and the destination component after migration. The object data retrieved first may then be returned to the requesting client. Therefore, in the first scenario the first bank or source would accept the read request as the destination is still being erased and getting ready to have the data migrated. In the second scenario, the second bank or destination would accept the read request as the data has recently been programmed in the second bank or destination).
Moshayedi and Sawhney et al. are analogous art because they are from the same field of endeavor of migrating data in storage systems (see Moshayedi, abstract and para. 49, and Sawhney et al., abstract, regarding migrating data in storage systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise the controller being configured to receive the read request while migrating the first data from the first bank to the second bank, and configured to execute a read command on the first bank and execute a program command or an erase command on the second bank while migrating the first data from the first bank to the second bank, when the controller applies the read command to the first bank at a first time period, applies the erase command to the second bank at a second time period and receives the read request at the second time period, the first bank accepts the read request to provide a corresponding data to the controller, and when the controller applies the read command to the first bank at a third time period, applies the program command to the second bank at a fourth time period and receives the read request at the third time period, the second bank accepts the read request to provide the corresponding data to the controller, as taught by Sawhney et al., in order to allow for uninterrupted access to data that is being migrated (see Sawhney et al., para. 25-27, regarding reasons for allowing for read access during migrations, including being able to access data that is being migrated during a migration).
Moshayedi and Sawney et al. disclose the claimed invention except for and where an erase command is applied to reset memory cell voltages and a program command is applied to set memory cell voltages; and where the read command is executed by applying a read voltage to a selected word-line and applying a read-pass voltage to unselected word-lines and a program command is executed by applying a program voltage to the selected word-line and a program pass voltage to the unselected word-lines and an erase command is executed by applying an erase voltage to a well of the plurality of memory blocks and applying a ground voltage to entire word-lines of the plurality of memory blocks; and each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop.
However, Lee disclose where an erase command is applied to reset memory cell voltages and a program command is applied to set memory cell voltages (see para. 107-109, where a program voltage is applied for a program operation and a ground voltage is applied during an erase operation). and where the read command is executed by applying a read voltage to a selected word-line and applying a read-pass voltage to unselected word-lines and a program command is executed by applying a program voltage to the selected word-line and a program pass voltage to the unselected word-lines and an erase command is executed by applying an erase voltage to a well of the plurality of memory blocks and applying a ground voltage to entire word-lines of the plurality of memory blocks (see para. 107-113, explaining different voltages applied for program, erase and read operations).
Moshayedi and Lee are analogous art because they are from the same field of endeavor of non-volatile memory devices (see Moshayedi, abstract and Lee, para. 5, regarding non-volatile memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise where an erase command is applied to reset memory cell voltages and a program command is applied to set memory cell voltages; and where the read command is executed by applying a read voltage to a selected word-line and applying a read-pass voltage to unselected word-lines and a program command is executed by applying a program voltage to the selected word-line and a program pass voltage to the unselected word-lines and an erase command is executed by applying an erase voltage to a well of the plurality of memory blocks and applying a ground voltage to entire word-lines of the plurality of memory blocks, as taught by Lee, in order to properly execute operations on the memory device (See Lee, para. 45, where a change in voltage is used to determine data stored in a memory cell). It is well known in the art to utilize different voltages when performing different operations on a memory device, such as taught by Lee.
Moshayedi, Sawhney et al. and Lee disclose the claimed invention except for each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop.
However, Joo et al. disclose each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop (see para. 81, where an SLC memory has a program loop number and an erase loop number and therefore uses program loops and erase loops for programming and erasing. This is well known in the art for SLC and MLC memories to use program and erase loops).
Moshayedi and Joo et al. are analogous art because they are from the same field of endeavor of non-volatile memory devices (see Moshayedi, abstract and Joo et al., abstract, regarding non-volatile memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop, as taught by Joo et al., in order to make sure the data has been properly programmed/erased. Utilizing program and erase loops for NAND flash memory is well known in the art and would be obvious to include in Moshayedi.
As to claim 2, Moshayedi, Sawhney et al., Lee and Joo et al. also disclose the storage device of claim 1, wherein the plurality of banks are assigned into a plurality of sets and one free bank, and each of the plurality of sets includes at least one bank (see Moshayedi, para. 37, where logical data blocks are associated with physical data blocks and a logical to physical block table is used. See para. 52, where there are sets of lists with different erase count ranges. Each list of blocks with a different erase count range would be a set. Each set therefore includes at least one bank or data block. Moshayedi, para. 49 also discloses where there is at least one free bank or blocks to move and copy data).
As to claim 4, Moshayedi, Sawhney et al., Lee and Joo et al. also disclose the storage device of claim 2, wherein a program operation and/or an erase operation are performed only in the free bank among the plurality of banks (see Moshayedi, para. 26, where each channel may accommodate send, write, or erase commands to a specific flash memory. As the different blocks and memories are on different channels, only one command at a specific time would be used for a block/channel at a time. Therefore when the free bank is getting programmed, only that bank would be programmed).
As to claim 7, Moshayedi, Sawhney et al., Lee and Joo et al. also disclose the storage device of claim 1, wherein the controller controls a data migration operation from the first bank to the second bank such that an I/0 request is independent of the data migration operation (see Moshayedi, para. 25-27, where the flash array is controlled by a controller, and see Sawhney et al., para. 27 and 100-103, where there is uninterrupted access to data during migration and read operations may be directed toward either the source or destination storage device or both during migration. Therefore the I/O request would be independent of the data migration operation).
Referring to claim 8, Moshayedi disclose as claimed, a storage device comprising: a plurality of NAND flash nonvolatile memory devices configured to store data and including a plurality of memory blocks (see para. 25-26, where a flash array that stores data may include multiple flash chips that may include both SLC and MLC flash, both which would include memory blocks); and a controller configured to control the plurality of nonvolatile memory devices, wherein the plurality of memory blocks are divided into a plurality of banks that include a first bank and a second bank (see para. 25-27, where the flash array is controlled by a controller and where the data is divided into a plurality of logical data blocks, which would be the plurality of banks. See para. 49, where a first bank would be an SLC block where data is being moved from, and a second bank would be the MLC block where data is being copied to), the plurality of banks are assigned into a plurality of sets and one free bank, each of the plurality of sets includes at least one bank (see para. 40-41, where the SLC and MLC flash chips are made up of data blocks, including free blocks. Logical data blocks would be assigned or associated with physical data blocks as indicated in para. 37, where a logical to physical block table is used. See para. 52, where sets of lists include blocks with different erase count ranges. Each list of blocks comprising an erase count range would be a set), the controller is configured to transfer first data from the first bank to the second bank and to perform an erase operation on the second bank (see para. 49, where data is migrated from an SLC block to an MLC block. An erase operation is performed on the MLC block or second bank), and the erase operation is performed only in the free bank among the plurality of banks (see para. 26, where each channel may accommodate send, write, or erase commands to a specific flash memory. As the different blocks and memories are on different channels, only one command at a specific time would be used for a block/channel at a time. Therefore when the free bank/block is getting programmed, only that bank/block would be programmed).
Moshayedi discloses the claimed invention except for programming cells in the second bank using a program voltage applied to a first word-line of the second bank, a program pass voltage applied to unselected word-lines, the transferring the first data from the first bank to the second bank while receiving a read request and applying an erase voltage to a well of the first bank and applying a ground voltage to entire word-lines in the plurality of memory blocks, the performing the erase operations while processing the read request; each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop.
However, Sawhney et al. disclose the transferring the first data from the first bank to the second bank while receiving a read request and the performing the erase operations while processing the read request (see para. 103, where during a migration, read operations may be received and directed toward both the source and destination components. See. 88, where a migration is from a source storage component or bank to a destination storage component or bank. Therefore a read command would be executed on the source bank to read the data that is being transferred to the destination storage where the same data would then be programmed or loaded. And see para. 103 and 111, where during a migration operation, read requests may be directed toward both the source and destination storage component, which would be the first and second banks. Para. 98 states that the object pointers would point to the source storage component before migration, both components during migration and the destination component after migration. The object data retrieved first may then be returned to the requesting client. Therefore, in the first scenario the first bank or source would accept the read request as the destination is still being erased and getting ready to have the data migrated. In the second scenario, the second bank or destination would accept the read request as the data has recently been programmed in the second bank or destination).
Moshayedi and Sawhney et al. are analogous art because they are from the same field of endeavor of migrating data in storage systems (see Moshayedi, abstract and para. 49, and Sawhney et al., abstract, regarding migrating data in storage systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise the transferring the first data from the first bank to the second bank while receiving a read request and the performing the erase operations while processing the read request, as taught by Sawhney et al., in order to allow for uninterrupted access to data that is being migrated (see Sawhney et al., para. 25-27, regarding reasons for allowing for read access during migrations, including being able to access data that is being migrated during a migration).
Moshayedi and Sawney et al. disclose the claimed invention except for programming cells in the second bank using a program voltage applied to a first word-line of the second bank, a program pass voltage applied to unselected word-lines, and applying an erase voltage to a well of the first bank and applying a ground voltage to entire word-lines in the plurality of memory blocks; each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop.
However, Lee disclose programming cells in the second bank using a program voltage applied to a first word-line of the second bank, a program pass voltage applied to unselected word-lines, and applying an erase voltage to a well of the first bank and applying a ground voltage to entire word-lines in the plurality of memory blocks (see para. 107-113, where a program voltage is applied to selected word lines and a program pass voltage to unselected word lines during a program operation, and a ground voltage is applied to word lines during an erase operation, while the voltage generator generates a plurality of erase voltages).
Moshayedi and Lee are analogous art because they are from the same field of endeavor of non-volatile memory devices (see Moshayedi, abstract and Lee, para. 5, regarding non-volatile memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise programming cells in the second bank using a program voltage applied to a first word-line of the second bank, a program pass voltage applied to unselected word-lines, and applying an erase voltage to a well of the first bank and applying a ground voltage to entire word-lines in the plurality of memory blocks, as taught by Lee, in order to properly execute operations on the memory device (See Lee, para. 45, where a change in voltage is used to determine data stored in a memory cell). It is well known in the art to utilize different voltages when performing different operations on a memory device, such as taught by Lee.
Moshayedi, Sawhney et al. and Lee disclose the claimed invention except for each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop.
However, Joo et al. disclose each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop (see para. 81, where an SLC memory has a program loop number and an erase loop number and therefore uses program loops and erase loops for programming and erasing. This is well known in the art for SLC and MLC memories to use program and erase loops).
Moshayedi and Joo et al. are analogous art because they are from the same field of endeavor of non-volatile memory devices (see Moshayedi, abstract and Joo et al., abstract, regarding non-volatile memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop, as taught by Joo et al., in order to make sure the data has been properly programmed/erased. Utilizing program and erase loops for NAND flash memory is well known in the art and would be obvious to include in Moshayedi.
As to claim 9, Moshayedi, Sawhney et al., Lee and Joo et al. also discloses the storage device of claim 8, wherein the plurality of sets include a first set that includes the first bank at a first time period, and the controller maps a physical bank address of the second bank to a logical bank address of the first set when the first data is transferred to the second bank from the first bank, and assigns the first bank as the free bank at a second time period (see Moshayedi, para. 32, where data for an LBA may be moved between MLC and SLC, but the LBA would stay the same and would map to a different physical address instead. Also see para. 49, where when data is copied from SLC to MLC, the SLC bank or block is later assigned as a free bank/block).
As to claim 10, Moshayedi, Sawhney et al., Lee and Joo et al. also disclose the storage device of claim 8, wherein when the controller applies a read command to the first bank at a first time period, applies the erase command to the second bank at a second time period and receives a read request at the second time period, the first bank accepts the read request to provide a corresponding data to the controller (see Sawhney et al., para. 103 and 111, where during a migration operation, read requests may be directed toward both the source and destination storage component, which would be the first and second banks. Para. 98 states that the object pointers would point to the source storage component before migration, both components during migration and the destination component after migration. The object data retrieved first may then be returned to the requesting client. Therefore, the first bank or source would accept the read request as the destination is still being erased and getting ready to have the data migrated).
As to claim 11, Moshayedi, Sawhney et al., Lee and Joo et al. also disclose the storage device of claim 8, wherein when the controller applies a read command to the first bank at a third time period, applies a program command to the second bank at a fourth time period and receives a read request at the third time period, the second bank accepts the read request to provide a corresponding data to the controller (see Sawhney et al., para. 103 and 111, where during a migration operation, read requests may be directed toward both the source and destination storage component, which would be the first and second banks. Para. 98 states that the object pointers would point to the source storage component before migration, both components during migration and the destination component after migration. The object data retrieved first may then be returned to the requesting client. Therefore the second bank or destination would accept the read request as the data has recently been programmed in the second bank or destination).
As to claim 14, Moshayedi, Sawhney et al., Lee and Joo et al. also disclose the storage device of claim 8, wherein the controller controls a data migration operation from the first bank to the second bank (see Moshayedi, para. 25-27, where the flash array is controlled by a controller, and see para. 49 where data is migrated between the SLC and MLC blocks or banks) and where the I/O request is independent of the data migration operation (see para. 27 and 100-103, where there is uninterrupted access to data during migration and read operations may be directed toward either the source or destination storage device or both during migration. Therefore the I/O request would be independent of the data migration operation).
Referring to claim 15, Moshayedi disclose as claimed, a storage device comprising: a plurality of nonvolatile memory devices configured to store data and including a plurality of memory blocks (see para. 25-26, where a flash array that stores data may include multiple flash chips that may include both SLC and MLC flash, both which would include memory blocks); and a controller configured to control the plurality of nonvolatile memory devices, wherein the plurality of memory blocks are divided into a plurality of banks that include a first bank and a second bank (see para. 25-27, where the flash array is controlled by a controller and where the data is divided into a plurality of logical data blocks, which would be the plurality of banks. See para. 49, where a first bank would be an SLC block where data is being moved from, and a second bank would be the MLC block where data is being copied to), the plurality of banks are assigned into a plurality of sets and one free bank, each of the plurality of sets includes at least one bank (see para. 40-41, where the SLC and MLC flash chips are made up of data blocks, including free blocks. Logical data blocks would be assigned or associated with physical data blocks as indicated in para. 37, where a logical to physical block table is used. See para. 52, where sets of lists include blocks with different erase count ranges. Each list of blocks comprising an erase count range would be a set), the controller is configured to receive a read request from an external device (see para. 25 and 46-47 where the controller receives read/write requests from the host).
Moshayedi discloses the claimed invention except for where the reads requests are received while migrating first data from the first bank to the second bank, and configured to execute a read command on the first bank and execute a program command or an erase command on the second bank while migrating the first data from the first bank to the second bank, and the controller controls a data migration operation from the first bank to the second bank such that an 1/0 request is independent of the data migration operation; and where an erase command is applied to reset memory cell voltages and a program command is applied to set memory cell voltages; and where the read command is executed by applying a read voltage to a selected word-line and applying a read-pass voltage to unselected word-lines and a program command is executed by applying a program voltage to the selected word-line and a program pass voltage to the unselected word-lines and an erase command is executed by applying an erase voltage to a well of the plurality of memory blocks and applying a ground voltage to entire word-lines of the plurality of memory blocks; each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop.
However, Sawhney et al. disclose where the reads requests are received while migrating first data from the first bank to the second bank (see para. 103, where during a migration, read operations may be received and directed toward both the source and destination components) and configured to execute a read command on the first bank and execute a program command or an erase command on the second bank while migrating the first data from the first bank to the second bank (see para. 88, where a migration is from a source storage component or bank to a destination storage component or bank. Therefore a read command would be executed on the source bank to read the data that is being transferred to the destination storage where the same data would then be programmed or loaded), and the controller controls a data migration operation from the first bank to the second bank such that an 1/0 request is independent of the data migration operation (see para. 27 and 100-103, where there is uninterrupted access to data during migration and read operations may be directed toward either the source or destination storage device or both during migration. Therefore the I/O request would be independent of the data migration operation).
Moshayedi and Sawhney et al. are analogous art because they are from the same field of endeavor of migrating data in storage systems (see Moshayedi, abstract and para. 49, and Sawhney et al., abstract, regarding migrating data in storage systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise where the reads requests are received while migrating first data from the first bank to the second bank, and configured to execute a read command on the first bank and execute a program command or an erase command on the second bank while migrating the first data from the first bank to the second bank, and the controller controls a data migration operation from the first bank to the second bank such that an 1/0 request is independent of the data migration operation, as taught by Sawhney et al., in order to allow for uninterrupted access to data that is being migrated (see Sawhney et al., para. 25-27, regarding reasons for allowing for read access during migrations, including being able to access data that is being migrated during a migration).
Moshayedi and Sawney et al. disclose the claimed invention except for and where an erase command is applied to reset memory cell voltages and a program command is applied to set memory cell voltages; and where the read command is executed by applying a read voltage to a selected word-line and applying a read-pass voltage to unselected word-lines and a program command is executed by applying a program voltage to the selected word-line and a program pass voltage to the unselected word-lines and an erase command is executed by applying an erase voltage to a well of the plurality of memory blocks and applying a ground voltage to entire word-lines of the plurality of memory blocks; each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop.
However, Lee disclose where an erase command is applied to reset memory cell voltages and a program command is applied to set memory cell voltages (see para. 107-109, where a program voltage is applied for a program operation and a ground voltage is applied during an erase operation). and where the read command is executed by applying a read voltage to a selected word-line and applying a read-pass voltage to unselected word-lines and a program command is executed by applying a program voltage to the selected word-line and a program pass voltage to the unselected word-lines and an erase command is executed by applying an erase voltage to a well of the plurality of memory blocks and applying a ground voltage to entire word-lines of the plurality of memory blocks (see para. 107-113, explaining different voltages applied for program, erase and read operations).
Moshayedi and Lee are analogous art because they are from the same field of endeavor of non-volatile memory devices (see Moshayedi, abstract and Lee, para. 5, regarding non-volatile memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise where an erase command is applied to reset memory cell voltages and a program command is applied to set memory cell voltages; and where the read command is executed by applying a read voltage to a selected word-line and applying a read-pass voltage to unselected word-lines and a program command is executed by applying a program voltage to the selected word-line and a program pass voltage to the unselected word-lines and an erase command is executed by applying an erase voltage to a well of the plurality of memory blocks and applying a ground voltage to entire word-lines of the plurality of memory blocks, as taught by Lee, in order to properly execute operations on the memory device (See Lee, para. 45, where a change in voltage is used to determine data stored in a memory cell). It is well known in the art to utilize different voltages when performing different operations on a memory device, such as taught by Lee.
Moshayedi, Sawhney et al. and Lee disclose the claimed invention except for each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop.
However, Joo et al. disclose each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop (see para. 81, where an SLC memory has a program loop number and an erase loop number and therefore uses program loops and erase loops for programming and erasing. This is well known in the art for SLC and MLC memories to use program and erase loops).
Moshayedi and Joo et al. are analogous art because they are from the same field of endeavor of non-volatile memory devices (see Moshayedi, abstract and Joo et al., abstract, regarding non-volatile memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise each of the plurality of memory blocks configured to be programmed with a program loop and configured to be erased with an erase loop, as taught by Joo et al., in order to make sure the data has been properly programmed/erased. Utilizing program and erase loops for NAND flash memory is well known in the art and would be obvious to include in Moshayedi.
As to claim 16, Moshayedi, Sawhney et al., Lee and Joo et al. also disclose the storage device of claim 15, wherein when the controller applies the read command to the first bank at a first time period, applies the erase command to the second bank at a second time period and receives the read request at the second time period, the first bank accepts the read request to provide a corresponding data to the controller, and when the controller applies the read command to the first bank at a third time period, applies the program command to the second bank at a fourth time period and receives the read request at the third time period, the second bank accepts the read request to provide the corresponding data to the controller (see Sawhney et al., para. 103 and 111, where during a migration operation, read requests may be directed toward both the source and destination storage component, which would be the first and second banks. Para. 98 states that the object pointers would point to the source storage component before migration, both components during migration and the destination component after migration. The object data retrieved first may then be returned to the requesting client. Therefore, in the first scenario the first bank or source would accept the read request as the destination is still being erased and getting ready to have the data migrated. In the second scenario, the second bank or destination would accept the read request as the data has recently been programmed in the second bank or destination).
As to claim 17, Moshayedi, Sawhney et al., Lee and Joo et al. also disclose the storage device of claim 16, wherein the second bank is the free bank at the first time period, and when the first data is transferred to the second bank from the first bank, the first bank is assigned as the free bank at a fifth time period (see Moshayedi, para. 49, where when data is transferred from a first bank or block of SLC memory to a second bank or block of MLC memory, the MLC memory is initially a free block. However, after the copying, the SLC block is then erased and added to the free block of SLC. Therefore the first bank would be assigned as a free bank/block as a later step in the migration or during a fifth time period).
As to claim 18, Moshayedi, Sawhney et al., Lee and Joo et al. also disclose the storage device of claim 15, wherein a program operation and/or an erase operation are performed only in the free bank among the plurality of banks (see Moshayedi, para. 26, where each channel may accommodate send, write, or erase commands to a specific flash memory. As the different blocks and memories are on different channels, only one command at a specific time would be used for a block/channel at a time. Therefore when the free bank is getting programmed, only that bank would be programmed).
Claims 3, 5-6, 12-13 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Moshayedi in view of Sawhney et al., Lee and Joo et al. in view of Scott et al. (U.S. Patent Application Publication No. 2020/0004672), herein referred to as Scott et al.
As to claim 3, Moshayedi, Sawhney et al., Lee and Joo et al. also disclose the storage device of claim 2, wherein the second bank is the free bank at the first time period, and the controller performs a data migration operation among the plurality of sets by using the second bank in response to an input/output (I/O) request from the external device (see para. 41, where 3 units in MLC are kept as a data buffer for copying data and see para. 49, where the free block of MLC or second bank is used during a data migration. The data migration would be in response to an erase count reaching a threshold, which would occur in response to an I/O request).
Moshayedi, Sawhney et al., Lee and Joo et al. disclose the claimed invention except for where the I/O request is performed within an I/O execution time associated with the I/O request.
However, Scott et al. disclose where the I/O request is performed within an I/O execution time associated with the I/O request (see para. 81, where deterministic windows may be used to give a certain level of guaranteed performance. The guaranteed performance may be specified by a certain number of operations carried out within a certain period of time).
Moshayedi and Scott et al. are analogous art because they are from the same field of endeavor of flash memory (see Moshayedi, abstract, and Scott et al., abstract, regarding flash memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise where the I/O request is performed within an I/O execution time associated with the I/O request, as taught by Scott et al., in order to have a certain level of guaranteed performance (see Scott et al., para. 81, where having a certain deterministic window or I/O execution time would allow for a level of guaranteed performance).
As to claim 5, Moshayedi, Sawhney et al., Lee and Joo et al. disclose the claimed invention except for the storage device of claim 1, wherein the controller is configured to perform interfacing with the external device through a nonvolatile memory express (NVMe) protocol.
However, Scott et al. disclose wherein the controller is configured to perform interfacing with an external device through a nonvolatile memory express (NVMe) protocol (see fig. 1, showing a storage device interfacing with a host. See para. 37, where the SSD may use the NVMe protocol as an interface).
Moshayedi and Scott et al. are analogous art because they are from the same field of endeavor of flash memory (see Moshayedi, abstract, and Scott et al., abstract, regarding flash memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise wherein the controller is configured to perform interfacing with an external device through a nonvolatile memory express (NVMe) protocol, as taught by Scott et al., in order to allow for higher transmission speeds using NVME.
As to claim 6, Moshayedi, Sawhney et al., Lee, Joo et al. and Scott et al. also disclose the storage device of claim 5, wherein an I/O execution time is defined by the NVMe protocol (see Scott et al., para. 37, where the SSD may operate in accordance with the NVMe standard or protocol. See para. 81, where the SSD is configured to operate with the NVMe specification to allow for guaranteed performance which may be a specified by a certain number of operations carried out within a certain period of time).
As to claim 12, Moshayedi, Sawhney et al., Lee and Joo et al. disclose the claimed invention except for the storage device of claim 8, wherein the controller is configured to perform interfacing with an external device through a nonvolatile memory express (NVMe) protocol.
However, Scott et al. disclose wherein the controller is configured to perform interfacing with an external device through a nonvolatile memory express (NVMe) protocol (see fig. 1, showing a storage device interfacing with a host. See para. 37, where the SSD may use the NVMe protocol as an interface).
Moshayedi and Scott et al. are analogous art because they are from the same field of endeavor of flash memory (see Moshayedi, abstract, and Scott et al., abstract, regarding flash memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise wherein the controller is configured to perform interfacing with an external device through a nonvolatile memory express (NVMe) protocol, as taught by Scott et al., in order to allow for higher transmission speeds using NVME.
As to claim 13, Moshayedi, Sawhney et al., Lee and Joo et al. and Scott et al. also disclose the storage device of claim 12, wherein an I/O execution time is defined by the NVMe protocol (see Scott et al., para. 37, where the SSD may operate in accordance with the NVMe standard or protocol. See para. 81, where the SSD is configured to operate with the NVMe specification to allow for guaranteed performance which may be a specified by a certain number of operations carried out within a certain period of time).
As to claim 19, Moshayedi, Sawhney et al., Lee and Joo et al. disclose the claimed invention except for the storage device of claim 15, wherein the controller is configured to perform interfacing with the external device through a nonvolatile memory express (NVMe) protocol.
However, Scott et al. disclose wherein the controller is configured to perform interfacing with an external device through a nonvolatile memory express (NVMe) protocol (see fig. 1, showing a storage device interfacing with a host. See para. 37, where the SSD may use the NVMe protocol as an interface).
Moshayedi and Scott et al. are analogous art because they are from the same field of endeavor of flash memory (see Moshayedi, abstract, and Scott et al., abstract, regarding flash memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moshayedi to comprise wherein the controller is configured to perform interfacing with an external device through a nonvolatile memory express (NVMe) protocol, as taught by Scott et al., in order to allow for higher transmission speeds using NVME.
As to claim 20, Moshayedi, Sawhney et al., Lee and Joo et al. and Scott et al. also disclose the storage device of claim 19, wherein an I/O execution time is defined by the NVMe protocol (see Scott et al., para. 37, where the SSD may operate in accordance with the NVMe standard or protocol. See para. 81, where the SSD is configured to operate with the NVMe specification to allow for guaranteed performance which may be a specified by a certain number of operations carried out within a certain period of time).
Response to Arguments
Applicant’s arguments have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Joo et al. Joo et al. teaches where NAND flash memory uses erase and program loops for erasing and programming. In addition, both SLC and MLC memory may use erasing and program loops, as also shown additionally in Zainuddin et al. (U.S. Patent Application Publication No. 2023/0058038), para. 166-169, 175-186, or 209-212. Also see Zhang et al. (U.S. Patent Application Publication No. 2023/0023618), para. 52, showing that MLC and SLC devices may be programmed and erased with program and erase loops.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 stand rejected.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
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/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132