DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 3/25/26, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-13, 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lasser (US 20150325290) in view of Shin (US 11416178) and Song (US 20210208894).
With respect to claim 1, the Lasser reference teaches a memory controller configured to skip processing of a near-memory processing command in response to satisfaction of one or more skip criteria. (paragraph 27, where write circuitry 142 may include skipping logic 144. The skipping logic 144 may store a disable flag 146; and paragraph 36, where in response to the write command 182, the non-volatile memory 103 may determine whether to write the data according to the first mode that skips writing values into storage elements that contain the values or according to the second mode that writes the values into the storage elements that contain the values)
However, the Lasser reference does not explicitly teach wherein the near-memory processing command comprises a broadcast memory processing command capable of triggering local computations in parallel at a plurality of target memory elements; and wherein the satisfaction of the one or more skip criteria comprises an immediate operand in the near-memory processing command.
The Shin reference teaches it is conventional to have wherein the near-memory processing command comprises a broadcast memory processing command capable of triggering local computations in parallel at a plurality of target memory elements. (see fig. 1; and column 5, line 20 to 44, where data from the memory controller 100 may be provided in common to the first through N-th PIM circuits 221_1 through 221_N, and the first through N-th PIM circuits 221_1 through 221_N may perform calculation processing using the data in common. In addition, different information may be read from the first through N-th banks BANK 1 through BANK N and provided to the first through N-th PIM circuits 221_1 through 221_N, and accordingly, the first through N-th PIM circuits 221_1 through 221_N may perform calculation processing using the same data and different information; and the first through N-th PIM circuits 221_1 through 221_N may perform parallel calculation processing, and accordingly, read operations respectively on the first through N-th banks BANK 1 through BANK N may be performed in parallel)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Lasser reference to have wherein the near-memory processing command comprises a broadcast memory processing command capable of triggering local computations in parallel at a plurality of target memory elements, as taught by the Shin reference.
The suggestion/motivation for doing so would have been to allow performing of calculations in parallel using PIM circuits; and having information for a neural network computation to be efficiently read from the different rows of the banks. (Shin, column 14, lines 40-49)
However, the combination of the Lasser and Shin references does not explicitly teach wherein the satisfaction of the one or more skip criteria comprises an immediate operand in the near-memory processing command.
The Song reference teaches it is conventional to have wherein the satisfaction of the one or more skip criteria comprises an immediate operand in the near-memory processing command. (paragraph 185, where the arithmetic circuit 900 might not include the demultiplexers, and the plurality of adders may be modified to receive the arithmetic operation signal MUL_OP. The plurality of adders may be modified to, when the arithmetic operation signal MUL_OP is enabled, activate bypass paths and output arithmetic data, output from the plurality of multipliers, to the output terminal OUT of the arithmetic circuit 900)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Lasser and Shin references to have wherein the satisfaction of the one or more skip criteria comprises an immediate operand in the near-memory processing command, as taught by the Song reference.
The suggestion/motivation for doing so would have been to include processing-in-memory (PIM) devices which are capable of performing a deterministic arithmetic operation at a high speed. (Song, paragraph 57)
Therefore it would have been obvious to combine the Lasser, Shin, and Song references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the combination of Lasser, Shin, and Song references teaches the memory controller of Claim 1, wherein the one or more skip criteria are configured such that the near-memory processing command does not change values stored at the plurality of target memory elements. (Lasser, paragraph 27, where write circuitry 142 may include skipping logic 144. The skipping logic 144 may store a disable flag 146; and paragraph 36, where in response to the write command 182, the non-volatile memory 103 may determine whether to write the data according to the first mode that skips writing values into storage elements that contain the values [i.e. the data/values does not change because the write command is “skipped”] or according to the second mode that writes the values into the storage elements that contain the values)
With respect to claim 3, the combination of Lasser, Shin, and Song references teaches the memory command processing element of Claim 1, wherein the one or more skip criteria include whether the near-memory processing command an operation that is specified in a table. (Lasser, paragraph 34, where during operation, the data storage device 102 may set the disable flag 146 to indicate either a first mode of operation that skips writing values into storage elements or a second mode of operation that writes values into storage elements that already contain the values. In a particular example, a first value of the disable flag 146 (e.g., non-assertion of the disable flag 146) causes the non-volatile memory 103 to operate according to the first mode, and a second value of the disable flag 146 (e.g., assertion of the disable flag 146) causes the non-volatile memory 103 to operate according to the second mode; and Song, paragraph 185, where the arithmetic circuit 900 might not include the demultiplexers, and the plurality of adders may be modified to receive the arithmetic operation signal MUL_OP. The plurality of adders may be modified to, when the arithmetic operation signal MUL_OP is enabled, activate bypass paths and output arithmetic data, output from the plurality of multipliers, to the output terminal OUT of the arithmetic circuit 900)
With respect to claim 4, the combination of Lasser, Shin, and Song references teaches the memory command processing element of Claim 1, wherein: the near-memory processing command specifies an operation and a location where a result of the operation is to be stored, and the one or more skip criteria include whether the result of the operation is the same as a current value stored at the location where the result of the operation is to be stored. (Lasser, paragraph 36, where in response to the write command 182, the non-volatile memory 103 may determine whether to write the data according to the first mode that skips writing values into storage elements that contain the values or according to the second mode that writes the values into the storage elements that contain the values)
With respect to claim 5, the combination of Lasser, Shin, and Song references teaches the memory command processing element of Claim 1, wherein the one or more skip criteria include whether the near-memory processing command specifies that the near- memory processing command is not to be skipped. (Lasser, paragraph 34, where during operation, the data storage device 102 may set the disable flag 146 to indicate either a first mode of operation that skips writing values into storage elements or a second mode of operation that writes values into storage elements that already contain the values. In a particular example, a first value of the disable flag 146 (e.g., non-assertion of the disable flag 146) causes the non-volatile memory 103 to operate according to the first mode, and a second value of the disable flag 146 (e.g., assertion of the disable flag 146) causes the non-volatile memory 103 to operate according to the second mode)
With respect to claim 7, the combination of Lasser, Shin, and Song references teaches the memory command processing element of Claim 1, wherein the processing logic is further configured to skip a plurality of near-memory processing commands that store their respective results to a same location, and wherein a net result of the plurality of near-memory processing commands is the same as a current value stored at the location. (Lasser, paragraph 34, where during operation, the data storage device 102 may set the disable flag 146 to indicate either a first mode of operation that skips writing values into storage elements or a second mode of operation that writes values into storage elements that already contain the values. In a particular example, a first value of the disable flag 146 (e.g., non-assertion of the disable flag 146) causes the non-volatile memory 103 to operate according to the first mode, and a second value of the disable flag 146 (e.g., assertion of the disable flag 146) causes the non-volatile memory 103 to operate according to the second mode)
With respect to claim 8, the combination of Lasser, Shin, and Song references teaches the memory command processing element of Claim 1, wherein the memory controller includes one or more of a cache, a queue, or a buffer. (Lasser, paragraph 130, where controller 120 may send the data (or a representation of the data) to the memory 1200 to be stored in the data latches 1202. For example, the controller 120 may encode the data prior to sending the encoded data to the data latches 1202 [analogous to a ‘cache, a queue, or a buffer’])
Claims 9-13 and 15 are the processor implementation of claims 1-5 and 7-8, and rejected under the same rationale as above.
With respect to claim 16, the combination of Lasser, Shin, and Song references teaches the processor of Claim 9, wherein the processor is one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Logic Array (FPGA), an accelerator, or a Digital Signal Processor (DSP). (Lasser, paragraphs 141-142)
Claims 17-20 are the method implementation of claims 1-5 and 7-8, and rejected under the same rationale as above.
Claims 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lasser in view of Shin and Song as shown in the rejections above, and further view of Brittain (US 20060179333).
With respect to claim 6, the combination of Lasser, Shin, and Song references does not explicitly teach the memory command processing element of Claim 1, wherein the one or more skip criteria include whether a current processing level of the memory command processing element exceeds a processing level threshold.
The Brittain reference teaches it is conventional to have wherein the one or more skip criteria include whether a current processing level of the memory command processing element exceeds a processing level threshold. (paragraph 18, where when the controller logic determines that a DIMM/DRAM has been issued enough processing load to reach/approach this threshold value, the memory controller withholds issuing additional read/writes targeting the particular DIMM/DRAM. The memory controller skips these reads/writes and issues other reads/writes targeting other DIMMs that have not yet reached their threshold value)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of Lasser, Shin, and Song references to have wherein the one or more skip criteria include whether a current processing level of the memory command processing element exceeds a processing level threshold, as taught by the Brittain reference.
The suggestion/motivation for doing so would have been to throttle the number/frequency at which commands (read/write operations) are issued to the specific DIMM/DRAM based on the specific DIMM/DRAM reaching the preset threshold power/temperature value. (Brittain, paragraph 16)
Therefore it would have been obvious to combine the Lasser, Shin, Song, and Brittain references for the benefits shown above to obtain the invention as specified in the claim.
Claim 14 is the processor implementation of claim 6, and rejected under the same rationale as above.
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 2-7 of the remarks) with respect to claims 1-20 have been considered, and are not persuasive.
In response to applicant’s argument (see argument A on pages 2-3) that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the Applicant appears to arguing the motivation of combining the Shin reference to produce the Applicant’s claimed invention. The Examiner notes the Shin reference is included to teach the limitation of “the near-memory processing command comprises a broadcast memory processing command capable of triggering local computations in parallel at a plurality of target memory elements” as shown in the rejection above. Shin teaches (see fig. 1; and column 5, line 20 to 44) where data from the memory controller 100 may be provided in common to the first through N-th PIM circuits 221_1 through 221_N, and the first through N-th PIM circuits 221_1 through 221_N may perform calculation processing using the data in common; and in addition, different information may be read from the first through N-th banks BANK 1 through BANK N and provided to the first through N-th PIM circuits 221_1 through 221_N, and accordingly, the first through N-th PIM circuits 221_1 through 221_N may perform calculation processing using the same data and different information; and the first through N-th PIM circuits 221_1 through 221_N may perform parallel calculation processing, and accordingly, read operations respectively on the first through N-th banks BANK 1 through BANK N may be performed in parallel.
The motivation to combine the Shin reference with the Lasser and Song references is to
“allow performing of calculations in parallel using PIM circuits; and having information for a neural network computation to be efficiently read from the different rows of the banks” (Shin, column 14, lines 40-49) as shown in the rejections above. Thus, the Examiner has maintained the rejections for the reasons set forth above.
In response to Applicant’s argument (see argument B of pages 3-4), the Applicant appears to argue that the “commands” are not modifiable to produce the Applicant’s claimed invention. As shown in the responses above, the Shin reference is included to teach that calculations can be performed in parallel through multiple memory banks, and not necessarily to teach a “near processing command” which is taught by the Lasser reference as shown in the rejections above. Thus, the Examiner contends that the “near-memory processing command” as discussed by Lasser would be modifiable by “parallel processing” of the Shin reference to produce the Applicant’s claimed invention for the reasons set forth above.
In response to Applicant’s argument (see argument C of page 4), the Applicant appears to argue that the memory controller of the Lasser reference is not a “memory controller configured to skip”. The Examiner notes the Lasser reference is included to teach “a memory controller configured to skip processing of a near-memory processing command in response to satisfaction of one or more skip criteria”. Lasser teaches (paragraph 27) where write circuitry 142 may include skipping logic 144; and the skipping logic 144 may store a disable flag 146; and further teaches (paragraph 36) where in response to the write command 182, the non-volatile memory 103 may determine whether to write the data according to the first mode that skips writing values into storage elements that contain the values or according to the second mode that writes the values into the storage elements that contain the values. Thus, in view of the citations above, the Examiner does not rely on the memory controller as argued. Further, even if the “memory controller” of Lasser was included to teach the limitation above, the memory controller and the write circuitry work in tandem to “skip” the processing as shown in figs. 1-3 and at least paragraph 35.
In response to Applicant’s argument (see argument D of pages 4-5), the Applicant appears to argue that the Song reference does not teach "A memory controller configured to skip … skip criteria comprises checking an immediate operand in the near-memory processing command". The Song reference is included to teach the limitation of “wherein the satisfaction of the one or more skip criteria comprises an immediate operand in the near-memory processing command” as shown in the rejections above. The Song reference teaches (paragraph 185) where the arithmetic circuit 900 might not include the demultiplexers, and the plurality of adders may be modified to receive the arithmetic operation signal MUL_OP; and the plurality of adders may be modified to, when the arithmetic operation signal MUL_OP is enabled, activate bypass paths and output arithmetic data, output from the plurality of multipliers, to the output terminal OUT of the arithmetic circuit 900. Thus, based on the citations above, the Song reference is not relied upon to teach a “memory controller” but the modification of the “skip criteria [that] comprises checking an immediate operand in the near-memory processing command” which is shown by the bypassing (analogous to the ‘skipping’ as claimed) of the adders (and their corresponding addition operations) and outputting from the multipliers based on the arithmetic operation signal MUL_OP being enabled (analogous to an ‘operand’ as claimed) as shown in the citations above. Thus, the Examiner has maintained the rejections.
In response to Applicant’s argument (see argument E of page 6), the Applicant appears to argue that the “memory controller” of the Shin reference and the “PIM” of Song reference would not be combinable. As shown in the responses and rejections above, the Song reference is included to “wherein the satisfaction of the one or more skip criteria comprises an immediate operand in the near-memory processing command”. Thus, the Song reference is included merely to teach satisfaction of the one or more skip criteria, and not the “memory controller” and the “PIM” structural teachings as argued.
In response to Applicant’s argument (see argument F of pages 6-7), the Applicant appears to argue the limitation of “skip criteria comprises checking an immediate operand in the near- memory processing command” is not taught by the Song reference. Specifically, the Applicant appears to argue the “signals … circuit” are not comparable to the operand in a command as claimed. The Examiner notes the Song reference (paragraphs 60-61 and 185; and explained above in the other response) teaches a PIM device that receives commands which performs calculations, which are a subset of the commands, which may bypass certain calculations based on the MUL_OP signal (analogous to the claimed “operand”). The Examiner further notes the other arguments pertaining to claims 3, 7, and 8 do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
In response to any other arguments not specifically addressed, the Examiner notes the responses above.
3. CLOSING COMMENTS
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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