Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is non-final and is in response to claims filed on 05/10/2022. Claims 1-7 are pending for examination.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 05/10/2022 are in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. They have been placed in the application file, and the information referred to therein has been considered as to the merits. Except for the NPL entitled “AND TECHNOLOGY”, since its contents was not included in the application.
Claim Objections
Claims 4-5 are objected to because of the following informalities:
Claim 4 should recite “wherein the n bits extracted at step b) are a least significant bit(s) of the timestamp register.”
Claim 5 should recite “the bit extracted at step b) is a least significant bit of the timestamp register.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "b) extracting at a given time n bits from the least significant bits" in line 3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, examiner has interpreted “b) extracting at a given time n bits from the least significant bits” as “b) extracting at a given time n bits from a least significant bits”
Claim 1 recites “b) extracting at a given time n bits from the least significant bits of the register”. It is unclear if this is the internal timestamp register or a different register. For examination purposes, examiner has interpreted “b) extracting at a given time n bits from the least significant bits of the register” as “b) extracting at a given time n bits from the least significant bits of the internal timestamp register”.
Claims 2-7 are rejected for being dependent on an above rejected claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 1, at step 1, the claim is directed to a method, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A random number generation method implemented by means of a digital processor, (mental process, evaluation) the method comprising: (mental process, evaluation)
a) searching an internal timestamp register which counts clock pulses for sequencing the processor; (mental process, evaluation)
b) extracting at a given time n bits from the least significant bits of the register, n >= 1; (mental process, evaluation; mathematical calculation)
c) using the n bits extracted at step b) as constituent bit(s) of a random number of N bits to be generated; (mental process, evaluation; mathematical calculation)
d) reiterating steps a) to c) until obtaining the N bits of the random number; and (mental process, evaluation; mathematical calculation)
e) providing the random number to an application circuit or software. (mathematical calculation)
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “A random number generation method implemented” limitation is an evaluation mental process that can be performed by choosing how the method is implemented. The “the method comprising” limitation is an evaluation mental process that can be performed by choosing what the method comprises. The “searching an internal timestamp register which” limitation is an evaluation mental process that can be performed by looking at the timestamp register. The “extracting at a given time n bits” limitation is an evaluation mental process and mathematical calculation that can be performed by extracting the bits by hand using pen and paper. The “using the n bits extracted at step b)” limitation is an evaluation mental process and mathematical calculation that can be performed by generating the random number by hand using pen and paper. The “reiterating steps a) to c) until” limitation is an evaluation mental process and mathematical calculation that can be performed by generating the random number by hand using pen and paper. The “providing the random number to” limitation is a mathematical calculation that can be performed by providing the random number by hand using pen and paper.
At step 2A Prong 2, the additional elements are bolded above. The “providing” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘providing’ in the context of the claim encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “providing the random number to an application circuit or software”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 2, it is directed to mental processes and/or mathematical concepts. The “wherein the timestamp register is a register counting pulses” limitation is an evaluation mental process that can be performed by choosing what the timestamp register does. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. the timestamp register, the oscillator of the clock, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 3, it is directed to mental processes and/or mathematical concepts. The “wherein steps a) to d) are carried out within” limitation is an evaluation mental process that can be performed by choosing where the steps are carried out. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. the firmware, the processor, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 4, it is directed to mental processes and/or mathematical concepts. The “wherein the n bits extracted at step b) are” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing what bits to extract by hand using pen and paper. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. the timestamp register, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 5, it is directed to mental processes and/or mathematical concepts. The “wherein n = 1” limitation is an evaluation mental process that can be performed by choosing what n equals. The “the bit extracted at step b) is the least significant bit” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing what bits to extract by hand using pen and paper. Under step 2A Prong 2, the “received” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘received’ in the context of the claim encompasses mere data gathering. none of the remaining additional elements regarding the generic computer components (i.e. the application circuit, the software, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 6, it is directed to mental processes and/or mathematical concepts. The “wherein the given time of extraction” limitation is an evaluation mental process that can be performed by choosing how the time of extraction is controlled. The limitation “a random or pseudo-random generator” is no more than generally linking the use of the judicial exception to a field of use. see MPEP 2106.05(h). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 7, it is directed to mental processes and/or mathematical concepts. The “wherein the given time of extraction” limitation is an evaluation mental process that can be performed by choosing how the time of extraction is controlled. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. the timestamp register, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “in response to a request received from the application circuit or software”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Marton et al. (“Randomness Assessment of an Unpredictable Random Number Generator based on Hardware Performance Counters”) as included in the IDS filed 05/10/2022, hereinafter Marton in view of Hironori et al. (Machine Translation of JP 2021026290 A) hereinafter Hironori.
With regards to claim 1, Marton teaches A random number generation method implemented by means of a digital processor, (Marton Page 136 Abstract: We have previously investigated the potential of hardware events captured by performance counters to provide entropy sources for generating unpredictable random number sequences, and now we extend the generator model introduced in [1] by various delay types and simple operations which show high impact on the internal behavior of the processor)
the method comprising: a) searching an internal timestamp register which counts clock pulses for sequencing the processor; (Marton Page 136 Abstract: We have previously investigated the potential of hardware events captured by performance counters to provide entropy sources for generating unpredictable random number sequences, and now we extend the generator model introduced in [1] by various delay types and simple operations which show high impact on the internal behavior of the processor; Matron Page 137 Section 2: Hence these registers can count the number of hardware events such as cache accesses and misses, instruction counts, stalls in the pipeline, TLB misses, retired instructions, hardware interrupts, clock cycles and various other events)
b) extracting at a given time n bits from the least significant bits of the register, n >= 1 (Marton Page 142 Section 3.1: According to this model, the generator samples all of the selected hardware counters for a number of n iterations, each time extracting ẞ bits from the least significant part of every counter value)
c) using the n bits extracted at step b) as constituent bit(s) of a random number of N bits to be generated; (Marton Page 152 Section 4.5: In order to combine the results of each counter and compute a single output sequence when sampling the hardware counters in event sets we have tested three methods, namely simple concatenation)
d) reiterating steps a) to c) until obtaining the N bits of the random number; (Marton Page 152 Section 4.5: In order to combine the results of each counter and compute a single output sequence when sampling the hardware counters in event sets we have tested three methods, namely simple concatenation; Marton Page 142 Section 3.1: n is the total number of samples taken for the considered event or event set e)
and e) providing the random number to [an application circuit or software.] (Marton Page 136-137 Section 1: the central reason that links all these domains to randomness is the need to meet the demand for providing number sequences that satisfy some or several of the effective laws of randomness, such as the independency of values, uniform distribution, unpredictability, irreproducibility, and indeed many others. One of the application domains which imposes the most exacting requirements on the source and quality of randomness is cryptography (and in general information security). The essential ingredient that empowers information protection methods to become effective and carry over the trust found in the physical world to the electronic world is randomness, in all its different forms and roles, such as cryptographic keys, initialization vectors, padding values, nonces and many others)
While Marton teaches different applications of the random number, Marton does not teach an application circuit or software.
However, Hironori does teach sending the random number of Marton to an application circuit or software (Hironori Page 2 Paragraph 16: the ECU 2 transmits the random number 35 used for the authentication of the update control device 4 to the update control device 4).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Marton with sending the random number to an application circuit or software as taught by Hironori. One of ordinary skill in the art would be motivated to make this combination because it would increase the flexibility of the system as the random number could be sent to many different systems for different applications.
With regards to claim 3, Marton in view of Hironori teaches all of the limitations of claim 1 above. Marton further teaches wherein steps a) to d) are carried out within a firmware of the processor (Marton Page 136 Abstract: Hardware performance counters capture and measure hardware events within the processor, providing a detailed indication on the internal behavior and performance of the various micro-architectural components within the processor while running system or user level programs. We have previously investigated the potential of hardware events captured by performance counters to provide entropy sources for generating unpredictable random number sequences, and now we extend the generator model).
With regards to claim 4, Marton in view of Hironori teaches all of the limitations of claim 1 above. Marton further teaches wherein the n bits extracted at step b) are the least significant bit(s) of the timestamp register (Marton Page 142 Section 3.1: According to this model, the generator samples all of the selected hardware counters for a number of n iterations, each time extracting ẞ bits from the least significant part of every counter value).
With regards to claim 5, Marton in view of Hironori teaches all of the limitations of claim 4 above. While Marton teaches extracting the least significant bits of the register, Marton fails to teach wherein n = 1 and the bit extracted at step b) is the least significant bit of the timestamp register.
However, Hironori teaches wherein n = 1 and the bit extracted at step b) is the least significant bit of the timestamp register (Hironori Page 4 Paragraph 10: The first extraction unit 262 receives the first count value 51A from the counter 261 and extracts the bit value of the least significant bit from the received first count value 51A).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Marton with extracting the least significant bit as taught by Hironori. One of ordinary skill in the art would be motivated to make this combination because it would make calculations faster as the system only has to deal with 1 bit at a time.
With regards to claim 6, Marton in view of Hironori teaches all of the limitations of claim 1 above. Marton further teaches wherein the given time of extraction of the n bits at step b) is a time controlled by a random or pseudo-random generator (Marton Page 142 Section 3.1: The formal model of the proposed generator is based on the generator described in [1] and is extended in order to allow several delay types and postprocessing functions… the delay introduced between two successive samples of the chosen counters. This delay can take many forms and may contain several instructions which influence the internal state of the processor).
With regards to claim 7, Marton in view of Hironori teaches all of the limitations of claim 1 above. Marton further teaches wherein the given time of extraction of the n bits at step b) is a time determined in response [to a request received from the application circuit or software] (Marton Page 142 Section 3.1: According to this model, the generator samples all of the selected hardware counters for a number of n iterations, each time extracting ẞ bits from the least significant part of every counter value).
Marton fails to teach that the extraction of the bits is determined in response to a request received from the application circuit or software.
However, Hironori teaches that the extraction of the bits of Marton are determined in response to a request received from the application circuit or software (Hironori Page 3 Paragraph 2: the update control device 4 transmits the random number transmission request).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Marton with extracting the least significant bits being in response to a request received from the application circuit or software as taught by Hironori. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system because the system would only need to generate the random number when a request was received.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Marton in view of Hironori further in view of Katsunori et al. (Machine Translation of JP 2019192989 A) hereinafter Katsunori.
With regards to claim 2, Marton in view of Hironori teaches all of the limitations of claim 1 above. Marton further teaches wherein the timestamp register is a register [counting pulses directly outputted from an oscillator of the clock] (Marton Page 136 Abstract: We have previously investigated the potential of hardware events captured by performance counters to provide entropy sources for generating unpredictable random number sequences, and now we extend the generator model introduced in [1] by various delay types and simple operations which show high impact on the internal behavior of the processor; Matron Page 137 Section 2: Hence these registers can count the number of hardware events such as cache accesses and misses, instruction counts, stalls in the pipeline, TLB misses, retired instructions, hardware interrupts, clock cycles and various other events).
While Marton teaches of a register that counts clock cycles, Marton fails to teach the register counting pulses directly outputted from an oscillator of the clock.
However, Katsunori does teach the register of Marton counting pulses directly outputted from an oscillator of the clock (Katsunori Page 3 Paragraph 3: In the time client 16 shown in FIG. 2, the free-run crystal oscillator 50 outputs a pulse signal to the clock counter 36. The clock counter 36 counts the pulse signal output from the free-run crystal oscillator).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Marton with counting pulses directly outputted from an oscillator of the clock as taught by Katsunori. One of ordinary skill in the art would be motivated to make this combination because it would increase the precision of the system, as it would make sure that the clock cycles are counted accurately.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jakob O Gudas whose telephone number is (571)272-0695. The examiner can normally be reached Monday-Thursday: 7:30AM-5:00PM Friday: 7:30AM-4:00PM.
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/J.O.G./Examiner, Art Unit 2182
/NICHOLAS KLICOS/Primary Examiner, Art Unit 2118