DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/06/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9, 10, 12 is rejected under 35 U.S.C. 103 as being unpatentable over Schutenberg et al (US 9842051, Schuttenberg) in view of Kamikubo (US 20190079870) and further in view of Jalal et al (US 20130042078, Jalal).
As to claim 9, Schuttenberg discloses a controller comprising:
a cache tag bank (fig. 3 tag array 332, 334);
a memory bank (line array 340, 342); and
a snoop filter (3-350) coupled to the cache tag bank and the memory bank (fig. 1 memory 104) by a cache line (fig. 5, entries in 5-350),
wherein the cache line includes:
a cache tag address (SnTag 506) associated with a data element;
a state of the cache tag address (SnValid 504); and
a value of the memory bank associated with the cache tag address (SCIO 508-512).
Schuttenberg does not disclose the cache tag bank that includes a first status indicator and a second status indicator. In the same field of art (memory), Kamikubo discloses an arithmetic processing unit which includes a cache including a cache memory for storing states of data and data in a block at an index of the memory access request (col 1 ln 65-67). In one embodiment, Kamikubo a cache tag bank that includes a first status indicator and a second status indicator (fig. 3 W0-W3, par. 68). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Schuttenberg and Kamikubo, by including the cache tag bank with a first status indicator and a second status indicator. The motivation is to improve the reliability of the system (par. 9).
Schuttenberg does not disclose wherein the cache tag bank, the snoop filter, and the memory bank are in separate memory devices. In the same field of art (memory), Jalal discloses an apparatus for processing data comprising: a plurality of transaction sources, each of said plurality of transaction sources having a local cache memory (par. 7). In one embodiment, Jalal discloses a cache tag bank (fig. 1, L1$-L3$ 16), a snoop filter (filter 14), and a memory bank (memory 5) are in separate memory devices (fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Schuttenberg/Kamikubo and Jalal, by configuring the cache tag bank, the snoop filter, and the memory bank in separate memory devices. The motivation is to improve the efficiency of the system (par 6 “consumed in terms of gate count, power, area and the like”).
As to claim 10, Schuttenberg/Kamikubo/Jalal discloses the controller of claim 9, wherein: an entry in the snoop filter corresponds to an entry in the cache tag bank (Jalal, fig. 2 “shared cache tag values) and an entry in the memory bank (par. 42 “returned target cache line of data from the main memory 6”).
As to claim 12, Schuttenberg/Kamikubo/Jalal discloses the controller of claim 9, wherein:
the state of the cache tag address includes one of shared, unique, invalid, modified, owned, and exclusive (Schuttenberg, col 8 ln 50-54 “indicates whether the SnTag 506 is valid”).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Schuttenberg in view of Kamikubo/Jalal and further in view of Jalal et al (US 20170168939, Jalal2).
As to claim 11, Schuttenberg/Kamikubo/Jalal discloses the controller of claim 9, but does not disclose wherein: the state of the cache tag address indicates a cache of a master peripheral stores a value associated with cache tag address. In the same field of art (memory), Jalal2 discloses a data processing system, having two or more of processors that access a shared data resource (abstract). In one embodiment, Jalal2 discloses that a state of the cache tag address (fig. 3, state 312 of tag 310) indicates a cache of a master peripheral (par. 14, master devices 104) stores a value associated with cache tag address (par. 26, “MOESI state of the data”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Schuttenberg/Kamikubo/Jalal and Jalal2, by comprising the state of the cache tag address to indicate a cache of a master peripheral stores a value associated with cache tag address. The motivation is to improve the efficiency of the system (par 6 “consumed in terms of gate count, power, area and the like”).
Allowable Subject Matter
Claims 1-8 and 13-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The primary reason for allowance of claims 1 and 13 in the instant application is “applying, by the controller, the tag to a snoop filter bank to determine a snoop filter result a memory bank result that includes a second status indicator; applying, by the controller, the tag to a memory bank to determine a memory bank result that includes a third status indicator; and determining, by the controller, based on the cache tag result, the snoop filter result, and the memory bank result whether to access a cached value of the data element or access the data element at the physical memory address of the data element, wherein the cache tag bank, the snoop filter bank, and the memory bank are in separate memory devices”, in combination with other steps/elements in the claims. The prior art of record including the disclosures of Tran (US 20130212585), Jamil et al (US 8990505) and Kamikubo (US
20190079870) neither anticipates nor renders obvious the above limitation. Because claims 2-8 and 14-20 depend directly or indirectly on either one of claims 1 or 13, these claims are considered allowable for at least the same reasons noted above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/D.P/ Examiner, Art Unit 2184
/STEVEN G SNYDER/ Primary Examiner, Art Unit 2184