Prosecution Insights
Last updated: May 04, 2026
Application No. 17/743,085

CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT

Non-Final OA §102§103
Filed
May 12, 2022
Priority
Dec 30, 2021 — provisional 63/295,139
Examiner
FAN, CHIEH M
Art Unit
2632
Tech Center
2600 — Communications
Assignee
Intel Corporation
OA Round
3 (Non-Final)
24%
Grant Probability
At Risk
3-4
OA Rounds
0m
Est. Remaining
22%
With Interview

Examiner Intelligence

Grants only 24% of cases
24%
Career Allowance Rate
5 granted / 21 resolved
-38.2% vs TC avg
Minimal -2% lift
Without
With
+-2.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
17 currently pending
Career history
38
Total Applications
across all art units

Statute-Specific Performance

§101
6.1%
-33.9% vs TC avg
§103
41.9%
+1.9% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
14.2%
-25.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 21 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is responsive to the RCE filed on 10/06/25 and the Amendment filed on 08/05/25. Accordingly, claims 1 and 3-20 are currently pending; and claim 2 is canceled. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 16, 17, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Truong et al (2008/0175327) previously cited. -Regarding claim 16, Truong et al teaches a method to be performed by a transmitter (being one among dies (“IC chips”, [0011])) of a die-to-die (D2D) interconnect link (“communication buses”, [0011])), wherein the method (see figure 6) comprises: identifying, by (603) of the transmitter, a phase of a data signal (608) to be transmitted on a data lane (605) of the D2D interconnect link, by clocking the data signal using a master clock (601, 613) (further see (601, 602, 608) of figure 9 and [0035]); identifying, by (Master Clk, 611) of the transmitter, a phase being a phase of a clock (612)) of a clock signal to be transmitted on a clock lane (625, 626) of the D2D interconnect link (further see (601, 612) of figure 9 and [0036]); adjusting, by (620) of the transmitter, the phase of the clock signal so that the phase of the clock signal is 90 degrees (“one-fourth of its clock cycle”, [0012]), or namely approximately 90 degrees, from the phase of the data signal to form a phase adjusted clock signal (being a differential clock signal (618, 628)), by shifting the clock signal by one-half cycle of the master clock, (further (612, 618) of figure 9 and [0036]), and transmitting, by (620) of the transmitter, the clock signal and transmitting, via (603), the data signal on the clock lane and the data lane, respectively. -Regarding claim 17, Truong et al teaches that adjustment of the phase of the clock signal includes adjustment of the phase of the clock signal such that a rising edge (being a rising edge of (618)) of the clock signal (618, 628) is at the approximate center of a unit interval (UI) (being a pulse width) of the data signal (608), (see (608, 618) of figure 9). -Regarding claim 19, Truong et al teaches that an amount (=90 degrees ) of adjustment of the phase of the clock signal is based on a predetermined mismatch (being a phase mismatch (=one fourth of the clock signal) ) between a parameter (being clock edges) of the clock signal and a parameter (being data edges) of the data signal (see [0012]). -Regarding claim 20, Truong et al teaches that based upon phase information of the mater clock (601, 613), adjustment of the phase of the clock signal includes: identification of a time location of a left edge (being a rising edge) of a unit interval (UI) (being a pulse width) of the data signal (608) (see the identification indicated by an arrow pointing to the time location of the left edge shown in figure 9); identification of a time location of a right edge (being a falling g edge) of the UI of the data signal (see the identification indicated by an arrow pointing to the time location of the falling edge shown in figure 9); and identification/knowing, based, via the phase information of the mater clock, on the time location of the left edge of the UI and the time location of the right edge of the UI, of a time location of a center of the UI (see the identification indicated by an arrow pointing to the time location the a center of the UI shown in figure 9). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Truong et al in view of Das Sharma et al (2018/0276164) previously cited. -Regarding claim 18, as for claim 16, Truong et al teaches that the interconnect link includes the data lane and the clock lane. Truong et al does not teach whether the interconnect link includes a valid lane on which a valid signal is transmitted that is used by the receiver die to frame the data signal, as claimed. In analogous art, Das Sharma et al teaches that an interconnect link (615) between a transmitter die (605) and a receiver die (610) can include a valid lane (“one or more dedicated lanes for a valid signal”, [0070]) (see figure 6), the valid lane on which a valid signal “valid” is transmitted to the receiver die to inform about an incoming of a data signal and is used by the receiver die to frame the data signal into frames for preparing for and sampling the incoming data signal in corresponding frames (e.g., (720, 725) of figure 7), (see [0078]). For application, it would have been obvious for one skilled in the art, at the time the invention was made, to further implement Truong et al, as taught by Das Sharma et al, in such a way that the interconnect link would further include a valid lane on which a valid signal is transmitted to the receiver die to inform about an incoming of a data signal and is used by the receiver die to frame the data signal into frames for preparing for and sampling the data signal in corresponding frames, so that with the implementation, the receiver die would be additional enhanced with features of being informed, via the valid signal, about the incoming of the data signal, and preparing for and sampling the incoming data signal in corresponding frames, upon reception of the valid signal. Allowable Subject Matter Claims 1 and 3-15 are allowed. Response to Arguments Applicant's arguments filed on 08/05/25 have been fully considered but they are, in part, not persuasive. -As results, claims 1 and 3-15 are allowed. -With respect to claims 16-20, the applicant argues that claims 16-20 should be allowable because claim 9, after amended, are allowable. The examiner respectfully disagrees. The rejections to claims 16-20 are still maintained, as set forth above in this Office Action, because (i) claims 16-20 have different scopes from claim 9 and are not depended on claim 9, and (ii) claims 16-20 are without any further amendment. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG M PHU whose telephone number is (571)272-3009. The examiner can normally be reached 8:00-16:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHUONG PHU/ Primary Examiner Art Unit 2632
Read full office action

Prosecution Timeline

Show 2 earlier events
Jan 28, 2025
Non-Final Rejection — §102, §103
Apr 30, 2025
Response Filed
Jun 04, 2025
Final Rejection — §102, §103
Aug 05, 2025
Response after Non-Final Action
Oct 06, 2025
Request for Continued Examination
Oct 10, 2025
Response after Non-Final Action
Dec 23, 2025
Non-Final Rejection — §102, §103
Mar 31, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
24%
Grant Probability
22%
With Interview (-2.0%)
3y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 21 resolved cases by this examiner. Grant probability derived from career allowance rate.

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