Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation is:
a plurality of combination units, each combination unit arranged to replace a different group of the one or more groups of input modulo k values with the combined modulo k value of the sum of that group of input modulo k values, as in claim 5.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. The following is being interpreted based on review of the disclosure:
The disclosure describes at least two embodiments of the combination units, wherein one embodiment describes the plurality of combination units operating on binary representation data, and a second embodiment describes the combination units operating on one-hot representation data, or a combination thereof. See p. 9.
As to the embodiment wherein the plurality of combination units operate on one-hot representation data, the plurality of combination units are interpreted to be configured in arrangement including input and output connections as in figure 11, and wherein the structure is interpreted to comprise a barrel shifter as in figure 9 including input and output connections and equivalents.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Specification
The specification is objected to because the limitations “a plurality of combination units” invoke 35 USC 112(f) or pre-AIA USC 112 sixth paragraph. The broadest reasonable interpretation of these claim elements is the structure, material, or acts described in the specification for performing the entire claim function and equivalents. See MPEP 2181. However, the written description fails to provide an adequate disclosure of the structure, material, or acts to perform the claimed functions of these limitations for the embodiment wherein the plurality of combination units operating on binary representation data. See rejection under 35 USC 112(b) below for further details as to the disclosure requirement.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skill in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The claim 5-6 limitation a “plurality of combination units” invoke 35 USC 112(f) or pre-AIA 35 USC 112, sixth paragraph. However, the written description fails to provide an adequate description of the structure, material, or acts to perform the claimed functions of these limitations for the embodiment wherein the plurality of combination units operating on binary representation data. See rejection under 35 USC 112(b) below for further details as to the lack of structure. Claim 6 inherits the same deficiency as claim 6 based on dependence.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 2 recites “input data value analysis circuitry configured to consider an input value”. It is unclear what is meant by “to consider”. For purposes of examination, Examiner interprets as “to receive”. Claims 2-19 inherit the same deficiency as claim 1 based on dependence. Claim 20, and claim 21 recite substantially the same limitation and are rejected for the same reason.
Claim 12 line 1 recites “the combined modulo k value”. This limitation lacks antecedent basis. It is unclear which combined modulo k value of the one or more combined modulo k values recited in claim 1 this refers to. For purposes of examination, Examiner interprets as each of the plurality of combined modulo k values.
Claim 16 recites “the output”. This limitation lacks antecedent basis. It is unclear whether this refers to the output modulo k value or the intermediate reduced plurality of modulo k values output as in claim 1, or other. For purposes of examination, Examiner interprets as “the output modulo k value”.
The claim 5 limitation a “plurality of combination units” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Claim 6 inherits the same deficiency as claim 6 based on dependence. As to the “plurality of combination units”, for the embodiment wherein the plurality of combination units operating on binary representation data, the specification and drawings discloses the connections between each combination unit as arranged, but does not disclose the structure, material or acts of the combination unit itself. See figure 2 device 42N, 44N, 46A, figure 3 device 52, 54N, figure 4 device 72Bm 74Bm 76Am 78A and associated description of the drawings in the specification, which disclose the plurality of combination units as a black box. Furthermore, with respect to the plurality of combination units operating on binary representation data, the specification discloses the combination units can be provided as a simple circuit that does not require a full adder or a full divider circuit, or in terms of an equation, but without disclosing the structure of the circuit beyond the function performed. See p. 8, p. 16-17.
Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, and 18-21 are rejected under 35 U.S.C. 102(a)(1)/35 U.S.C. 102(a)(2) as being anticipated by US 20110145311 A1 (hereinafter “JIn”).
Regarding claim 1, teaches Jin the following:
input data value analysis circuitry configured to consider an input data value as a plurality of partial operands, and to determine a plurality of modulo k values comprising a modulo k value derived from each of the plurality of partial operands (fig 3A, [0043-0044] input X which is 435 expressed as a binary number 110110011 for input data value, four groupings of three bits input to four first mod3 devices and one bit b0 for a plurality of partial operands, first four mod3 devices for determine a plurality of modulo k values, outputs of first four mod3 devices for a modulo k value derived from each of the plurality of partial operands); and
modulo k calculation circuitry comprising a plurality of combination stages, each combination stage arranged to replace one or more groups of input modulo k values with one or more combined modulo k values, each combined modulo k value providing a modulo k value derived from a sum of an associated group of input modulo k values, thereby generating a reduced plurality of modulo k values (fig 3 A, [0044] adder/mod3 stages following initial 4 mod3 devices for modulo k calculation circuitry comprising a plurality of combination stage, each adder/mod3 grouping for arranged to replace one or more groups of input modulo k values with one or more combined modulo k values, with adder for sum of an associated group of input modulo k values, each mod3 device output generating a reduced modulo k value),
wherein the plurality of combination stages comprises a first combination stage configured to receive the plurality of modulo k values as inputs and to output an intermediate reduced plurality of modulo k values (fig 3A, [0044], two adder/mod3 devices following the initial mod3 devices), and one or more further combination stages arranged to sequentially combine one or more groups of the intermediate reduced plurality of modulo k values to generate an output modulo k value of the input data value (fig 3A, [0044] remaining adder mod3 device for further combination stage, and output 011 for output modulo k value).
Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis, Jin teaches the following:
wherein: each of the one or more groups of input modulo k values is a pair of modulo k values (Fig 3A pair of input modulo k values input to upper first adder, and pair of input module k values input to lower first adder); and
each of the one or more groups of the intermediate reduced plurality of modulo k values is a pair of intermediate reduced modulo k values (fig 3A outputs of upper first add and lower first adder is a pair of mod3 values, for pair of intermediate reduced modulo k values).
Regarding claim 3, in addition to the teachings addressed in the claim 1 analysis, Jin teaches the following:
wherein each of the plurality of combination stages is arranged to replace a single group of the input modulo k values with a single combined modulo k value (fig 3A each adder, mod3 device replaces a group (pair) of input mod 3 values with a single mod 3 value).
Regarding claim 4, in addition to the teachings addressed in the claim 3 analysis, Jin teaches the following:
wherein: in the first combination stage, the single group of the input modulo k values is a single group of the plurality of modulo k values (fig 3A initial mod3 device out is the plurality of modulo k values as in the claim 1 mapping, which is the same as the single group of the input modulo k values as in the claim 3 mapping); and
in each of the one or more further combination stages the single group of the input modulo k values comprises at least one of the plurality of modulo k values and the combined modulo k value output from a preceding combination stage of the plurality of combination stages (fig 3A, the final output stage with inputs b0, b1, for b0 comprises at least one of the plurality of modulo k values, and the last adder/mod3 stages for comprising an output from a preceding combination stage).
Regarding claim 5, in addition to the teachings addressed in the claim 1 analysis, Jin teaches the following:
wherein each of the plurality of combination stages comprises a plurality of combination units, each combination unit arranged to replace a different group of the one or more groups of input modulo k values with the combined modulo k value of the sum of that group of input modulo k values (fig 3A plurality of adders for plurality of combination units).
Regarding claim 6, in addition to the teachings addressed in the claim 5 analysis, Jin teaches the following:
wherein: the plurality of modulo k values comprises 2N modulo k values ([0043], fig 3A, input to first mod3 devices comprises four (22) mod3 values);
the first combination stage comprises 2N-1 combination units arranged to output the intermediate reduced plurality of modulo k values comprising 2N-1 intermediate modulo k values (fig 3A, output of first upper and lower add/mod3 comprises 2 (21) intermediate modulo k values); and
a number of combination units in each of the one or more further combination stages is half of a number of combination units in a preceding combination stage (fig 3A, output of second add/mod3 comprises 1 add/mod3 (2/2)).
Regarding claim 7, in addition to the teachings addressed in the claim 1 analysis, Jin teaches the following:
wherein a sum of the plurality of partial operands is equal to the input data value ([0037], eqn 4).
Regarding claim 8, in addition to the teachings addressed in the claim 1 analysis, Jin teaches the following:
wherein each of the plurality of partial operands can be represented as a power of two ([0043], fig 3A inputs to first mod3 devices shown as a power of two representation).
Regarding claim 18, in addition to the teachings addressed in the claim 1 analysis, Jin teaches the following:
wherein k is a number other than a power of two ([0044], k = 3).
Regarding claim 19, in addition to the teachings addressed in the claim 1 analysis, Jin teaches the following:
wherein k equals three ([0044], k = 3).
Claim 20 is directed to a method that would be practiced by the apparatus of claim 1 as configured. All steps recited in claim 20 are practiced by the apparatus of claim 1 as configured. The claim 1 analysis applies equally to claim 20.
Claim 21 is directed to a non-transitory computer-readable medium to store computer-readable code for fabrication of the apparatus as in claim 1. All steps practiced by the computer-readable medium as in claim 21 are practiced by the apparatus of claim 1 as configured. The claim 1 analysis applies equally to claim 21.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of J.R. Diamond, et al., Arbitrary Modulus Indexing, 2014 47th IEEE/ACM International Symposium on Microarchitecture, IEEE Computer Society, 2014 (hereinafter “Diamond”).
Regarding claim 16, Jin further discloses application of modulo operations in the cellular technologies ([0005-0006]), but is silent with respect to using an output of a modulo operation for a chip enable signal for a memory device. However in the same field of endeavor, Diamond discloses various algorithms for the modulo operation (section II.C, section III). Diamond further discloses:
wherein the output is used for a chip enable signal for a memory device consisting of k banks (Introduction, section III, Arbitrary Modulus Indexing (AMI) of RAM for a chip enable signal for a memory device, fig 2b showing k banks).
It would have been obvious to one of ordinary skill in the art before the effective filing date to use Jin’s output of the modulo operation as a chip enable signal for a memory device consisting of k banks as disclosed by Diamond to achieve the benefit of memory access at a rate that is well matched to computation rates (Introduction).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of US 20200065066 A1 Kallen et al., (hereinafter “Kallen”).
Regarding claim 17, Jin further discloses specific modulo operation schemes, such as modulo 3, modulo 6, modulo 12, modulo 30, modulo 31 and modulo 65537, which are used in the 3GPP LTE standard, and modulo operation for efficient techniques ([0006]). Jin further discloses input data values, the plurality of modulo k values corresponding to one of the plurality of partial operands directly connected into input data value analysis circuitry (fig 3A). Jin does not, however, explicitly disclose that these connections are hardwired. However, in the same field of endeavor Kallen discloses connections between modulo units and the inputs as hardwired ([0082]). It would have been obvious to one of ordinary skill in the art before the effective filing date for Jin’s connections to be hardwired wherein the input data value analysis circuitry is configured such that a dependency of each of the plurality of modulo k values on a corresponding one of the plurality of partial operands is hardwired into the input data value analysis circuitry. It would have been obvious to achieve the benefit of configuring known parameters at design time such that the circuitry can be optimized to perform the modulo operation (Kallen [0082]).
Allowable Subject Matter
Claims 9-15 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and rewritten to overcome the rejection under 35 USC 112(b).
The following is a statement of reasons for the indication of allowable subject matter.
Applicant claims apparatus related to modulo k calculation, wherein the apparatus as in claim 1 comprises:
input data value analysis circuitry configured to consider an input data value as a plurality of partial operands, and to determine a plurality of modulo k values comprising a modulo k value derived from each of the plurality of partial operands; and
modulo k calculation circuitry comprising a plurality of combination stages, each combination stage arranged to replace one or more groups of input modulo k values with one or more combined modulo k values, each combined modulo k value providing a modulo k value derived from a sum of an associated group of input modulo k values, thereby generating a reduced plurality of modulo k values,
wherein the plurality of combination stages comprises a first combination stage configured to receive the plurality of modulo k values as inputs and to output an intermediate reduced plurality of modulo k values (fig 3A, [0044], two adder/mod3 devices following the initial mod3 devices), and one or more further combination stages arranged to sequentially combine one or more groups of the intermediate reduced plurality of modulo k values to generate an output modulo k value of the input data value.
Wherein the apparatus as in claim 1 further comprises as in claim 9:
wherein at least one of the plurality of modulo k values is encoded using a k-bit one-hot representation.
The primary reason for indication of allowable subject matter is the above highlighted limitations in combination with the remaining limitations.
Jin is the closest prior art found. Jin discloses an apparatus for a modulo N operation as in the above claim mappings. Jin further discloses converting a positive integer X into a binary number prior to performing the modulo N operation (abstract). Jin is silent with respect to converting a positive integer X into a one-hot encoded representation, and therefore does not teach or suggest the above highlighted limitations.
US 20180121166 A1 Rose (hereinafter “Rose”) discloses a binary logic circuit configured to generate a modulo operation for calculating mod(2n+-1) (abstract, fig 1, fig 1). Rose further discloses one-hot modulo encoding, and a binary logic circuit configured to operate using such one-hot encodings ([0121-0123], fig 5, fig 8). However, no motivation to combine the Rose one-hot coding apparatus with Jin could be determined, based on the representative structures of Jin versus Rose disclosed.
P. Athira et al., Modular Adder Designs Based On Thermometer Coding and One-Hot Coding, 2021 2nd International Conference on Advances in Computing, Communication, Embedded and Secure Systems (ACCESS) 2021 (hereinafter “Athira”), discloses modular adders based on one hot code residue (abstract, section III.C., IV.B, fig 5, fig 7, fig 8). Athira further discloses converting from binary to one-hot code representation (fig 1, Section II.A). However, no motivation to combine the Athira’s one-hot coding apparatus with Jin could be determined, based on the representative structures of Jin versus Athira disclosed.
F. Jafarzadehpour et al., Efficient Modular Adder Designs Based on Thermometer and One-hot Coding, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 9, 2019 (hereinafter “Jafarzadehpour”) discloses a one-hot coding adder design (abstract, introduction, Table II, fig 2, fig 6). However, no motivation to combine the Jafarzadehpour one-hot coding apparatus with Jin could be determined, based on the representative structures of Jin versus Jafarzadehpour disclosed.
Conclusion
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/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182