Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments to the claims filed on 12/19/2025 are acknowledged and entered. According to the Amendments to the claims, claims 4, 11, 18 and 20 has /have been amended. Accordingly, claims 1-20 are pending in the application. An action on the merits for claims 1-20 are as follow.
The previous 112 (b) Claim Rejections are withdrawn in accordance with applicant's amendment to the claims with no new matter added.
Claim Interpretations - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term "means" or "step" or a term used as a substitute for "means" that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term "means" or "step" or the generic placeholder is modified by functional language, typically, but not always linked by the transition word "for" (e.g., "means for") or another linking word or phrase, such as "configured to" or "so that"; and
(C) the term "means" or "step" or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word "means" (or "step") in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word "means" (or "step") in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre- AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word "means" (or "step") are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word "means" (or "step") are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim limitation “a first switching device” and “a second switching device” has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder “device” coupled with functional language “switching” and without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier.
Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claim 2 has/have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof. A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation: Under Spec. [0030], Fig 2, the switching device 54 of either or both of the first and second switching circuits 34, 36 may be a transistor (e.g., a first transistor Q1 and a second transistor Q2).
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Fattorini et al. (US 9,788,368 B2).
Regarding Independent Claim 1, Fattorini et al. disclose a heating assembly for a cooking appliance (See title) comprising:
at least one induction coil (an induction coil L, Fig 1);
a drive circuit (see Fig 1) configured to control a coil current (an induction coil current IL, Fig 2) through the at least one induction coil, the drive circuit including a first switching circuit (a first transistor S1, capacitor C1, Col 3 line 1-7, Fig 1) operable to conduct the coil current during a first conducting period and a second switching circuit (a second transistor S2, capacitor C2, Col 3 line 1-7, Fig 1) operable to conduct the coil current during a second conducting period different than the first conducting period (One terminal of the induction coil L is connected to the connecting point between the first transistor S1 and the second transistor S2, Col 3 line 30-32, Fig 1);
a sensing circuit (a zero cross detector 20, Col 3 line 5, Fig 1) configured to detect a polarity of the coil current; and
a control circuit (control circuit block comprises a gate drive circuit 14, a microcontroller 16, a power control circuit 18, and a detection circuit 22, Col 3 line 3-5, Fig 1) in communication with the drive circuit and the sensing circuit (see Fig 1), the control circuit configured to:
communicate a first activation signal to the first switching circuit during a first activation period (Two outputs of the gate drive circuit 14 are connected to the control electrodes of the first transistor S1 and the second transistor S2, respectively, Col 3 line 43-45);
communicate a second activation signal to the second switching circuit during a second activation period (Two outputs of the gate drive circuit 14 are connected to the control electrodes of the first transistor S1 and the second transistor S2, respectively, Col 3 line 43-45); and
control a delay (phase angle delay is determined by calculating an intersection of the induction coil current IL at zero, Col 4 line 54-55) between the first activation signal and the second activation signal based on the polarity of the coil current (the control circuit block is provided for estimating a phase angle delay between switching one semiconductor switch and the subsequent zero crossing of an induction coil current, Col 1 line 64-37; phase angle delay is the time delay between switching off one transistor S1 or S2 until the current in the induction coil L is zero, Col 4 line 40-42).
Claim 2, wherein the control circuit is configured to communicate the first activation signal to a first switching device (a first transistor S1, Fig 1) of the first switching circuit and the second activation signal to a second switching device (a second transistor S2, Fig 1) of the second switching circuit.
Claim 3, wherein the first activation signal corresponds to a high state of a first pulse-width modulation (PWM) signal (see the first activation signal corresponds to a high state of VG1 in Fig 2) and the second activation signal corresponds to a high state of a second PWM signal (see the second activation signal corresponds to a high state of VG2 in Fig 2).
Claim 4, wherein the control circuit is further configured to adjust a timing of a rising edge of the second PWM signal to control the delay (see adjust a timing of a rising edge of VG2 to control the delay 28 in Fig 2).
Claim 5, wherein the control circuit is further configured to adjust a timing of a falling edge of the first PWM signal to control the delay (see adjust a timing of a falling edge of VG1 to control the delay 28 in Fig 2).
Claim 6, wherein the control circuit is further configured to:
calculate an interval between a falling edge of the first activation signal and a change in the polarity (phase angle delay is determined by calculating an intersection of the induction coil current IL at zero, Col 4 line 54-55; an interval between a falling edge of S1 and a change in the polarity of IS in Fig 2); and
adjust the second activation signal based on the change in the polarity (voltage across the shunt element SE is applied… only positive values are amplified by the operational amplifier 30, Col 4 line 6-20, Figs 2 and 4).
Claim 7, wherein the first and second activation signals correspond to pulse-width modulation (PWM) signals having a plurality of cycles each defined by a pair of sequential first and second activation signals (see a plurality of cycles each defined by a pair of sequential first and second activation signals in Fig 2).
Claim 8, wherein the control of the delay is based further on the interval of one or more of the plurality of cycles (parameters can be achieved by the value of the phase angle delay between the output of the induction heating generator and the zero crossing of the induction coil current IL, Col 4 line 25-28, see Fig 2).
Claim 9, wherein the control circuit is further configured to:
estimate a polarity transition time of the coil current (the control circuit block is provided for estimating a phase angle delay between switching one semiconductor switch and the subsequent zero crossing of an induction coil current., Col 1 line 64-67, see induction coil current IL in Fig 2) based on the interval of the one or more of the plurality of cycles (see Fig 2); and
adjust a rising edge of the second activation signal to be temporally proximate to the polarity transition time (adjust a rising edge of VG2 to be temporally proximate to the polarity transition time, Figs 2 and 5-9).
Claim 10, further comprising: a first diode and a second diode (a first diode D1, a second diode D2, Col 3 line 1, Fig 1), wherein the first diode is configured to conduct the coil current following deactivation of the second switching device and the second diode is configured to conduct the coil current following deactivation of the first switching device (two diodes (Dl, D2) are connected in each case parallel to one of the semiconductor switches (S1, S2), Col 7 line 8-10, Fig 1).
Claim 11, disclose wherein the control circuit is further configured to:
determine that the coil current is being conducted via the second diode based on the polarity of the coil current and deactivation of the first switching device (the phase angle delay is estimated on the basis of an intersection line of the induction coil current with a zero value, Col 2 line 7-9, see Figs 1-2); and
activate the second switching device in response to the second diode not conducting the coil current following deactivation of the first switching device (the control circuit block is provided for estimating a phase angle delay between switching one semiconductor switch and the subsequent zero crossing of an induction coil current, Col 1 line 64-67).
Claim 12, wherein the first diode is in parallel with the first switching device and the second diode is in parallel with the second switching device (details see Fig 1).
Claim 13, wherein the control circuit is further configured to:
measure a diode time between deactivation of the second switching device and the first diode no longer conducting the coil current (phase angle delay is the time delay between switching off one transistor S1 or S2 until the current in the induction coil L is zero, Col 4 line 40-42, Figs 1-2);
calculate a ratio of the diode time to the second activation time (The phase angle delay can be derived by a combination of features of the AD converter in the microcontroller 16 and a software algorithm, Col 4 line 28-30); and
postpone an activation of the first switching device based on the ratio of the diode time to the second activation time (output signals I1 and 12 of the detection circuit 22 are filtered and transferred to the AD converter input of the microcontroller 16, Col 4 line 21-23).
Claim 14, wherein the control circuit is further configured to postpone the activation of the first switching device when the ratio corresponds to the diode time being at least 5% of the second activation time (The phase angle delay can be derived by a combination of features of the AD converter in the microcontroller 16 and a software algorithm, Col 4 line 28-30; Clearly, “the control circuit is” capable of “postpone the activation of the first switching device when the ratio corresponds to the diode time being at least 5% of the second activation time” as claimed).
Regarding Independent Claim 15, Fattorini et al. disclose a method for controlling at least one induction coil (an induction coil current IL, Fig 2) of a heating assembly for a cooking appliance (See title), comprising:
controlling a drive current (control circuit block comprises a gate drive circuit 14, a microcontroller 16, a power control circuit 18, and a detection circuit 22, Col 3 line 3-5, Fig 1) through the at least one induction coil (an induction coil current IL, Fig 2) via a drive circuit, the drive circuit including a first switching circuit (a first transistor S1, a first diode D1, capacitor C1, Col 3 line 1-7, Fig 1) operable to conduct the coil current during a first conducting period and a second switching circuit (a second transistor S2, a second diode D2, capacitor C2, Col 3 line 1-7, Fig 1) operable to conduct the coil current during a second conducting period different than the first conducting period (One terminal of the induction coil L is connected to the connecting point between the first transistor S1 and the second transistor S2, Col 3 line 30-32, Fig 1);
monitoring a polarity of the coil current via a sensing circuit (a zero cross detector 20, Col 3 line 5, Fig 1);
communicating a first activation signal to the first switching circuit during a first activation period (Two outputs of the gate drive circuit 14 are connected to the control electrodes of the first transistor S1 and the second transistor S2, respectively, Col 3 line 43-45);
communicating a second activation signal to the second switching circuit during a second activation period (Two outputs of the gate drive circuit 14 are connected to the control electrodes of the first transistor S1 and the second transistor S2, respectively, Col 3 line 43-45); and
controlling a delay (phase angle delay is determined by calculating an intersection of the induction coil current IL at zero, Col 4 line 54-55) between the first activation signal and the second activation signal based on the polarity of the coil current (the control circuit block is provided for estimating a phase angle delay between switching one semiconductor switch and the subsequent zero crossing of an induction coil current, Col 1 line 64-37; phase angle delay is the time delay between switching off one transistor S1 or S2 until the current in the induction coil L is zero, Col 4 line 40-42, Fig 2).
Claim 16, further comprising:
calculating an interval between a falling edge of the first activation signal and a change in the polarity (phase angle delay is determined by calculating an intersection of the induction coil current IL at zero, Col 4 line 54-55; an interval between a falling edge of S1 and a change in the polarity of IS in Fig 2); and
adjusting the second activation signal based on the change in the polarity (voltage across the shunt element SE is applied… only positive values are amplified by the operational amplifier 30, Col 4 line 6-20, Figs 2 and 4).
Claim 17, wherein the first and second activation signals correspond to pulse-width modulation (PWM) signals having a plurality of cycles each defined by a pair of sequential first and second activation signals (see a plurality of cycles each defined by a pair of sequential first and second activation signals in Fig 2).
Claim 18, wherein the step of controlling the delay is based further on the interval of one or more of the plurality of cycles (parameters can be achieved by the value of the phase angle delay between the output of the induction heating generator and the zero crossing of the induction coil current IL, Col 4 line 25-28, see Fig 2).
Claim 19, comprising:
estimating a polarity transition time of the coil current (the control circuit block is provided for estimating a phase angle delay between switching one semiconductor switch and the subsequent zero crossing of an induction coil current., Col 1 line 64-67, see induction coil current IL in Fig 2) based on the interval of the one or more of the plurality of cycles (see Fig 2); and
adjusting a rising edge of the second activation signal to be temporally proximate to the polarity transition time (adjust a rising edge of VG2 to be temporally proximate to the polarity transition time, Figs 2 and 5-9).
Regarding Independent Claim 20, Fattorini et al. disclose a heating assembly for a cooking appliance (See title) comprising:
at least one induction coil (an induction coil L, Fig 1);
a first switch (a first transistor S1, Col 2 line 67, Fig 1) and a second switch (a second transistor S2, Col 3 line 1, Fig 1) configured to control a coil current (an induction coil current IL, Fig 2) through the at least one induction coil in alternation (see Fig 1);
a first diode (a first diode D1, Col 3 line 1, Fig 1) in antiparallel with the first switch (D1 in antiparallel with S1, Fig 1);
a second diode (a second diode D2, Col 3 line 1, Fig 1) in antiparallel with the second switch (D2 in antiparallel with S2, Fig 1); and
a control circuit (control circuit block comprises a gate drive circuit 14, a microcontroller 16, a power control circuit 18, and a detection circuit 22, Col 3 line 3-5, Fig 1) in communication with the first and second switches (see Fig 1), the control circuit configured to:
activate the first switch for a first duration;
deactivate the first switch at a first time to end the first duration (Two outputs of the gate drive circuit 14 are connected to the control electrodes of the first transistor S1 and the second transistor S2, respectively, Col 3 line 43-45);
activate the second switch at a second time later than the first time for a second duration (Two outputs of the gate drive circuit 14 are connected to the control electrodes of the first transistor S1 and the second transistor S2, respectively, Col 3 line 43-45); and
control a delay (phase angle delay is determined by calculating an intersection of the induction coil current IL at zero, Col 4 line 54-55) between the first time and the second time, wherein the second time corresponds to an end of a period during which the coil current flows through the second diode following deactivation of the first switch (two diodes (Dl, D2) are connected in each case parallel to one of the semiconductor switches (S1, S2), Col 7 line 8-10, Fig 1).
Response to Arguments
Applicant’s arguments filed 12/19/2025 have been fully considered but they are not persuasive. The same prior art used under the Non-Final Rejection been able to cover all the limitations of the amended claims.
The applicant's argument on Remarks, namely “Applicant submits that
Fattorini et al. fails to disclose "control a delay between the first activation signal and the second activation signal based on the polarity of the coil current" as recited by independent claims 1, 15, and 20”, “Claim 1's "control a delay between the first activation signal and the second activation signal based on the polarity of the coil current" involves dynamic adjustment of switching timing to reduce activation time of active circuitry and improve efficiency. As described in the specification, "[t]he improved efficiency of the system may be provided by deactivating an active supply current to the induction coil or load over a delay period." As-Filed Specification, paragraph [0021]. This active control based on coil current polarity enables the system to identify a period of time in which electrical energy is being wasted and/or unnecessarily converted to thermal energy and control a timing of an activation signal for the drive circuit to improve thermal and/or electrical efficiency of the inverter circuit. As-Filed Specification, paragraphs [0038]-[0039]”, and “Independent claim 15 recites "controlling a delay between the first activation signal and the second activation signal based on the polarity of the coil current." For the same reasons as stated above with respect to claim 1, Applicant submits that Fattorini does not teach or suggest using coil current polarity information to dynamically adjust the delay between activation signals. Thus claim 15 is allowable over Fattorini. Claims 16-19 depend from claim 15 and are allowable for the same reasons as claim 15. Independent claim 20 recites "control a delay between the first time and the second time, wherein the second time corresponds to an end of a period during which the coil current flows through the second diode following deactivation of the first switch." Again, merely estimating a phase angle delay is not the same as actively controlling a delay. Thus, claim 20 is also allowable over Fattorini”.
The examiner’s response: Fattorini et al. disclose exactly a control circuit (control circuit block comprises a gate drive circuit 14, a microcontroller 16, a power control circuit 18, and a detection circuit 22, Col 3 line 3-5, Fig 1) and control a delay (phase angle delay is determined by calculating an intersection of the induction coil current IL at zero, Col 4 line 54-55) between the first activation signal and the second activation signal based on the polarity of the coil current (the control circuit block is provided for estimating a phase angle delay between switching one semiconductor switch and the subsequent zero crossing of an induction coil current, Col 1 line 64-37; phase angle delay is the time delay between switching off one transistor S1 or S2 until the current in the induction coil L is zero, Col 4 line 40-42) as claimed under claim 1; controlling a delay (phase angle delay is determined by calculating an intersection of the induction coil current IL at zero, Col 4 line 54-55) between the first activation signal and the second activation signal based on the polarity of the coil current (the control circuit block is provided for estimating a phase angle delay between switching one semiconductor switch and the subsequent zero crossing of an induction coil current, Col 1 line 64-37; phase angle delay is the time delay between switching off one transistor S1 or S2 until the current in the induction coil L is zero, Col 4 line 40-42, Fig 2) as claimed under claim 15; and control a delay (phase angle delay is determined by calculating an intersection of the induction coil current IL at zero, Col 4 line 54-55) between the first time and the second time, wherein the second time corresponds to an end of a period during which the coil current flows through the second diode following deactivation of the first switch (two diodes (Dl, D2) are connected in each case parallel to one of the semiconductor switches (S1, S2), Col 7 line 8-10, Fig 1) as claimed under claim 20 respectively shown above in this office action. One must know, limitations from the specification are not read into the claims; although a claim should be interpreted in light of the specification disclosure, it is generally considered improper to read limitations contained in the specification into the claims. See In re Prater, 415 F.2d 1393, 162 USPQ 541 (CCPA 1969) and In re Winkhaus, 527 F.2d 637, 188 USPQ 129 (CCPA 1975), which discuss the premise that one cannot rely on the specification to impart limitations to the claim that are not recited in the claim (MPEP 2173.05(q)). During “examination, a claim must be given its broadest reasonable interpretation consistent with the specification as it would be interpreted by one of ordinary skill in the art. Because the applicant has the opportunity to amend claims during prosecution, giving a claim its broadest reasonable interpretation will reduce the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989)”. “Under a broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. The plain meaning of a term means the ordinary and customary meaning given to the term by those of ordinary skill in the art at the time of the invention” (MPEP 2173.01(I)). Therefore, the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is advised to refer to the Notice of References Cited for pertinent prior art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KUANGYUE CHEN whose telephone number is 571/272-8224. The examiner can normally be reached on M-F 9:00-5:00 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, supervisor Ibrahime Abraham can be reached on 571/270-5569, supervisor Kosanovic Helena can be reached on 571/272-9059, supervisor Steven Crabb can be reached on 571/270-5095, or supervisor Edward Landrum can be reached on 571/272-5567. The fax phone number for the organization where this application or proceeding is assigned is 571/273-8300.
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/KUANGYUE CHEN/
Examiner, Art Unit 3761
/EDWARD F LANDRUM/Supervisory Patent Examiner, Art Unit 3761