DETAILED ACTION
This office action is in response to claims filed 13 January 2026.
Claims 1-8 and 10 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see the remarks filed 13 January 2026, with respect to the claim objections and rejections under 35 U.S.C. 112b, and 35 U.S.C. 101 have been fully considered and are persuasive. The objections and rejections have been withdrawn.
Applicant’s arguments, see the remarks filed 13 January 2026, with respect to the claim objections and rejections under 35 U.S.C. 102 have been fully considered but are not persuasive.
On page 12 of the remarks, the applicant argues:
“First, referring to paragraph [0050] of HERRERO ABELLANAS, HERRERO ABELLANAS only loads ‘input image pixels’ and does not include the loading of weights. Furthermore, paragraph [0037] of HERRERO ABELLANAS explicitly states that latches are used to store input pixel values. However, the S2 in the currently presented claim 1 loads ‘convolution kernels’ (i.e., weight parameters). Therefore, HERRERO ABELLANAS does not teach S2 in the currently presented claim 1. HERRERO ABELLANAS fails to teach the feature ‘S2: sequentially loading a group of convolution kernels into corresponding convolution kernel cache sub-blocks in a first convolution kernel cache’ as recited in the currently presented claim 1.
The examiner respectfully disagrees. The limitation upon which the applicant’s argument relies, namely that S2 of the claim requires “loading of weights…loads ‘convolution kernels’ (i.e., weight parameters)” (emphasis added), is not present in the currently presented claim 1. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims (MPEP 2111.01(II)). Specifically, claim 1 does not describe a convolution kernel as comprising “weights” of any kind, and does not require that a “weight” be loaded, or that in loading a convolution kernel, weight parameters are also loaded, as alleged in the applicant’s argument. At best, claim 1 describes a “convolution kernel cache” that stores an “effective weight” (line 45), however, this does not require that a convolution kernel itself comprise the effective weight, nor does it require that the effective weight by loaded in S2. Further, a review of the specification has failed to uncover any detail or recitation supporting the applicant’s argument requiring that “weight parameters” be loaded in S2. Since the applicant’s arguments are directed to limitations that are not contained within the claims, the applicant’s argument is not persuasive.
On pages 12-14 of the remarks, the applicant argues:
“Moreover, the Examiner considered that the looping operation (repeating blocks 930/940) in paragraph [0054] of HERRERO ABELLANAS…However, the paragraph [0054] of HERRERO ABELLANAS describes a looping pooling operation, or sliding input window. The paragraph [0121] of HERRERO ABELLANAS only discloses that the convolution filter can be provided by a rectangular matrix of pre-defined binary values, HERRERO ABELLANAS does not reveal, nor was there any incentive, to load new convolution kernels during convolution computation. Therefore, HERRERO ABELLANAS does not teach S3, S31, S32, S33, S34, and S35 in the currently presented claim 1…”
The examiner respectfully disagrees. As defined in the previously cited “Types of Convolution Kernels: Simplified”, groups of convolution kernels are represented by a convolution filter, which, along with input data, is stored and operated on, thereby requiring a load of the convolution filter and input. The input data is shifted relatively to its initial position and the steps of storing and operating on the filter and input data are repeated. Since the shifted input represents “new” input, the repeated operation is interpreted to represent, or at least requiring loading of a “new” group of convolution kernels. Or, alternatively, each loop of the pooling operation that requires loading of convolution filter and input, regardless of whether that sliding input represents “new” input, would represent loading of a “new” or “next” group of convolution filters. Therefore, the cited portion of HERRERO ABELLANAS teaches this limitation, and the applicant’s argument is not persuasive.
On page 14 of the remarks, the applicant argues:
“HERRERO ABELLANAS refers to the end of a single convolutional computational process. Therefore, HERRERO ABELLANAS fails to teach the feature ‘S5: determining that all convolution computation is completed”.
The examiner respectfully disagrees. As an initial matter, it is unclear as to how HERRERO ABELLANAS’s teaching of a single convolutional computational process precludes it from also determining that convolutional computation is completed, as once the single convolutional computational process completes, it also means that all convolutional computation is completed. Further, HERRERO ABELLANAS describes a convolutional computational process that comprises a looping operation that repeatedly executes convolutional computations on sliding windows of input. As such, plural convolutional computations are performed, and once the entirety of the input has been processed it is determined that all convolutional computations have been completed. In this way, HERRERO ABELLANAS teaches the limitation at issue, and the applicant’s arguments are not persuasive.
Allowable Subject Matter
Claim 10 is allowed.
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “parallel device for convolution computation” in claim 10.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof, described in [0037] as comprising at least hardware “chip” that implements the parallel device using an “accelerator” (i.e., GPU) and kernel cache, interpreted as memory.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Examiner’s Note Regarding Contingent Limitations in Method Claims
Claims 1, 2, 3, and 6 are method claims that comprise contingent limitations. For example, Claim 1 recites:
i. “under the condition that a current instruction is an input feature map loading instruction”
ii. “under the condition that the current instruction is a convolution kernel loading instruction”
iii. “under the condition that the total number of the convolution kernels is greater than a latch value of the number of the loaded convolution kernels and is an integer multiple, greater than 1 multiple, of the number of the loaded convolution kernels in a convolution computation instruction”
iv. “under the condition that the total number of the convolution kernels is greater than the latch value of the number of the loaded convolution kernels and is 1 multiple of the number of the loaded convolution kernels in the convolution computation instruction”
v. “under the condition that the total number of the convolution kernels is equal to the latch value of the number of the loaded convolution kernels in the convolution computation instruction, determining whether to load convolution kernels in the next layer according to setting in the convolution computation instruction”
The MPEP states: “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B” (MPEP 2111.04(II)).
Since the examiner has interpreted these limitations to comprise contingent limitations. none of the resultant steps are required by the broadest reasonable interpretation of the claim. For examination purposes, the examiner has examined these limitations as if they were not required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by HERRERO ABELLANAS et al. Pub. No.: US 2015/0178246 A1 (hereafter HERRERO ABELLANAS).
Regarding claim 1, HERRERO ABELLANAS teaches:
A parallel method for convolution computation ( [0049] FIG. 9 depicts a flow diagram of an example method for performing convolution operations…Two or more functions, routines, subroutines, or operations of method 900 may be performed in parallel (i.e., parallel method for performing convolution operation “computation”)) and data loading ([0050] At block 910, the processing device implementing method 900 may set an initial position of an input window in a two-dimensional array of input data elements (i.e., input data elements are “loaded”)) of a neural network accelerator ([0064] The elements of system 100 (e.g. graphics accelerator 112)), comprising:
S1: storing a frame of input feature maps into an input feature map cache, and dispersedly storing the input feature maps into input feature map sub-caches according to channels of the input feature maps ([0050] At block 910, the processing device implementing method 900 may set an initial position of an input window in a two-dimensional array of input data elements (i.e., input data elements represent a “feature map” that is stored across multiple elements, or “sub-caches” of the two-dimensional array));
S2: sequentially loading a group of convolution kernels into corresponding convolution kernel cache sub-blocks in a first convolution kernel cache; S3, loading the input feature map cache and the first convolution kernel cache to execute convolution computation ([0051] At block 920, the processing device may applying a convolution filter. [0052] At block 930, the processing device may shift the input window, relatively to its initial position, by one or more positions along the first one-dimensional section of the two-dimensional array (e.g., one or more rows down relatively to the initial position). (i.e., a convolution filter is a matrix used to obtain output data from an image, which is representative of “group of convolution kernels” as discussed in “Types of Convolution Kernels: Simplified”. Available at https://towardsdatascience.com/types-of-convolution-kernels-simplified-f040cb307c37/. Available on 18 October 2019.) to a plurality of input data elements referenced by the input window, as described in more details herein above.), putting a result into an output feature map cache ([0021] Results of the filter operations 108 may be summed together to provide an output from the convolution layer 102 to the next pooling layer 104), and storing a next group of convolution kernels into corresponding convolution kernel cache sub-blocks in a second convolution kernel cache ([0054] The operations referenced by blocks 930 and 940 may be repeated several times, depending on the chosen pooling sample size. The number of iterations may be equal to the pooling sample dimension reduced by one, e.g., for 3×3 pooling the operations referenced by blocks 930 and 940 will be repeated twice, for 4×4 pooling the operations referenced by blocks 930 and 940 will be repeated three times, etc (i.e., convolution filter and input data are repeatedly stored and operated on)), which comprises:
S31: loading an input feature map instruction parameter latch, loading a convolution kernel instruction parameter latch ([0053] The input data elements may be retrieved from a plurality of latches where the input data elements have been stored during the previous processing operation.), and under the condition that a current instruction is an input feature map loading instruction, latching an off-chip input feature map storage address and loading an input feature map length; and latching the number of currently loaded convolution kernels, lengths of the loaded convolution kernels, a convolution kernel cache starting address and an off-chip convolution kernel storage address under the condition that the current instruction is a convolution kernel loading instruction;
S32: comparing the number of the convolution kernels ([0056] At block 960, the processing device may apply the convolution filter to a plurality of input data elements referenced by the input window, as described in more details herein above. As noted herein above, all but one input data elements may be retrieved from a plurality of latches where the input data elements have been stored during the previous processing operation (i.e., the number of latches that the input data is retrieved from, representing “latch value” is determined based on, or “compared to” the convolution filter, representing the number of “convolution kernels”)), and under the condition that the total number of the convolution kernels is greater than a latch value of the number of the loaded convolution kernels and is an integer multiple, greater than 1 multiple, of the number of the loaded convolution kernels in a convolution computation instruction, computing convolution and synchronously loading convolution kernels, the number of channels of the convolution kernels being the number of the loaded convolution kernels; under the condition that the total number of the convolution kernels is greater than the latch value of the number of the loaded convolution kernels and is 1 multiple of the number of the loaded convolution kernels in the convolution computation instruction, computing convolution and synchronously loading convolution kernels, the number of channels of the convolution kernels being a difference value between the total number of the convolution kernels and the latch value of the number of the loaded convolution kernels; and under the condition that the total number of the convolution kernels is equal to the latch value of the number of the loaded convolution kernels in the convolution computation instruction, determining whether to load convolution kernels in the next layer according to setting in the convolution computation instruction; and
S33: setting a loading flag according to a comparison result of the number of the convolution kernels, the loading lag representing that data is specifically loaded into which convolution kernel cache, and setting a convolution computation starting flag;
S34: synchronously carrying out convolution computation and data loading which are independent of each other; and
S35: computing the number of remaining convolution kernels after convolution computation and data loading are completed, latching data loading parameters of the convolution kernels in S34, and returning S32 to continue being executed until convolution computation is completed;
S4: after convolution computation of the layer is completed, interchanging the input feature map cache and the output feature map cache, and using a convolution kernel cache storing an effective weight as the first convolution kernel cache to execute S3; and
S5: determining that all convolution computation is completed (([0051] At block 920, the processing device may applying a convolution filter. [0052] At block 930, the processing device may shift the input window, relatively to its initial position, by one or more positions along the first one-dimensional section of the two-dimensional array (e.g., one or more rows down relatively to the initial position). (i.e., a convolution filter is a matrix used to obtain output data from an image, which is representative of “group of convolution kernels” as discussed in “Types of Convolution Kernels: Simplified”. Available at https://towardsdatascience.com/types-of-convolution-kernels-simplified-f040cb307c37/. Available on 18 October 2019.) to a plurality of input data elements referenced by the input window, as described in more details herein above)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
ZHANG et al. Pub. No.: US 2020/0293379 A1 discloses performing convolutional computations on received input data and pre-stored convolution kernels during clock cycles, and storing convolutional kernels for use in subsequent convolutional computation tasks.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL W AYERS whose telephone number is (571)272-6420. The examiner can normally be reached M-F 8:30-5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee Li can be reached at (571) 272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL W AYERS/Primary Examiner, Art Unit 2195