DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The following guidelines illustrate the preferred layout for the specification of a utility application. These guidelines are suggested for the applicant’s use.
The examiner has highlighted (bold) areas for improvement.
Arrangement of the Specification
As provided in 37 CFR 1.77(b), the specification of a utility application should include the following sections in order. Each of the lettered items should appear in upper case, without underlining or bold type, as a section heading. If no text follows the section heading, the phrase “Not Applicable” should follow the section heading: note, please center the headings.
(a) TITLE OF THE INVENTION. Please correct “QUGATE” ? add title to the first page.
(b) CROSS-REFERENCE TO RELATED APPLICATIONS.
(c) STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT.
(d) THE NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT.
(e) INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A READ-ONLY OPTICAL DISC, AS A TEXT FILE OR AN XML FILE VIA THE PATENT ELECTRONIC SYSTEM.
(f) STATEMENT REGARDING PRIOR DISCLOSURES BY THE INVENTOR OR A JOINT INVENTOR.
(g) BACKGROUND OF THE INVENTION.
(1) Field of the Invention.
(2) Description of Related Art including information disclosed under 37 CFR 1.97 and 1.98.
(h) BRIEF SUMMARY OF THE INVENTION.
(i) BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S). Please note that this should be a brief description that captures the figure.
(j) DETAILED DESCRIPTION OF THE INVENTION.
(k) CLAIM OR CLAIMS (commencing on a separate sheet).
(l) ABSTRACT OF THE DISCLOSURE (commencing on a separate sheet). Please remove title and abstract should be written in single paragraph format.
(m) SEQUENCE LISTING. (See MPEP § 2422.03 and 37 CFR 1.821 - 1.825). A “Sequence Listing” is required on paper if the application discloses a nucleotide or amino acid sequence as defined in 37 CFR 1.821(a) and if the required “Sequence Listing” is not submitted as an electronic document either on read-only optical disc or as a text file via the patent electronic system.
Drawings
The drawings are not of sufficient quality to permit examination. Accordingly, replacement drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to this Office action. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
Applicant is given a shortened statutory period of TWO (2) MONTHS to submit new drawings in compliance with 37 CFR 1.81. Extensions of time may be obtained under the provisions of 37 CFR 1.136(a) but in no case can any extension carry the date for reply to this letter beyond the maximum period of SIX MONTHS set by statute (35 U.S.C. 133). Failure to timely submit replacement drawing sheets will result in ABANDONMENT of the application.
in figure 5, what exactly is being represented? What are the four representations of the hardware(74-77 wave functions?)?…how does this reflect Noise allocation ?
“four repetitions of the hardware shown in FIG. 1 are required to create the universal qubit representation. FIG. 5 reflects this quadrupling of the circuits.”?
Claim Objections
Claims 1-3 are objected to because of the following informalities: the periods in the preamble of all claims should be removed. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, because the claim purports to invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, but fails to recite a combination of elements as required by that statutory provision and thus cannot rely on the specification to provide the structure, material or acts to support the claimed function. As such, the claim recites a function that has no limits and covers every conceivable means for achieving the stated function, while the specification discloses at most only those means known to the inventor(see claim 2, for example). Accordingly, the disclosure is not commensurate with the scope of the claim.
Re claims 1 and 2:
Due to the period “.” In the preamble, the claim is awkwardly written so in effect it is broken/separate and disjointed from the rest of the claim body.
1. A circuit of quantum bit (qubit) for the generation of a random sequence with the ability to change the probability of a superposition of two orthogonal states 10> and |1> and with a controllable noise allocation. The circuit of a qubit is comprised of: a. a linear shift m-bit register generating 2"'-1 numbers; b. a random disturber stopping the linear shift register from advancing at a rate slower than the linear shift register clock; c. an m-bit register for storing a value of the desired probability of the orthogonal states; d. an m-bit register for the setting of the desired level of noise; and e. a multilevel quantizer (arithmetical comparator between the current value of the linear shift register and the value stored in the programmable m-bit register for the probability of states), driving the output of the qubit to the orthogonal states I0> and 11> proportionally to the programmed probability and allocating the desirable noise level according to the setting in the second m-bit register.
2. A circuit for implementing a quantum gate for combining orthogonal states 10> and 11> of the multiple qubits and with an ability to inject random noise. The circuit of the quantum gate is a combination of: a. a classic function gate XOR, OR, AND, etc.; b. a quantum gate noise injection circuit based on the allocation of noise from qubits' settings; c. a random bit generator as a source of the allocated noise for the quantum gate.
3.A combination of the above circuits for implementing a quantum bit and quantum gate with the ability to serve both probability and quantum phase functionality.
What claim is this referencing?
Claim 1-3 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The “allocating the desirable noise level” in claim 1 and the “allocation of noise” in claim 2, see below, cannot be determined, as this “allocation” with regards noise is not made clear in the specification and/or drawings.
1. A circuit of quantum bit (qubit) for the generation of a random sequence with the ability to change the probability of a superposition of two orthogonal states 10> and |1> and with a controllable noise allocation. The circuit of a qubit is comprised of: a. a linear shift m-bit register generating 2"'-1 numbers; b. a random disturber stopping the linear shift register from advancing at a rate slower than the linear shift register clock; c. an m-bit register for storing a value of the desired probability of the orthogonal states; d. an m-bit register for the setting of the desired level of noise; and e. a multilevel quantizer (arithmetical comparator between the current value of the linear shift register and the value stored in the programmable m-bit register for the probability of states), driving the output of the qubit to the orthogonal states I0> and 11> proportionally to the programmed probability and allocating the desirable noise level according to the setting in the second m-bit register.
2. A circuit for implementing a quantum gate for combining orthogonal states 10> and 11> of the multiple qubits and with an ability to inject random noise. The circuit of the quantum gate is a combination of: a. a classic function gate XOR, OR, AND, etc.; b. a quantum gate noise injection circuit based on the allocation of noise from qubits' settings; c. a random bit generator as a source of the allocated noise for the quantum gate.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
Re claims 1 and 2:
Due to the “.” In the preamble and the awkwardly written claim recitations, it is not clear how the elements and functionality of such flow in a manner to determine the metes and bounds of the claims presented.
Re claim 1: what exactly is meant by: 1. A circuit of quantum bit (qubit) for the generation of a random sequence with the ability to change the probability of a superposition of two orthogonal states 10> and |1> and with a controllable noise allocation?
Re claim 2: what exactly is meant by : 2. A circuit for implementing a quantum gate for combining orthogonal states 10> and 11> of the multiple qubits and with an ability to inject random noise?.
Also, “the circuit of the quantum gate is a combination of: a. a classic function gate XOR, OR, AND, etc.;” ? this recitation, as to what elements and how they connect with other elements, to allow for the injection of random noise, is indefinite.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite in that it fails to point out what is included or excluded by the claim language. This claim is an omnibus type claim.
Also, claim 3 does not have a clear line of dependency…which claim does it depend from?
The Examiner will not attempt applying art rejections at this time as the above issues need to be addressed first. An interview is recommended to discuss all of the above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2849