DETAILED ACTION
This action is responsive to communications filed on September 2, 2025. This action is made Non-Final.
Claims 1-7, 11-15, and 32-39 are pending in the case.
Claims 1, 11, and 32 are independent claims.
Claims 11-15 and 32-39 are withdrawn as indicated below.
Claims 1-7 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Claims 11-15 and 32-39 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 2, 2025.
Information Disclosure Statement
The information disclosure statement (IDS(s)) submitted on 05/18/2022, 12/28/2022, 09/11/2025 is/are in compliance with the provisions of 37 C.F.R. 1.97. Accordingly, the IDS(s) is/are being considered by the examiner.
Claim Objections
Claim 3 is objected to and recites the limitation "the neural network". There is insufficient antecedent basis for this limitation in the claim. The Examiner notes that claim 1 introduces “A neuromorphic device.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Papageorgiou et al., US Publication 2022/0028444 (“Papageorgiou”), and further in view of Chang et al., US Patent 10,340,003 (“Chang”).
Claim 1:
Papageorgiou teaches or suggests a neuromorphic device, comprising:
a plurality of cell tiles, each of the plurality of cell tiles including a cell array including a plurality of memory cells configured to store weights of a neural network (see Fig. 6-9, 15-18h, 36-38a; para. 0074 - elements 611, U Ro can be implemented with different components such as resistors (RRAM, PCM), capacitors, transistors or combinations of these. These elements may be used to perform dot products or convolutions of the input signals on the rows 603 with weights determined by values of the elements 611; para. 0085 - FIG. 15 illustrates a block diagram of in-memory compute MAC block. Multiple neurons (columns) are connected adjacently and each outputs the result of a single MAC operation.),
a row driver connected to the plurality of memory cells via a plurality of row lines (see Fig. 6-9, 15-18h, 36-38a; para. 0074 - row drivers 612 may perform different functions depending on the types of devices used in the compute fabric 600; para. 0085 - the row driver 1503 may output the N activations to the array 1501. The array may output the M columns to the column readout 1505.), and
at least one cell analog-digital converter (ADC) connected to the plurality of memory cells via a plurality of column lines, the at least one cell ADC configured to convert cell currents read via the plurality of lines into a plurality of pieces of digital cell data (see Fig. 6-9, 15-18h, 36-38a; para. 0092 - analog-to-digital converter (ADC) may be directly used on the bitline as shown in FIG. 18(g) to convert the analog value (for example voltage, current, or charge) to a digital one. Reading the difference in output quantities (for example, voltage, current, or charge) between adjacent columns or sets of columns; para. 0095 - FIG. 18(g) an ADC may be used to directly to read out the result of the MAC operation; para. 0114 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0119 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0182 - bit line voltages are digitized by ADCs.);
a … tile including a … cell array including a plurality of … cells (see Fig. 6-9, 15-18h, 36-38a; para. 0074 - elements 611, U Ro can be implemented with different components such as resistors (RRAM, PCM), capacitors, transistors or combinations of these. These elements may be used to perform dot products or convolutions of the input signals on the rows 603 with weights determined by values of the elements 611; para. 0085 - FIG. 15 illustrates a block diagram of in-memory compute MAC block. Multiple neurons (columns) are connected adjacently and each outputs the result of a single MAC operation.),
a … row driver connected to the plurality of … cells via a plurality of … row lines (see Fig. 6-9, 15-18h, 36-38a; para. 0074 - row drivers 612 may perform different functions depending on the types of devices used in the compute fabric 600; para. 0085 - the row driver 1503 may output the N activations to the array 1501. The array may output the M columns to the column readout 1505.), and
at least one … ADC connected to the plurality of … cells via a plurality of … column lines, the at lest one … ADC configured to convert … currents read via the plurality of … column lines into a plurality of pieces of digital … data (see Fig. 6-9, 15-18h, 36-38a; para. 0092 - analog-to-digital converter (ADC) may be directly used on the bitline as shown in FIG. 18(g) to convert the analog value (for example voltage, current, or charge) to a digital one. Reading the difference in output quantities (for example, voltage, current, or charge) between adjacent columns or sets of columns; para. 0095 - FIG. 18(g) an ADC may be used to directly to read out the result of the MAC operation; para. 0114 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0119 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0182 - bit line voltages are digitized by ADCs.); and
at least one comparator circuit configured to compare … digital … data with … digital … data (see para. 0092 - analog-to-digital converter (ADC) may be directly used on the bitline as shown in FIG. 18(g) to convert the analog value (for example voltage, current, or charge) to a digital one. reading the difference in output quantities (for example, voltage, current, or charge) between adjacent columns or sets of columns.).
Papageorgiou does not explicitly disclose that the tile, cell array, row driver, row lines, ADC, cells, currents, column lines, and data are reference elements or components, and does not explicitly disclose configured to compare the plurality of pieces of cell data with the plurality of pieces of reference data.
Chang teaches or suggests that the tile, cell array, row driver, row lines, ADC, cells, currents, column lines, and data are reference elements or components, and does not explicitly disclose at least one comparator circuit configured to compare the plurality of pieces of digital cell data with the plurality of pieces of digital reference data (see Fig. 2A, 3, 5; col. 1, lines 33-38 - generating input-pattern aware reference currents and/or input-pattern aware reference voltages is need. Therefore, the present disclosure provides an input-pattern aware reference generation system to generate reference signals being able to distinguish candidates of the computational result of the bit lines in the memory cell array; col. 2, lines 54-57 - the reference array may include one or more reference sub-array and each of the reference sub-arrays may include m reference word lines crossing n reference bit lines; col. 3, lines 19-21 - method of comparing the bit line current with reference bit line currents; col. 10, lines 21-23 - the input pattern aware reference generation system can properly distinguish candidates of the bit line current and further increase the sensing margin and improve the sensing yield.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Papageorgiou, to include that the tile, cell array, row driver, row lines, ADC, cells, currents, column lines, and data are reference elements or components, and does not explicitly disclose at least one comparator circuit configured to compare the plurality of pieces of digital cell data with the plurality of pieces of digital reference data for the purpose of efficiently comparing outputs with reference values to properly distinguish bit line results in a memory array, improving memory output, as taught by Chang (col. 1 and 10).
Claim 2:
Papageorgiou further teaches or suggests a buffer configured to store the plurality of pieces of digital reference data output by the at least one … ADC (see Fig. 6-9, 15-18h, 36-38a; para. 0002 – neural network (NN) models may include a combination of multiple layers with varying number of weights in each layer. Each layer may compute a number of multiply-accumulate (MAC) operations involving the stored weights as well as the input to each layer; para. 0086 - weight is stored using a physical parameter; para. 0090 - unit cells 1701 storing components of encoded weights 1701 may be connected to separate bitlines; para. 0092 - analog-to-digital converter (ADC) may be directly used on the bitline as shown in FIG. 18(g) to convert the analog value (for example voltage, current, or charge) to a digital one. Reading the difference in output quantities (for example, voltage, current, or charge) between adjacent columns or sets of columns; para. 0095 - FIG. 18(g) an ADC may be used to directly to read out the result of the MAC operation; para. 0114 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0119 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0182 - bit line voltages are digitized by ADCs.).
Chang teaches or suggests that the ADC are reference elements or components (see Fig. 2A, 3, 5; col. 1, lines 33-38 - generating input-pattern aware reference currents and/or input-pattern aware reference voltages is need. Therefore, the present disclosure provides an input-pattern aware reference generation system to generate reference signals being able to distinguish candidates of the computational result of the bit lines in the memory cell array; col. 2, lines 54-57 - the reference array may include one or more reference sub-array and each of the reference sub-arrays may include m reference word lines crossing n reference bit lines; col. 3, lines 19-21 - method of comparing the bit line current with reference bit line currents; col. 10, lines 21-23 - the input pattern aware reference generation system can properly distinguish candidates of the bit line current and further increase the sensing margin and improve the sensing yield.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Papageorgiou, to include that the ADC are reference elements or components for the purpose of efficiently comparing outputs with reference values to properly distinguish bit line results in a memory array, improving memory output, as taught by Chang (col. 1 and 10).
Claim 3:
Papageorgiou further teaches or suggests when an inference using the neural network starts, the … tile converts the … currents into the plurality of pieces of digital … data and stores the data in a buffer, and the at least one comparator compares the plurality of pieces of digital cell data output by each of the plurality of cell tiles with the plurality of pieces of digital … data stored in the buffer (see Fig. 6-9, 15-18h, 36-38a; para. 0002 – neural network (NN) models may include a combination of multiple layers with varying number of weights in each layer. Each layer may compute a number of multiply-accumulate (MAC) operations involving the stored weights as well as the input to each layer. NN shave been very successful in classification tasks (inference); para. 0086 - weight is stored using a physical parameter; para. 0090 - unit cells 1701 storing components of encoded weights 1701 may be connected to separate bitlines; para. 0092 - analog-to-digital converter (ADC) may be directly used on the bitline as shown in FIG. 18(g) to convert the analog value (for example voltage, current, or charge) to a digital one. Reading the difference in output quantities (for example, voltage, current, or charge) between adjacent columns or sets of columns; para. 0094 - NN algorithms; para. 0095 - FIG. 18(g) an ADC may be used to directly to read out the result of the MAC operation; para. 0114 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0119 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0182 - bit line voltages are digitized by ADCs.).
Chang teaches or suggests that the tile, currents, and datas are reference elements or components (see Fig. 2A, 3, 5; col. 1, lines 33-38 - generating input-pattern aware reference currents and/or input-pattern aware reference voltages is need. Therefore, the present disclosure provides an input-pattern aware reference generation system to generate reference signals being able to distinguish candidates of the computational result of the bit lines in the memory cell array; col. 2, lines 54-57 - the reference array may include one or more reference sub-array and each of the reference sub-arrays may include m reference word lines crossing n reference bit lines; col. 3, lines 19-21 - method of comparing the bit line current with reference bit line currents; col. 10, lines 21-23 - the input pattern aware reference generation system can properly distinguish candidates of the bit line current and further increase the sensing margin and improve the sensing yield.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Papageorgiou, to include that the tile, currents, and datas are reference elements or components for the purpose of efficiently comparing outputs with reference values to properly distinguish bit line results in a memory array, improving memory output, as taught by Chang (col. 1 and 10).
Claim 4:
Papageorgiou further teaches or suggests the at least one comparator circuit includes a plurality of comparator circuits, each of the plurality of comparator circuits including a plurality of comparators, respectively, and the plurality of comparator circuits are connected to the plurality of cell tiles, respectively, and an amount of the plurality of comparators included in the plurality of comparator circuits, respectively, is equal to an amount of the plurality of column lines included in the plurality of cell tiles (see Fig. 6-9, 15-18h, 36-38a; para. 0002 - NN shave been very successful in classification tasks (inference); para. 0092 - analog-to-digital converter (ADC) may be directly used on the bitline as shown in FIG. 18(g) to convert the analog value (for example voltage, current, or charge) to a digital one. Reading the difference in output quantities (for example, voltage, current, or charge) between adjacent columns or sets of columns; para. 0094 - NN algorithms; para. 0095 - FIG. 18(g) an ADC may be used to directly to read out the result of the MAC operation; para. 0114 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0119 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0182 - bit line voltages are digitized by ADCs; para. 0233 - analog comparators connected to the two terminals of each differential bit line compare the bit-line voltages and to a VBLJ VBLbJ threshold voltage Vref (comparators could also be shared among bit lines at the cost of throughput).).
Claim 5:
Papageorgiou further teaches or suggests wherein the at least one comparator circuit includes a plurality of comparators, and the plurality of comparators are connected to the plurality of cell tiles, respectively (see Fig. 6-9, 15-18h, 36-38a; para. 0002 - NN shave been very successful in classification tasks (inference); para. 0092 - analog-to-digital converter (ADC) may be directly used on the bitline as shown in FIG. 18(g) to convert the analog value (for example voltage, current, or charge) to a digital one. Reading the difference in output quantities (for example, voltage, current, or charge) between adjacent columns or sets of columns; para. 0094 - NN algorithms; para. 0095 - FIG. 18(g) an ADC may be used to directly to read out the result of the MAC operation; para. 0114 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0119 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0182 - bit line voltages are digitized by ADCs; para. 0233 - analog comparators connected to the two terminals of each differential bit line compare the bit-line voltages and to a VBLJ VBLbJ threshold voltage Vref (comparators could also be shared among bit lines at the cost of throughput).).
Claim 6:
Papageorgiou further teaches or suggests wherein the at least one comparator circuit includes a plurality of comparator circuits having a plurality of comparators, respectively, each of the plurality of comparator circuits are connected to two or more of the plurality of cell tiles; and the two or more cell tiles store weights included in a single layer among a plurality of layers included in the neural network (see Fig. 6-9, 15-18h, 36-38a; para. 0002 – neural network (NN) models may include a combination of multiple layers with varying number of weights in each layer. Each layer may compute a number of multiply-accumulate (MAC) operations involving the stored weights as well as the input to each layer. NN shave been very successful in classification tasks (inference); para. 0090 - unit cells 1701 storing components of encoded weights 1701 may be connected to separate bitlines; para. 0092 - analog-to-digital converter (ADC) may be directly used on the bitline as shown in FIG. 18(g) to convert the analog value (for example voltage, current, or charge) to a digital one. Reading the difference in output quantities (for example, voltage, current, or charge) between adjacent columns or sets of columns; para. 0094 - NN algorithms; para. 0095 - FIG. 18(g) an ADC may be used to directly to read out the result of the MAC operation; para. 0114 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0119 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0182 - bit line voltages are digitized by ADCs; para. 0233 - analog comparators connected to the two terminals of each differential bit line compare the bit-line voltages and to a VBLJ VBLbJ threshold voltage Vref (comparators could also be shared among bit lines at the cost of throughput).).
Claim 7:
Papageorgiou further teaches or suggests wherein the comparator circuit includes a plurality of comparators, and each of the plurality of comparators are connected to two or more of the plurality of cell tiles (see Fig. 6-9, 15-18h, 36-38a; para. 0002 – neural network (NN) models may include a combination of multiple layers with varying number of weights in each layer. Each layer may compute a number of multiply-accumulate (MAC) operations involving the stored weights as well as the input to each layer. NN shave been very successful in classification tasks (inference); para. 0090 - unit cells 1701 storing components of encoded weights 1701 may be connected to separate bitlines; para. 0092 - analog-to-digital converter (ADC) may be directly used on the bitline as shown in FIG. 18(g) to convert the analog value (for example voltage, current, or charge) to a digital one. Reading the difference in output quantities (for example, voltage, current, or charge) between adjacent columns or sets of columns; para. 0094 - NN algorithms; para. 0095 - FIG. 18(g) an ADC may be used to directly to read out the result of the MAC operation; para. 0114 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0119 - current can be digitized directly using a current input ADC or buffered and passed to a subsequent stage; para. 0182 - bit line voltages are digitized by ADCs; para. 0233 - analog comparators connected to the two terminals of each differential bit line compare the bit-line voltages and to a VBLJ VBLbJ threshold voltage Vref (comparators could also be shared among bit lines at the cost of throughput).).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew T McIntosh whose telephone number is (571)270-7790. The examiner can normally be reached M-Th 8:00am-5:30pm.
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/ANDREW T MCINTOSH/Primary Examiner, Art Unit 2144