DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/12/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 and 21-25 have been considered but are moot in view of the new ground of rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-5, 8, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata (US Pat. Pub. 2005/0193293) in view of Miner (US Pat. 6,493,839).
As per claim 1: Shikata teaches an integrated circuit comprising:
a local sector manager controller circuit (Fig. 11, 6) that provides an indication to perform a memory test (paragraph 87);
a built-in-self-test (BIST) circuit (Fig. 11, 200) configurable to generate a first control signal (paragraph 87);
a first memory circuit (Fig. 11, 14) that outputs first read data in response to the first control signal during the memory test (output of 14; paragraph 86);
a first comparator circuit (Fig. 11, 53) configurable to compare the first read data with the first expected data during the memory test (paragraph 86) to generate a first test result that is provided to the BIST circuit (Fig. 11, 64);
a second memory circuit (Fig. 11, 15) that outputs second read data during the memory test (output of 15; paragraph 86); and
a second comparator circuit (Fig. 11, 59) configurable to generate a second test result based on a comparison between the second read data and the second expected data during the memory test (paragraph 86), wherein the second test result is provided to the BIST circuit (Fig. 11, 65).
Not explicitly disclosed is the built-in-self-test (BIST) circuit is configurable to generate a second control signal; and first and second expected data in response to the indication to perform the memory test. However, Miner in an analogous art teaches a BIST circuit that is configurable to generate control signals to a specified memory of a plurality of memories (col. 10, lines 50-52), and corresponding expected data (col. 11, lines 27-33).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to generate control signals and expected data for each memory of Shikata in the BIST control circuit as done by Miner. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Shikata already suggests generating control signals via a control circuit (Fig. 11, 6). Shikata also teaches generating first and second expected data (paragraph 86), and providing the expected data values by the BIST circuit 200 as done by Miner would have produced expected results. Furthermore, doing so would only have required a relocation of parts and would not have changed the principle of operation (see MPEP 2144.04 Section V: MAKING PORTABLE, INTEGRAL, SEPARABLE, ADJUSTABLE, OR CONTINUOUS).
As per claim 3: Shikata further teaches the integrated circuit of claim 1, wherein each of the sectors of logic circuits further comprises: a parallel input/output interface circuit that provides the indication to the BIST circuit and that provides the test result to the local sector manager controller circuit (Fig. 11, 54 and 62).
As per claim 4: Miner further teaches the integrated circuit of claim 1 further comprising: a secure device manager controller circuit that receives a command to perform the memory test through an input terminal of the integrated circuit (Fig. 6, 629), wherein the secure device manager controller circuit provides the command to the local sector manager controller circuit (Fig. 6, 630), and wherein the local sector manager controller circuit provides the indication to perform the memory test to the BIST circuit in response to the command (Fig. 6, 626).
As per claim 5: Miner further teaches the integrated circuit of claim 4, wherein the BIST circuit provides the test result to the local sector manager controller circuit (Fig. 5, 573), and wherein the local sector manager controller circuit provides the test result to the secure device manager controller circuit (Fig. 6, 621).
As per claim 8: Shikata further teaches the integrated circuit of claim 1, wherein the first comparator circuit is separate from the local sector manager controller circuit (Fig. 11, 53), and wherein the second comparator circuit is separate from the BIST circuit (Fig. 11, 59).
As per claim 24: Shikata further teaches the integrated circuit of claim 1, wherein each of the sectors of logic circuits further comprises: a multiplexer circuit configurable to provide write data from the BIST circuit to the first memory circuit during the memory test (Fig. 11, 71 and 72).
Claim(s) 2, 7, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Shikata in view of Miner in view of Nadeau-Dostie et al (US Pat. 4,969,148; hereinafter referred to as Nadeau-Dostie).
As per claim 2: Miner et al teach the integrated circuit of claim 1 above. Not explicitly disclosed is wherein each of the sectors of logic circuits further comprises: a multiplexer circuit configurable to provide the first control signal and first address signals from the BIST circuit to the first memory circuit during the memory test, wherein the multiplexer circuit is configurable to provide a third control signal and second address signals to the first memory circuit during a user mode. However, Nadeau-Dostie in an analogous art teaches multiplexer circuitry (Fig. 3, 41-42) configurable to provide control and address signals (Fig. 3, 26-28) from the BIST circuit (Fig. 3, 38) to a memory (Fig. 3, 25), wherein the multiplexer circuit is configurable to provide second control and address signals to the memory circuit during a user mode (Fig. 3, control and address from mission mode interface).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to employ the multiplexers of Nadeau-Dostie in the system of Miner et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have had utility where the test area must be minimized (col. 7, lines 6-19).
As per claim 7: Nadeau-Dostie further teaches the integrated circuit of claim 2, wherein the multiplexer circuit is configurable in response to an enable signal generated by the BIST circuit (Fig. 3, 32), and wherein the first comparator circuit is configurable to compare the first read data with the first expected data during the memory test in response to the enable signal (it would have been obvious to perform the BIST, which includes comparison, during a test mode).
As per claim 15: Miner et al teach the method of claim 9. Not explicitly disclosed is further comprising: generating a second control signal and additional expected data using the built-in-self-test circuit in response to the indication to perform the built-in-self-test; providing the second control signal to an additional memory circuit; outputting additional read data from the additional memory circuit during the built-in-self-test in response to the second control signal; and comparing the additional read data to the additional expected data using an additional comparator circuit to generate an additional test result. However, Pekny in an analogous art teaches performing testing on additional memory circuits (Fig. 2, 2041-204N), each comprising their own corresponding signals for independent testing (Fig. 3).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to combine the configurable BIST of Miner with the circuit architecture of Pekny. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Miner teaches circuitry for testing memory, and could have been used in Pekny for testing the memory as disclosed by Pekny in col. 3, lines 49-51.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Shikata in view of Miner in view of Natarajan et al (US Pat. 7,475,315; hereinafter referred to as Natarajan).
As per claim 6: Miner et al teach the integrated circuit of claim 1. Not explicitly disclosed is wherein the integrated circuit is a programmable logic integrated circuit, and wherein the logic circuits are programmable logic circuits. However, Natarajan in an analogous art teaches a programmable logic integrated circuit having BIST testable memory (Fig. 1; col. 3, lines 3-16).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to perform the teachings of Shikata et al on a programmable logic integrated circuit containing memory. This modification would have been obvious for one of ordinary skill in the art at the time of filing because the testing of Miner could have been performed on any suitable memory, including memory contained in programmable logic devices.
Claim(s) 9-15, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Shikata in view of Miner in view of Nadeau-Dostie.
As per claim 9: Shikata teaches a method for performing a built-in-self-test (Fig. 11, 200) of first and second memory circuits in each one of sectors of logic circuits of an integrated circuit (Fig. 11, 14 and 15), the method comprising:
providing an indication to perform the built-in-self-test (Fig. 11, 200) from a local sector manager controller circuit each of the sectors of logic circuits (Fig. 11, 51 and 57);
generating a first control signal (paragraph 87) and first expected data (paragraph 86) using a built-in-self-test circuit in the sector in response to the indication to perform the built-in-self-test (Fig. 11, 6);
outputting first read data from the first memory circuit in each of the sectors during the built-in-self-test in response to the first control signal received from the multiplexer circuit (output of 14; paragraph 86); and
comparing the first read data to the first expected data using a first comparator circuit in each of the sectors during the built-in-self-test (paragraph 86) to generate a first test result (col. 11, lines 46-47), wherein the first comparator circuit is separate from the built-in-self-test circuit (Fig. 11, 53);
providing a second memory circuit in each of the sectors (Fig. 11, 15);
outputting second read data from the second memory circuit during the built-in- self-test in response to the second control signal (output of 15; paragraph 86); and
comparing the second read data to the second expected data using a second comparator circuit in each of the sectors to generate a second test result (Fig. 11, 59; paragraph 86).
Not explicitly disclosed is providing the first control signal to the first memory circuit using a multiplexer circuit in each of the sectors; and generating and providing a second control signal and second expected data using the built-in- self-test circuit in each of the sectors in response to the indication to perform the built-in-self- test.
However, Miner in an analogous art teaches a BIST circuit that is configurable to generate control signals to a specified memory of a plurality of memories (col. 10, lines 50-52), and corresponding expected data (col. 11, lines 27-33).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to generate control signals and expected data for each memory of Shikata in the BIST control circuit as done by Miner. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Shikata already suggests generating control signals via a control circuit (Fig. 11, 6). Shikata also teaches generating first and second expected data (paragraph 86), and providing the expected data values by the BIST circuit 200 as done by Miner would have produced expected results. Furthermore, doing so would only have required a relocation of parts and would not have changed the principle of operation (see MPEP 2144.04 Section V: MAKING PORTABLE, INTEGRAL, SEPARABLE, ADJUSTABLE, OR CONTINUOUS).
Also not explicitly disclosed is providing the first control signal to the first memory circuit using a multiplexer circuit. However, Nadeau-Dostie in an analogous art teaches providing a control signal (Fig. 3, 28) to a memory circuit (Fig. 3, 25) using a multiplexer circuit (Fig. 3, 42); and outputting read data (Fig. 3, 30) in response to the control signal received from the multiplexer circuit (Fig. 3, read and write control signals).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to employ the multiplexers of Nadeau-Dostie for providing the control signals of Shikata and Miner. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have had utility where the test area must be minimized (col. 7, lines 6-19).
As per claim 10: Shikata further teaches the method of claim 9 further comprising: providing the first test result from the first comparator circuit to the built-in-self-test circuit (Fig. 11, 64).
As per claim 11: Shikata and Nadeau-Dostie further teach the method of claim 9 further comprising: generating address signals at the built-in-self-test circuit (Shikata Fig. 1, 7); providing the address signals from the built-in-self-test circuit to the memory circuit through the multiplexer circuit during the built-in-self-test (Nadeau-Dostie Fig. 3, 26); and accessing the read data in the memory circuit at addresses indicated by the address signals (Shikata paragraph 36).
As per claim 12: Shikata further teaches the method of claim 9, wherein providing the indication to perform the built-in-self-test further comprises: providing the indication to perform the built-in-self-test through a parallel input/output interface circuit to the built-in-self-test circuit (Fig. 11, 54 and 62).
As per claim 13:
Miner further teaches the method of claim 9 further comprising: receiving a command to perform the built-in-self-test at a secure device manager circuit in the integrated circuit from a host system through an input terminal of the integrated circuit (Fig. 6, 629); and providing the command from the secure device manager circuit to the local sector manager controller circuit (Fig. 6, 630).
As per claim 14: Nadeau-Dostie further teaches the method of claim 9 further comprising: providing a third control signal from a user logic circuit to the first memory circuit using the multiplexer circuit (Fig. 3, control and address from mission mode interface) in response to an enable signal generated by the built-in-self-test circuit (Fig. 3, 32).
As per claim 15:
Shikata further teaches the method of claim 9, wherein the first comparator circuit is separate from the local sector manager controller circuit (Fig. 11, 53), and wherein the second comparator circuit is separate from the BIST circuit (Fig. 11, 59).
As per claim 22:
Nadeau-Dostie further teaches the method of claim 9 further comprising: configuring the multiplexer circuit to provide a third control signal and address signals to the first memory circuit during a user mode of the integrated circuit (Figs. 3 and 5; second signals for a user mission mode provided to the multiplexer from the Mission Mode Interface).
As per claim 23: Nadeau-Dostie further teaches the method of claim 9 further comprising: configuring the multiplexer circuit in response to an enable signal generated by the built-in-self-test circuit (Fig. 3, TESTON); and configuring the first comparator circuit to compare the first read data with the first expected data during the built-in-self-test in response to the enable signal (Shikata paragraph 86).
Claim(s) 21 are rejected under 35 U.S.C. 103 as being unpatentable over Shikata in view of Miner in view of Nadeau-Dostie in view of Moore (US Pat. 6,839,873).
As per claim 21: Miner et al teach the method of claim 9. Not explicitly disclosed is wherein the integrated circuit is a programmable logic integrated circuit, and wherein the logic circuits are programmable logic circuits. However, Moore in an analogous art teaches a BIST circuit of a memory (Fig. 2A, 208) in an integrated circuit comprising a programmable logic device (Fig. 2A, 204).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to implement the teachings of Shikata et al to a memory in a programmable logic device such as Moore. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Miner et al could have been applied to any memory with expected results and without changing the principle of operation.
Claim(s) 25 is rejected under 35 U.S.C. 103 as being unpatentable over Shikata in view of Miner in view of Reynolds, Jr (US Pat. Pub. 2004/0243898; hereinafter referred to as Reynolds).
As per claim 25: Miner et al teach the integrated circuit of claim 24 above. Not explicitly disclosed is wherein the multiplexer circuit is configurable to provide addresses and a read enable bit to the memory circuit, and wherein the memory circuit outputs the read data at the addresses in response to the read enable bit during the memory test. However, Reynolds in an analogous art teaches a memory BIST comprising multiplexers (Fig. 3) to provide address (Fig. 1B, 205) and read enable bit (Fig. 1B, 203) for outputting read data in response to the read enable bit during the memory test (Fig. 2, 209-212).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to perform the memory read as taught by Reynolds. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have allowed edged triggered memory devices to be tested by a BIST (paragraph 18).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111