Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 7th, 2025 has been received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendments
Acknowledgment is made of the amendment filed 11/19/2025 (“A...”), in which: claims 1, 12, and 18 are amended; no claims are cancelled; no new claims are added; and the rejection of the claims are traversed. Claims 1 – 20 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to Claims 1 - 20 have been fully considered but are moot in view of the new grounds of rejection.
Rejections
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3, 7, and 9 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Keeth et al. (US 20110246746 A1) and Hsu et al. (US 10727198 B2).
Regarding independent claim 1, Yu teaches a semiconductor package comprising:
a base redistribution layer (Fig. 10; redistribution structure 102);
a plurality of package connection members (Fig. 10; conductive connectors 114) attached to a lower surface of the base redistribution layer (Fig. 10 shows the conductive connectors 114 attached to a lower surface of the base redistribution layer. See [0060] – [0061]);
a first semiconductor chip (Fig. 10; memory device 60 is interpreted to be a first semiconductor chip. See [0015] wherein Yu discloses that each of a first processor device 20, a second processor device 40, a memory device 60, and a passive device 80 is a bare integrated circuit die, i.e., a first semiconductor chip, or a packaged die) provided on the base redistribution layer (Figs. 10 – 11 and [0061]);
…
a third semiconductor chip (Fig. 10; second processor device 40 is interpreted to be a third semiconductor chip) provided between the base redistribution layer and the first semiconductor chip (Fig. 10);
a plurality of connection posts (Fig. 10; second conductive vias 110 (unlabeled; see Fig. 7B) are discussed, e.g., at least in [0036], to connect the redistribution structure 102 to the back side 60B of the memory device 60) provided between the base redistribution layer and the first semiconductor chip (Fig. 10), the plurality of connection posts being configured to electrically connect the base redistribution layer to the first semiconductor chip ([0036]) and being spaced apart from the third semiconductor chip in a horizontal direction (Fig. 10); and
a second molding layer (Fig. 10; second dielectric layer 108 (unlabeled; see Fig. 7B) are discussed, e.g., at least in [0036], to surround the second processor device 40 and second conductive vias 110) surrounding the third semiconductor chip (Fig. 10 and [0036]) and the plurality of connection posts (Fig. 10 and [0036]) between the base redistribution layer and the first semiconductor chip (Fig. 10),
wherein the first semiconductor chip extends over both sides of the third semiconductor chip in the horizontal direction (Fig. 10),
…
wherein the first semiconductor chip comprises a first through electrode (Figs. 1C and 10 – 11; die connectors 68 of the memory device 60),
…
However, Yu remains silent regarding a semiconductor package further comprising:
… at least two chip stacks stacked on the first semiconductor chip in a vertical direction, each chip stack of the at least two chip stacks comprising a plurality of second semiconductor chips electrically connected to the first semiconductor chip;
a first molding layer covering an upper surface of the first semiconductor chip and surrounding the at least two chip stacks; …
wherein, in a first stack of the at least two chip stacks, each of the plurality of second semiconductor chips comprises a second through electrode, and
wherein the first through electrode is vertically aligned with each second through electrode.
Examiner asserts that Yu’s first processor device 20 of integrated circuit package 100 (Figs. 1A, 9B, and 10 – 11) is a device connected to Yu’s first semiconductor chip (Fig. 10; memory device 60 and [0046]); such as applicant’s instant, albeit of different structure, at least two chip stacks stacked on the first semiconductor chip in a vertical direction configured to be a device connected to applicant’s first semiconductor chip. Further, examiner notes the related feature between Yu’s first semiconductor chip and first processor device 20 wherein both include through electrodes, first (die connectors 68 of the memory device 60) and second (die connectors 28 of the first processor device 20 taught to be conductive pillars in and/or on interconnect structure 24 in at least [0019]) through electrodes, respectively; and wherein the first through electrode is vertically aligned with each second through electrode (Fig. 10). From the above understanding, examiner concludes from Yu that a device may be added in a similar way to that of Yu’s first processor device 20, modifying Yu’s disclosed package structure.
Thus, in the same field of endeavor, Keeth describes stacked devices wherein an interface die 310 (analogous to Yu’s first semiconductor chip) has at least two chip stacks (Fig. 3; two dice stacks 302 and 325. Also see [0025]) stacked on the first semiconductor chip in a vertical direction (Fig. 3), each chip stack of the at least two chip stacks comprising a plurality of second semiconductor chips (e.g., dice 320, 321, 322, 323, 330, 331, 332, and 333) electrically connected to the first semiconductor chip (Fig. 3); further including the feature wherein, in a first stack of the at least two chip stacks, each of the plurality of second semiconductor chips comprises a second through electrode (Fig. 3; TSVs 304), and wherein the first through electrode is vertically aligned with each second through electrode (Fig. 3; wherein joints 308 are considered analogous to Yu’s first through electrode). Examiner asserts that through Yu’s disclosure, Keeth’s at least two chip stacks may be combined with Yu’s semiconductor package; thus, yielding a semiconductor package of Yu, further in view of Keeth, including:
... at least two chip stacks stacked on the first semiconductor chip in a vertical direction, each chip stack of the at least two chip stacks comprising a plurality of second semiconductor chips electrically connected to the first semiconductor chip; ...
wherein, in a first stack of the at least two chip stacks, each of the plurality of second semiconductor chips comprises a second through electrode, and
wherein the first through electrode is vertically aligned with each second through electrode.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s semiconductor package to include Keeth’s at least two chip stacks, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Keeth’s semiconductor package is comparable to Yu’s semiconductor package because they both include memory device (E.g., Yu’s chip 60 and Keeth’s at least two chip stacks). Therefore, it is within the capabilities of one of ordinary skill in the art to modify Yu’s semiconductor package to include Keeth’s at least two chip stacks with the predictable result of forming a package components with memory semiconductor devices.
Further, in the same field of endeavor, Hsu teaches a semiconductor package including semiconductor devices 200a and 200b; wherein the semiconductor devices, i.e., semiconductor devices 200a and 200b, have a similar style of attachment as Yu and Keeth’s combined first semiconductor chip and at least two chip stacks; however, Hsu teaches an underfill material 210, considered by the examiner to be analogous to the instant first molding layer, that fills gaps between the semiconductor devices 200a and 200b, and between the semiconductor devices 200a and 200b and the chips below, e.g., Hsu’s integrated circuit component 130. Thus, Hsu’s underfill material may be combined with the semiconductor package of Yu, further in view of Keeth, to yield a semiconductor package wherein:
… a first molding layer (Hsu: Fig. 24; underfill material 210) covering an upper surface of the first semiconductor chip (Similar to Hsu’s Fig. 24 (showing the underfill material 210 between semiconductor devices 200a and 200b and integrated circuit component 130), the first molding layer, i.e., Hsu’s underfill material 210, filling the gap between Yu and Keeth’s first semiconductor chip and second semiconductor chip) and surrounding the at least two chip stacks (Similar to Hsu’s Fig. 24, showing the underfill material 210 surrounding the semiconductor devices 200a and 200b); …
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s semiconductor package, further in view of Keeth, to include Hsu’s underfill material as a mold, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Yu’s semiconductor package, further in view of Keeth, as modified by Hsu’s underfill material can yield a predictable result of stress relief on package components (Yu: [0065]). Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Regarding dependent claim 3, Yu, further in view of Keeth and Hsu, teach the semiconductor package of claim 1; however, Yu remains silent wherein:
a horizontal width and a horizontal area of the first semiconductor chip are equal to a horizontal width and a horizontal area of each of the first molding layer, the second molding layer, and the base redistribution layer.
However, Yu discloses a first processor device 20 which a relatively large width and area (Fig. 2D); such that the Yu discloses that a chip, i.e., first processor device 20, has a width and area that may be equal to a horizontal width and a horizontal area of each of the first molding layer, the second molding layer, and the base redistribution layer. Thus, one of ordinary skill in the art would be enablable to form a first semiconductor chip with a width and area that is that same as Yu’s first processor device 20; such that a horizontal width and a horizontal area of the first semiconductor chip are equal to a horizontal width and a horizontal area of each of the first molding layer, the second molding layer, and the base redistribution layer. Examiner notes that one of ordinary skill in the art would be mindful to ensure that the first semiconductor chip including a plurality/at least two chip stacks thereon, has sufficient area to package the at least two chip stacks thereon.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s first semiconductor chip to include a large width and area because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Yu teaches in at least [0041] – [0043] the benefits of the first processor device 20 having a wide width and area; benefits of which may be applicable to Yu’s first semiconductor chip, because Yu teaches the open possibility that the memory device 60, i.e., a first semiconductor chip, may be a packaged die. In the case where Yu’s first semiconductor chip is a packaged die, hybrid bonding may be incorporated by placing second dielectric layer 108 over memory device 60. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Yu’s first semiconductor chip to include a horizontal width and a horizontal area of the first semiconductor chip are equal to a horizontal width and a horizontal area of each of the first molding layer, the second molding layer, and the base redistribution layer with the predictable result of improving direct face-to-face bonding and the possibility of connecting with multiple package components with lower latency.
Regarding dependent claim 7, Yu, further in view of Keeth and Hsu, teach the semiconductor package of claim 1, wherein:
an active surface of the third semiconductor chip (Yu: Fig. 1B; active surface 42A of the second processor device 40) faces the base redistribution layer (Yu: Fig. 10).
Regarding dependent claim 9, Yu, further in view of Keeth and Hsu, teach the semiconductor package of claim 7, wherein:
the third semiconductor chip is electrically connected to the base redistribution layer by a plurality of chip connection members (Yu: Fig. 1B; interconnect structure 44) between a lower surface of the third semiconductor chip and the base redistribution layer (Yu: Figs. 1B and 10), and
wherein lower surfaces of the plurality of chip connection members, lower surfaces of the plurality of connection posts, and a lower surface of the second molding layer are positioned at a same vertical level to be coplanar with each other (Yu: Fig. 10).
Regarding dependent claim 10, Yu, further in view of Keeth and Hsu, teach the semiconductor package of claim 1, wherein:
… the third semiconductor chip comprises a graphics processing unit (GPU) chip (Yu teaches in [0021] that second processor device 40 can be a GPU).
However, Yu remains silent wherein:
the first semiconductor chip and the plurality of second semiconductor chips constitute a high bandwidth memory (HBM), and ...
However, Keeth discloses in [0016] that the formed memory device (Fig. 3) may be HBDRAM, i.e., high bandwidth memory (HBM); wherein Yu discloses that the memory device 60 may be DRAM. Examiner asserts that these technologies are analogous to each other, and therefore the modification of Yu, further in view of Keeth, is obvious.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s semiconductor package to include Keeth’s at least two chip stacks, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Keeth’s semiconductor package is comparable to Yu’s semiconductor package because they both include memory device (E.g., Yu’s chip 60 and Keeth’s at least two chip stacks). Therefore, it is within the capabilities of one of ordinary skill in the art to modify Yu’s semiconductor package to include Keeth’s at least two chip stacks with the predictable result of forming a package components with memory semiconductor devices.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Keeth et al. (US 20110246746 A1), Hsu et al. (US 10727198 B2), and Chen et al. (US 20190148336 A1).
Regarding dependent claim 2, Yu, further in view of Keeth and Hsu, teach the semiconductor package of claim 1, wherein:
an active surface of the first semiconductor chip (Yu: Fig. 1C; active surface 62A of memory device 60, as discussed in [0024]) …
However, Yu remain silent wherein:
an active surface of the first semiconductor chip …faces active surfaces of the plurality of second semiconductor chips.
However, in the same field of endeavor, Chen teaches in Fig. 14 a package component 2 which may include a plurality of chips 4 therein; and wherein the device die 4 may be a memory die ([0012]). Further, Chen discloses in [0063] that die stacks 112 and device die 4 have face-to-face structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor package of Yu, further in view of Keeth and Hsu, to include Chen’s face to face chip structure for a memory structure, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Chen’s first semiconductor chip and plurality of second semiconductor chips is comparable to the first semiconductor chip and plurality of second semiconductor chips of Yu, further in view of Keeth, because they’re both memory semiconductor devices. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor package of Yu, further in view of Keeth and Hsu, to include Chen’s face to face chip structure for a memory structure with the predictable result of forming a memory device structure.
Claims 4 – 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Keeth et al. (US 20110246746 A1), Hsu et al. (US 10727198 B2), Ho (US 20010016370 A1), and Yu et al. (US 20170170155 A1).
Regarding dependent claim 4, Yu, further in view of Keeth and Hsu, teach the semiconductor package of claim 1; however, Yu remains silent regarding the semiconductor package further comprising:
a connection redistribution layer provided between the first semiconductor chip and the second molding layer,
wherein an active surface of the third semiconductor chip faces the connection redistribution layer.
However, in the same field of endeavor, Ho teaches in [0085] an integrated circuit die/ flip chip 16 disposed directly in contact with an interconnect substrate 12, i.e., a base redistribution layer; wherein the active surface is facing away from the base redistribution layer. Thus, the non-active surface of flip chip 16 is disposed in direct contact with the interconnect substrate 12, i.e., a base redistribution layer. Ho’s teaching for assembling package components may be applied to the assembly of Yu’s third semiconductor chip; such that Yu’s die connectors 48 and conductive vias 46 (Fig. 1B) are no longer functionally necessary, and Yu’s dielectric layer 50 of the third semiconductor chip would be disposed directedly on the base redistribution layer. Further, Application of Ho’s teaching to Yu’s semiconductor package results in Yu’s interconnect structure 44, i.e., a connection redistribution layer, facing upwards instead of downwards; such that a connection redistribution layer is provided between the first semiconductor chip and the second molding layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s third semiconductor chip to include being assembled into the semiconductor package in a manner similar to what is disclosed by Ho, because such a modification is the result of applying a known technique to a known device ready for improvement to yield predictable results. More specifically, Ho’s disclosed method of assembling package components permits Yu’s active surfaces of the first semiconductor chip and third semiconductor chip to be electrically connected without the use of Yu’s die connectors 48 and conductive vias 46, lowering latency of the semiconductor package. This known benefit in Ho’s disclosed method of assembling package components is applicable to Yu’s assembly of their third semiconductor chip into their semiconductor package as they both share characteristics and capabilities, namely, they are directed to packaging semiconductor chips. Therefore, it would have been recognized that modifying Yu’s third semiconductor chip to include being assembled into the semiconductor package in a manner similar to what is disclosed by Ho would have yielded predictable results because (i) the level of ordinary skill in the art demonstrated by the references applied shows the ability to incorporate Ho’s disclosed method of assembling package components in semiconductor packages and (ii) the benefits of such a combination would have been recognized by those of ordinary skill in the art.
Yu’s disclosed interconnect structure 44 makes the use of Ho’s wire bond optional, however, interconnect structure 44 should be further modified to allow connection to the first semiconductor chip and the base distribution layer.
Further, in the same field of endeavor, Yu (US 20170170155 A1) teaches a semiconductor package in Fig. 6; wherein the substrate 421 is considered to be a base redistribution layer ([0071]), fourth semiconductor device 107 is considered to be a third semiconductor chip, the first redistribution layer 309 is considered to be a connection redistribution layer, and the second encapsulant 419 is considered to be a second molding layer. Thus, Yu, further in view of Keeth, Hsu and Ho, combined with Yu’s (US 20170170155 A1) configuration disclosed in their Fig. 6 yields the semiconductor package structure including a connection redistribution layer provided between the first semiconductor chip and the second molding layer, wherein an active surface of the third semiconductor chip faces the connection redistribution layer
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the connection redistribution layer of Yu, further in view of Keeth, Hsu and Ho, to include a structure for rerouting a signal from the third semiconductor chip to the base redistribution layer, as disclosed by Yu (US 20170170155 A1) in Fig. 6 of their disclosure, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Yu’s (US 20170170155 A1) semiconductor package structure with regards to their analogous connection redistribution layer, first semiconductor chip, third semiconductor chip, and base redistribution layer is comparable to the modified semiconductor package of Yu, further in view of Keeth, Hsu and Ho (as outlined above) because both allow electrical connection between semiconductor package components via a connection redistribution with the same orientation of active surfaces of the semiconductor chips. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the connection redistribution layer of Yu, further in view of Keeth, Hsu and Ho, to include a structure for rerouting a signal from the third semiconductor chip to the base redistribution layer, as disclosed by Yu (US 20170170155 A1) with the predictable result of connecting the third semiconductor chip to the base redistribution layer.
Regarding dependent claim 5, Yu, further in view of Keeth, Hsu, Ho, and Yu, teach the semiconductor package of claim 4, wherein:
a non-active surface of the third semiconductor chip contacts an upper surface of the base redistribution layer (Yielded from the combination of Yu and Ho).
Regarding dependent claim 6, Yu, further in view of Keeth, Hsu, Ho, and Yu, teach the semiconductor package of claim 4; wherein:
a non-active surface of the third semiconductor chip, lower surfaces of the plurality of connection posts, and a lower surface of the second molding layer are at a same vertical level to be coplanar with each other (Yielded from the contributions of Ho and Yu (US 20170170155 A1) to the semiconductor package of Yu, further in view of Hsu).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Keeth et al. (US 20110246746 A1), Hsu et al. (US 10727198 B2), and Lin et al. (US 20180165396 A1).
Regarding dependent claim 8, Yu, further in view of Keeth, Hsu, teach the semiconductor package of claim 1,further comprising:
… a non- active surface of the third semiconductor chip (Yu: Fig. 1B; inactive surface 42N), …
However, Yu remains silent regarding:
a connection redistribution layer provided between the first semiconductor chip and the second molding layer,
wherein the third semiconductor chip comprises a die adhesive film attached to… a non- active surface of the third semiconductor chip, … and attached to a lower surface of the connection redistribution layer.
However, in the same field of endeavor, Lin teaches a semiconductor package (Fig. 19N) including a Top Interconnection Scheme in, on or of the logic Drive (TISD) 101 is considered to be analogous to a connection redistribution layer ([0033]); a semiconductor chip 100, considered to be similar to the instant third semiconductor chip, under the TISD 101; a semiconductor chip 100, considered to be similar to the instant first semiconductor chip, above TISD 101; a glue material 88, considered to be analogous to a die adhesive film; and a polymer layer 92, considered to be analogous to a second molding layer. Lin’s structure for their semiconductor chips, including the micro-bumps 34, may be applied to the semiconductor package of Yu, further in view of Keeth and Hsu, to yield the semiconductor package wherein a connection redistribution layer provided between the first semiconductor chip and the second molding layer, wherein the third semiconductor chip comprises a die adhesive film attached to a non- active surface of the third semiconductor chip, and attached to a lower surface of the connection redistribution layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the assembly of the semiconductor package of Yu, further in view of Keeth and Hsu, to include the structure disclosed by Lin, because such a modification is the result of applying a known technique to a known device ready for improvement to yield predictable results. More specifically, Lin’s semiconductor package assembly permits a connection redistribution layer provided between the first semiconductor chip and the second molding layer, wherein the third semiconductor chip comprises a die adhesive film attached to a non- active surface of the third semiconductor chip, and attached to a lower surface of the connection redistribution layer. This known semiconductor structure, as disclosed by Lin’s semiconductor package assembly is applicable to the assembly of the semiconductor package of Yu, further in view of Keeth and Hsu, as they both share characteristics and capabilities, namely, they are directed to semiconductor packages. Therefore, it would have been recognized that modifying the assembly of the semiconductor package of Yu, further in view of Keeth and Hsu, to include a connection redistribution layer provided between the first semiconductor chip and the second molding layer, wherein the third semiconductor chip comprises a die adhesive film attached to a non- active surface of the third semiconductor chip, and attached to a lower surface of the connection redistribution layer, as disclosed by Lin, would have yielded predictable results because (i) the level of ordinary skill in the art demonstrated by the references applied shows the ability to incorporate Lin’s semiconductor package assembly in semiconductor packages and (ii) the benefits of such a combination would have been recognized by those of ordinary skill in the art.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Hsu et al. (US 10727198 B2), Ho (US 20010016370 A1), Yu et al. (US 20170170155 A1), and Chang et al. (US 20220375826 A1).
Regarding dependent claim 11, Yu, further in view of Keeth, Hsu, Ho, and Yu, teach the semiconductor package of claim 5, wherein:
each chip stack of the at least two chip stacks comprises n second semiconductor chips (Keeth: Fig. 3; each chip stack includes 4 dies) stacked in the vertical direction, and n is a multiple of 2 (4 is a multiple of 2), and …
However, Yu remains silent wherein:
... wherein a thickness of the third semiconductor chip is less than 1/n of a total thickness of the first semiconductor chip and the at least two chip stacks.
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However, in the same field of endeavor, Chang discloses substrate cores 502 and 755; which, in some embodiments, includes one or more passive and/or active components embedded inside ([0085] and [0093]). Thus, the examiner is interpreting these substrate cores to be analogous to semiconductor chips, more specifically, substrate core 755 to be a first semiconductor chip and substrate core 502 to be a third semiconductor chip. Further, as shown in Fig. 20, there is chip stack 195 including at least 2 chips therein. In the excerpt of Fig. 20 below, it is shown that the first semiconductor chip has a thickness of 0.76 and the at least two chip stack is shown with a thickness of 1.61; such that the total thickness of the first semiconductor chip and the at least two chip stack is drawn with a thickness of 2.37. As n equals 2, one-half of 2.37 is 1.185. Note below that the third semiconductor chip has a thickness 0.61. Therefore, Chang discloses a feature of a semiconductor package wherein a thickness of the third semiconductor chip is less than 1/n of a total thickness of the first semiconductor chip and the at least two chip stacks. This relative thickness for the respective components may be applied to the semiconductor package of Yu, further in view of Keeth, Hsu, Ho, and Yu.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor package of Yu, further in view of Keeth, Hsu, Ho, and Yu, to include chips wherein a thickness of the third semiconductor chip is less than 1/n of a total thickness of the first semiconductor chip and the at least two chip stacks, as disclosed by Chang, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Chang’s semiconductor chips are comparable to the semiconductor chips of Yu, further in view of Keeth, Hsu, Ho, and Yu, because they may be the same type, in reference to function, of semiconductor devices and made with similar materials. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor chips of Yu, further in view of Keeth, Hsu, Ho, and Yu, to include Chang’s relative sizing of semiconductor chips with the predictable result of a thickness of the third semiconductor chip is less than 1/n of a total thickness of the first semiconductor chip and the at least two chip stacks.
Claims 12 and 16 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Lim (US 20170012031 A1) and Hsu et al. (US 10727198 B2).
Regarding independent claim 12, Yu teaches a semiconductor package comprising:
a base redistribution layer (Fig. 8B; redistribution structure 102);
a plurality of package connection members (Fig. 10; conductive connectors 114) attached to a lower surface of the base redistribution layer (Figs. 10 – 11);
a connection redistribution layer (Fig. 1A; interconnect structure 24) provided on the base redistribution layer;
a main semiconductor chip (Fig. 10; second processor device 40 is interpreted to be a main semiconductor chip) comprising a graphics processing unit (GPU) ([0021] teaches that the second processor device 40 may be a graphics processing unit (GPU)), and provided between the base redistribution layer and the connection redistribution layer (Figs. 10 – 11);
a plurality of connection posts (Figs. 7B and 10; second conductive vias 110) provided between the base redistribution layer and the connection redistribution layer (Fig. 11) to electrically connect the base redistribution layer to the connection redistribution layer (Fig. 11), the plurality of connection posts being spaced apart from the main semiconductor chip in a horizontal direction (Figs. 10 - 11); …
a second molding layer (Fig. 2B; second dielectric layer 108) configured to fill a space between the base redistribution layer and the connection redistribution layer and surrounding the plurality of connection posts (Fig. 10), …
However, Yu, remains silent regarding a semiconductor package wherein:
… at least one chip stack electrically connected to the connection redistribution layer, attached to the connection redistribution layer such that at least a portion of the at least one chip stack overlaps the main semiconductor chip in a vertical direction, the at least one chip stack comprising a plurality of sub-semiconductor chips;
a first molding layer covering an upper surface of the connection redistribution layer and surrounding at least some of the plurality of sub-semiconductor chips; and …
wherein the plurality of sub-semiconductor chips are shifted in the horizontal direction to be stacked on the connection redistribution layer in the vertical direction and to have a step shape in the vertical direction,
wherein, in the horizontal direction, the main semiconductor chip comprises a first side and a second side opposite to the first side,
wherein a lowermost sub-semiconductor chip of the plurality of sub-semiconductor chips extends past the first side of the main semiconductor chip in the horizontal direction, and
wherein an uppermost sub-semiconductor chip of the plurality of sub-semiconductor chips extends past the second side of the main semiconductor chip in the horizontal direction.
However, in the same field of endeavor, Lim discloses a semiconductor package including a logic die (Fig. 8; first semiconductor die 110), i.e., a main semiconductor chip, and at least one chip stack (Fig. 8; memory die 1 – 8) comprising a plurality of sub-semiconductor chips. Examiner asserts that Lim’s at least one chip stack may be used to modify Yu’s semiconductor package; wherein combining the disclosures may yield the structure wherein Lim’s at least one chip stack may be disposed over Yu’s first processor device 20. Thus, Yu, further in view of Lim, yield at least one chip stack that may be connected to the connection redistribution layer.
Further, Lim’s discloses the at least one chip stack wherein the plurality of sub-semiconductor chips are shifted in the horizontal direction to be stacked on the connection redistribution layer in the vertical direction and to have a step shape in the vertical direction, wherein, in the horizontal direction, the main semiconductor chip comprises a first side and a second side opposite to the first side, wherein a lowermost sub-semiconductor chip of the plurality of sub-semiconductor chips extends past the first side of the main semiconductor chip in the horizontal direction, and wherein an uppermost sub-semiconductor chip of the plurality of sub-semiconductor chips extends past the second side of the main semiconductor chip in the horizontal direction.
Thus, Yu, further in view of Lim, yield the semiconductor package wherein:
at least one chip stack electrically connected to the connection redistribution layer, attached to the connection redistribution layer such that at least a portion of the at least one chip stack overlaps the main semiconductor chip in a vertical direction, the at least one chip stack comprising a plurality of sub-semiconductor chips ...
wherein the plurality of sub-semiconductor chips are shifted in the horizontal direction to be stacked on the connection redistribution layer in the vertical direction and to have a step shape in the vertical direction,
wherein, in the horizontal direction, the main semiconductor chip comprises a first side and a second side opposite to the first side,
wherein a lowermost sub-semiconductor chip of the plurality of sub-semiconductor chips extends past the first side of the main semiconductor chip in the horizontal direction, and
wherein an uppermost sub-semiconductor chip of the plurality of sub-semiconductor chips extends past the second side of the main semiconductor chip in the horizontal direction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s semiconductor package to include Lim’s at least one chip stack, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Lim’s semiconductor package is comparable to Yu’s semiconductor package because they both include memory device (E.g., Yu’s chip 60 and Lim’s at least one chip stack). Therefore, it is within the capabilities of one of ordinary skill in the art to modify Yu’s semiconductor package to include Lim’s at least one chip stack with the predictable result of forming a package components with memory semiconductor devices.
Further, in the same field of endeavor, Hsu teaches a semiconductor package (e.g., Fig. 22) with an integrated circuit component 130 (i.e., a semiconductor chip) formed with through silicon vias (TSVs) 136. The TSVs 136 are embedded in the semiconductor substrate 131 (considered analogous to Yu’s semiconductor substrate 22 of the first processor device 20) of integrated circuit component 130 ([0033]) to create an electrical pathway from the interconnection structure 132 (considered analogous to Yu’s interconnect structure 24, i.e., the connection redistribution layer of the first processor device 20) to the both the conductive patterns 230 and the conductive elements 240 ([0084]). Hsu’s disclosure provides an example wherein a semiconductor chip/package, e.g., at least one chip stack, may be electrically connected to the connection redistribution layer. Additionally, Hsu teaches an a first molding layer, i.e., underfill material 210 (Fig. 24), that may be provided during the addition of Lim’s at least one chip stack; such that Hsu’s underfill material 210 may be provided covering an upper surface of the connection redistribution layer and surrounding at least some of the plurality of sub-semiconductor chips, similar to Lim’s overmold material 160 (Fig. 8).
Thus, Yu, further in view of Lim and Hsu, teach the semiconductor package including:
… a first molding layer covering an upper surface of the connection redistribution layer and surrounding at least some of the plurality of sub-semiconductor chips; …
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s semiconductor package, further in view of Lim, to include Hsu’s underfill material as a mold, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Yu’s semiconductor package, further in view of Lim, as modified by Hsu’s underfill material can yield a predictable result of stress relief on package components (Yu: [0065]). Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Regarding dependent claim 16, Yu, further in view of Lim and Hsu, teach the semiconductor package of claim 12, wherein:
a non-active surface of each sub-semiconductor chip of the plurality of sub-semiconductor chips faces the connection redistribution layer (Lim: Fig. 8; inactive surfaces 174).
Regarding dependent claim 17, Yu, further in view of Lim and Hsu, teach the semiconductor package of claim 12, wherein:
corresponding side surfaces of the first molding layer, the connection redistribution layer, the second molding layer, and the base redistribution layer are aligned with each other in the vertical direction (Yu: Fig. 11).
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Lim (US 20170012031 A1), Hsu et al. (US 10727198 B2), and Yu et al. (US 20190074261 A1).
Regarding dependent claim 13, Yu, further in view of Lim and Hsu, teach the semiconductor package of claim 12, further comprising:
a first semiconductor chip (Yu: Figs. 1A, 10, and 11; first processor 20 is interpreted to be a first semiconductor chip, more specifically semiconductor substrate 22 including active and passive surfaces. See [0015] wherein Yu discloses that the first processor device 20 may be a bare integrated circuit die, i.e., a first semiconductor chip) provided between the connection redistribution layer and the first molding layer (yielded from the combination of Yu, Lim, and Hsu. See Yu’s Fig. 11), ...
However, Yu remains silent regarding:
... wherein the at least one chip stack comprises at least two chip stacks, each chip stack comprising at least two of the plurality of sub-semiconductor chips stacked on the first semiconductor chip in the vertical direction and spaced apart from each other in the horizontal direction, and
wherein the main semiconductor chip overlaps at least a portion of the at least two chip stacks in the vertical direction.
However, in the same field of endeavor, Yu (US 20190074261 A1) teaches a package structure in Fig. 10 wherein the at least one chip stack (Fig. 10; device dies 20) comprises at least two chip stacks (Fig. 10), each chip stack comprising at least two of the plurality of sub-semiconductor chips (Fig. 10; device dies 20-3 and 20-4) stacked on the first semiconductor chip (Fig. 10; device die 10) in the vertical direction and spaced apart from each other in the horizontal direction (Fig. 10), and wherein the main semiconductor chip overlaps at least a portion of the at least two chip stacks in the vertical direction (Fig. 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the at least one chip stack of Yu, further in view of Lim, to include at least two chip stacks as part of the one chip stack, as disclosed by Yu (US 20190074261 A1), because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Yu’s (US 20190074261 A1) at least one chip stack is comparable to the at least one chip stack of Yu, further in view of Lim, because both are related to packaging semiconductor chips stacked over each other. Therefore, it is within the capabilities of one of ordinary skill in the art to modify [the at least one chip stack of Yu, further in view of Lim, to include at least two chip stacks as part of the one chip stack, as disclosed by Yu (US 20190074261 A1) with the predictable result of optimizing the area used over the base of the device.
Regarding dependent claim 15, Yu, further in view of Lim, Hsu, and Yu, teach the semiconductor package of claim 13; wherein:
a horizontal width and a horizontal area of the first semiconductor chip are equal to a horizontal width and a horizontal area of each of the first molding layer, the connection redistribution layer, the second molding layer, and the base redistribution layer (Yielded through the combination of Yu, further in view of Lim, Hsu, and Yu. See Fig. 2D of Yu).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Lim (US 20170012031 A1), Hsu et al. (US 10727198 B2), Yu et al. (US 20190074261 A1), and Yu et al. (US 20170170155 A1).
Regarding dependent claim 14, Yu, further in view of Lim, Hsu, and Yu, teach the semiconductor package of claim 13, wherein:
… a second active surface of each of the plurality of sub semiconductor chips (Lim: Fig. 8; active surfaces 172).
However, Yu remains silent wherein:
the plurality of sub- semiconductor chips are stacked on the first semiconductor chip such that a first active surface of the first semiconductor chip faces … a second active surface of each of the plurality of sub semiconductor chips.
However, in the same field of endeavor, Yu (US 20170170155 A1) discloses chip connectivity in Fig. 7; wherein the substrate 421 is considered to be a base redistribution layer ([0071]) and a fourth semiconductor device 107 is considered to be a first semiconductor chip. The connectively and orientation of Yu’s (US 20170170155 A1) 107 may be used to modify the first semiconductor ship of Yu, further in view of Lim, Hsu, and Yu, to yield the semiconductor package wherein the plurality of sub- semiconductor chips are stacked on the first semiconductor chip such that a first active surface of the first semiconductor chip faces a second active surface of each of the plurality of sub semiconductor chips.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the assembly of the semiconductor package of Yu, further in view of Lim, Hsu, and Yu, to include the structure and connectivity, wherein the plurality of sub- semiconductor chips are stacked on the first semiconductor chip such that a first active surface of the first semiconductor chip faces a second active surface of each of the plurality of sub semiconductor chips, disclosed by Yu (US 20170170155 A1), because such a modification is the result of applying a known technique to a known device ready for improvement to yield predictable results. More specifically, Yu’s (US 20170170155 A1) semiconductor package assembly permits signal sent between plurality of sub- semiconductor chips and the first semiconductor chip to travel with lower latency. This known semiconductor structure, as disclosed by Yu’s (US 20170170155 A1) semiconductor package assembly is applicable to the assembly of the semiconductor package of Yu, further in view of Lim, Hsu, and Yu, as they both share characteristics and capabilities, namely, they are directed to semiconductor packages. Therefore, it would have been recognized that modifying the assembly of the semiconductor package of Yu, further in view of Lim, Hsu, and Yu, to include the structure and connectivity, wherein the plurality of sub- semiconductor chips are stacked on the first semiconductor chip such that a first active surface of the first semiconductor chip faces a second active surface of each of the plurality of sub semiconductor chips, disclosed by Yu (US 20170170155 A1), would have yielded predictable results because (i) the level of ordinary skill in the art demonstrated by the references applied shows the ability to incorporate Lin’s semiconductor package assembly in semiconductor packages and (ii) the benefits of such a combination would have been recognized by those of ordinary skill in the art.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Keeth et al. (US 20110246746 A1), Chen et al. (US 20190148336 A1), and Hsu et al. (US 10727198 B2).
Regarding independent claim 18, Yu teaches a semiconductor package comprising:
a base redistribution layer (Fig. 16; redistribution structure 312);
a plurality of package connection members (Fig. 16; conductive connectors 314) attached to a lower surface of the base redistribution layer (Fig. 16 shows the conductive connectors 314 attached to a lower surface of the base redistribution layer, i.e., redistribution structure 312. See [0075]);
a connection redistribution layer (Fig. 16; redistribution structure 306) provided on the base redistribution layer (Fig. 16);
a first semiconductor chip (Figs. 1C, 10, and 16; memory device 60 of integrated circuit package 100 is interpreted to be a first semiconductor chip. See [0015] wherein Yu discloses that each of a first processor device 20, a second processor device 40, a memory device 60, and a passive device 80 is a bare integrated circuit die, i.e., a first semiconductor chip, or a packaged die) attached on the connection redistribution layer (Fig. 16) and having comprising a first active surface (Fig. 1C; active surface 62A);
…
a third semiconductor chip (Figs. 1B and 16; second processor device 40 of integrated circuit package 100 is interpreted to be a third semiconductor chip) provided between the base redistribution layer and the connection redistribution layer (Fig. 16);
a plurality of connection posts (Fig. 16; conductive vias 308) provided apart from each other in the horizontal direction (Fig. 16) between the base redistribution layer and the connection redistribution layer (Fig. 16), the plurality of connection posts being configured to electrically connect the base redistribution layer to the connection redistribution layer (Fig. 16); and
a second molding layer (Fig. 16; encapsulant 310) surrounding the third semiconductor chip and the plurality of connection posts (Fig. 16) between the base redistribution layer and the connection redistribution layer (Fig. 16),
wherein corresponding side surfaces of the first molding layer, the first semiconductor chip, the connection redistribution layer, the second molding layer, and the base redistribution layer are aligned with each other in the vertical direction (Fig. 16), …
wherein the third semiconductor chip comprises a graphics processing unit (GPU) chip (Yu teaches [0021] that second processor device 40 of integrated circuit package 100 may be a graphics processing unit (GPU)),
wherein the first semiconductor chip extends over both sides of the third semiconductor chip in the horizontal direction (Fig. 16),
wherein a portion of each of the at least two chip stacks overlaps the third semiconductor chip in the vertical direction (Fig. 16),
wherein the first semiconductor chip comprises a first through electrode (Figs. 1C and 10 – 11; die connectors 68 of the memory device 60), ...
However, Yu remains silent regarding:
at least two chip stacks, each chip stack of the at least two chip stacks comprising a plurality of second semiconductor chips having a second active surface facing the first active surface and stacked on the first semiconductor chip in a vertical direction, the at least two chip stacks being apart from each other in a horizontal direction;
a first molding layer configured to cover an upper surface of the first semiconductor chip and surrounding the at least two chip stacks;
…
wherein the first semiconductor chip and the plurality of second semiconductor chips constitute a high bandwidth memory (HBM), …
wherein, in a first stack of the at least two chip stacks, each of the plurality of second semiconductor chips comprises a second through electrode, and
wherein the first through electrode is vertically aligned with each second through electrode.
Examiner asserts that Yu’s first processor device 20 of integrated circuit package 100 (Figs. 1A, 9B, and 10 – 11) is a device added to be connected to Yu’s first semiconductor chip (Fig. 10; memory device 60 and [0046]); such as applicant’s instant, albeit of different structure, at least two chip stacks stacked on the first semiconductor chip in a vertical direction configured to be a device added to be connected to applicant’s first semiconductor chip. Further, examiner notes the related feature between Yu’s first semiconductor chip and first processor device 20 wherein both include through electrodes, first (die connectors 68 of the memory device 60) and second (die connectors 28 of the first processor device 20 taught to be conductive pillars in and/or on interconnect structure 24 in at least [0019]) through electrodes, respectively; and wherein the first through electrode is vertically aligned with each second through electrode (Fig. 10). From the above understanding, examiner concludes from Yu that a device may be added in a similar way to that of Yu’s first processor device 20, modifying Yu’s disclosed package structure.
Thus, in the same field of endeavor, Keeth describes stacked devices wherein an interface die 310 (analogous to Yu’s first semiconductor chip) has at least two chip stacks (Fig. 3; two dice stacks 302 and 325. Also see [0025]) stacked on the first semiconductor chip in a vertical direction (Fig. 3), each chip stack of the at least two chip stacks comprising a plurality of second semiconductor chips (e.g., dice 320, 321, 322, 323, 330, 331, 332, and 333) electrically connected to the first semiconductor chip (Fig. 3); further including the feature wherein, in a first stack of the at least two chip stacks, each of the plurality of second semiconductor chips comprises a second through electrode (Fig. 3; TSVs 304), and wherein the first through electrode is vertically aligned with each second through electrode (Fig. 3; wherein joints 308 are considered analogous to Yu’s first through electrode). Examiner asserts that through Yu’s disclosure, Keeth’s at least two chip stacks may be combined with Yu’s semiconductor package; thus, yielding a semiconductor package of Yu, further in view of Keeth, including:
... at least two chip stacks, each chip stack of the at least two chip stacks comprising a plurality of second semiconductor chips ... on the first semiconductor chip in a vertical direction, the at least two chip stacks being apart from each other in a horizontal direction; ...
wherein, in a first stack of the at least two chip stacks, each of the plurality of second semiconductor chips comprises a second through electrode, and
wherein the first through electrode is vertically aligned with each second through electrode.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s semiconductor package to include Keeth’s at least two chip stacks, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Keeth’s semiconductor package is comparable to Yu’s semiconductor package because they both include memory device (E.g., Yu’s chip 60 and Keeth’s at least two chip stacks). Therefore, it is within the capabilities of one of ordinary skill in the art to modify Yu’s semiconductor package to include Keeth’s at least two chip stacks with the predictable result of forming a package components with memory semiconductor devices.
However, Keeth discloses in [0016] that the formed memory device (Fig. 3) may be HBDRAM, i.e., high bandwidth memory (HBM); wherein Yu discloses that the memory device 60 may be DRAM. Examiner asserts that these technologies are analogous to each other, and therefore the modification of Yu, further in view of Keeth, is obvious.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s semiconductor package to include Keeth’s at least two chip stacks, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Keeth’s semiconductor package is comparable to Yu’s semiconductor package because they both include memory device (E.g., Yu’s chip 60 and Keeth’s at least two chip stacks). Therefore, it is within the capabilities of one of ordinary skill in the art to modify Yu’s semiconductor package to include Keeth’s at least two chip stacks with the predictable result of forming a package components with memory semiconductor devices.
Further, in the same field of endeavor, Chen teaches in Fig. 14 a package component 2 which may include a plurality of chips 4 therein; and wherein the device die 4 may be a memory die ([0012]). Further, Chen discloses in [0063] that die stacks 112 and device die 4 have face-to-face structure, i.e., a second active surface facing the first active surface.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor package of Yu, further in view of Keeth and Hsu, to include Chen’s face to face chip structure for a memory structure, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Chen’s first semiconductor chip and plurality of second semiconductor chips is comparable to the first semiconductor chip and plurality of second semiconductor chips of Yu, further in view of Keeth, because they’re both memory semiconductor devices. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor package of Yu, further in view of Keeth and Hsu, to include Chen’s face to face chip structure for a memory structure with the predictable result of forming a memory device structure.
Further, in the same field of endeavor, Hsu teaches a semiconductor package including semiconductor devices 200a and 200b; wherein the semiconductor devices, i.e., semiconductor devices 200a and 200b, have a similar style of attachment as Yu and Keeth’s combined first semiconductor chip and at least two chip stacks; however, Hsu teaches an underfill material 210, considered by the examiner to be analogous to the instant first molding layer, that fills gaps between the semiconductor devices 200a and 200b, and between the semiconductor devices 200a and 200b and the chips below, e.g., Hsu’s integrated circuit component 130. Thus, Hsu’s underfill material may be combined with the semiconductor package of Yu, further in view of Keeth, to yield a semiconductor package wherein:
… a first molding layer (Hsu: Fig. 24; underfill material 210) configured to cover an upper surface of the first semiconductor chip (Similar to Hsu’s Fig. 24 (showing the underfill material 210 between semiconductor devices 200a and 200b and integrated circuit component 130), the first molding layer, i.e., Hsu’s underfill material 210, filling the gap between Yu and Keeth’s first semiconductor chip and second semiconductor chip) and surrounding the at least two chip stacks (Similar to Hsu’s Fig. 24, showing the underfill material 210 surrounding the semiconductor devices 200a and 200b); …
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s semiconductor package, further in view of Keeth, to include Hsu’s underfill material as a mold, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Yu’s semiconductor package, further in view of Keeth, as modified by Hsu’s underfill material can yield a predictable result of stress relief on package components (Yu: [0065]). Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Keeth et al. (US 20110246746 A1), Chen et al. (US 20190148336 A1), Hsu et al. (US 10727198 B2), and Shimizu et al. (US 20160020163 A1).
Regarding dependent claim 19, Yu, further in view of Keeth and Hsu, teach the semiconductor package of claim 18; however, Yu remain silent wherein:
a thickness of the third semiconductor chip is in a range from about 30 µm to about 80 µm.
However, in the same field of endeavor, Shimizu teaches a semiconductor chip 101 that may be a graphics processing unit (GPU) chip, analogous to the instant third semiconductor chip; wherein Shimizu’s semiconductor chip 101 may be approximately 50 to 100 µm ([0082] – [0083]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s third semiconductor chip to include a thickness of the third semiconductor chip is in a range from about 30 µm to about 80 µm, as disclosed by Shimizu, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Yu’s semiconductor chip 101 is comparable to Yu’s third semiconductor chip because both disclose that the chips may function as GPUs. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Yu’s third semiconductor chip to include a thickness of the third semiconductor chip is in a range from about 30 µm to about 80 µm, as disclosed by Shimizu, with the predictable result of making the semiconductor package smaller; which leads to the reduction of necessary material needed to construct other package components such as conductive vias, such that the cost of production may be reduced.
Further, the thickness of the third semiconductor chip being somewhere in the range of 30 µm to 80 µm would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, from at least [0082] – [0083] of Shimizu, because absent evidence or disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d454, 105 USQ 233, 235 (CCPA 1995).
Additionally, the specification contains no disclosure of either the critical nature of the dimensions claimed or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the claimed dimensions or variable are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20210118859 A1), and further in view of Keeth et al. (US 20110246746 A1), Chen et al. (US 20190148336 A1), Hsu et al. (US 10727198 B2), and Ho (US 20010016370 A1).
Regarding dependent claim 20, Yu, further in view of Keeth and Hsu, teach the semiconductor package of claim 18, wherein:
… a lower surface of each of the plurality of connection posts, and a lower surface of the second molding layer are positioned at a same vertical level to be coplanar with each other and are in contact with an upper surface of the base redistribution layer (Yu: Fig. 16).
However, Yu remains silent wherein:
a non-active surface of the third semiconductor chip, … is coplanar with a lower surface of each of the plurality of connection posts and a lower surface of the second molding layer and in contact with an upper surface of the base redistribution layer.
However, in the same field of endeavor, Ho teaches in [0085] an integrated circuit die/ flip chip 16 disposed directly in contact with an interconnect substrate 12, i.e., a base redistribution layer; wherein the active surface is facing away from the base redistribution layer. Thus, the non-active surface of flip chip 16 is disposed in direct contact with the interconnect substrate 12, i.e., a base redistribution layer. Ho’s teaching for assembling package components may be applied to the assembly of Yu’s third semiconductor chip; such that a non-active surface of the third semiconductor chip is coplanar with a lower surface of each of the plurality of connection posts and a lower surface of the second molding layer and in contact with an upper surface of the base redistribution layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yu’s third semiconductor chip to include Ho’s teaching of a semiconductor chip having a non-active surface in contact with an upper surface of the base redistribution layer, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Ho’s assembly of an integrated circuit die/ flip chip in a semiconductor package is comparable to Yu’s assembly of the third semiconductor chip in a semiconductor package, because both disclosures teach a method of forming a semiconductor package structure. However, the difference between the disclosure lies in the orientation and connectivity of the semiconductor chips, wherein the examiner asserts that both methods between the two disclosure are applicable to Yu’s assembly of the third semiconductor chip in a semiconductor package. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Yu’s third semiconductor chip to include Ho’s teaching of a semiconductor chip having a non-active surface in contact with an upper surface of the base redistribution layer, with the predictable result of a non-active surface of the third semiconductor chip, a lower surface of each of the plurality of connection posts, and a lower surface of the second molding layer are positioned at a same vertical level to be coplanar with each other.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20210043606 A1 previously relied upon.
US 10515848 B1 previously relied upon.
US 11004826 B2 claims in claim 16 of their disclosure a width of the second encapsulant is equal to widths of the second redistribution structure, the first encapsulant, and the first redistribution structure.
US 20160240480 A1 discloses a similar semiconductor package (Fig. 24).
US 10297571 B2 discloses a memory device including a stack of semiconductor chips shifted stepwise in the horizontal direction (Fig. 4).
US 20190304955 A1 discloses relevant teaching for face-up and face-down semiconductor chips.
US 20230054984 A1 teaches similar width and areas of chips in a semiconductor package.
US 10163750 B2 teaches similar width and areas of chips in a semiconductor package.
US 10276545 B1 discloses relevant teaching for face-up and face-down semiconductor chips.
US 20190341376 A1 teaches a semiconductor chip 102 over a semiconductor chip 104; wherein the width of semiconductor chip 102 is greater than the width of semiconductor chip 104; and the width of semiconductor chip 102 is equal to the width of the redistribution layer 116 (Fig. 5).
US 20240258286 A1 teaches similar width and areas of chips in a semiconductor package (Fig. 12).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARIO A. AUTORE JR.
Examiner
Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897