DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Amendment filed June 3, 2025 has been fully considered and entered.
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement(s) filed on January 9, 2026 and July 30, 2026 have all been considered and made of record (note the attached copies of form PTO-1449).
Drawings
The replacement drawing sheets were received on June 3, 2025. These drawings are acceptable.
Specification
Applicant’s Amendment to the specification filed June 3, 2025 has been accepted.
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to Arguments
Applicant’s arguments filed June 3, 2025 have been fully considered and are responded to as follows:
Doerr’s FIG. 7B does not illustrate edge-coupling
Applicant argues that Doerr’s FIG. 7B does not teach edge-coupling and instead teaches surface-coupling.
The Examiner agrees. Therefore, the rejection has been withdrawn. However, newly cited reference “Patel” teaches a thermal lid with a fiber passage therethrough and edge-coupling a fiber passed through the lid to a PIC and has been applied in the present office action to properly address the claim limitations in question.
Modifying Decker to enable fiber edge-coupling would have impermissibly changed Decker’s principle of operation
Applicant argues that no modification of Decker would have resulted in an edge-coupled fiber to the PIC because the principle of operation of Decker’s package is surface-coupling.
The Examiner disagrees. The teachings of Decker are being applied in the present office action for the structure including the relative location and connection of components including the ASIC, interposer, and PIC. Elements of Decker’s teachings are directed to surface-coupling into the PIC from an optical-fiber assembly, but both surface-coupling and edge-coupling are well-known in the PIC art and are simply alternative means for coupling an optical signal into a PIC. The modification between surface-coupling and edge-coupling is understood by a person of ordinary skill in the art based on the package structure and the requirements of the specific PIC. Further, Decker teaches edge-coupling (horizontal) in Paragraph [0040], “Furthermore, FIGS. 1 and 2 may be used with edge (or horizontal) coupling or vertical coupling of optical-fiber assembly 140. As noted previously, horizontal coupling may involve the use of additional mirrors, lenses and/or optical coupling elements.”
Applicant further argues that due to the placement of the PIC in the etched pit taught by Decker it would have been impractical if not impossible to edge-couple a fiber into the PIC.
The Examiner disagrees. Decker teaches in Paragraph [0040] “Furthermore, FIGS. 1 and 2 may be used with edge (or horizontal) coupling or vertical coupling of optical-fiber assembly 140. As noted previously, horizontal coupling may involve the use of additional mirrors, lenses and/or optical coupling elements.”
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ghiasi (US 10866376 B1) in view of Patel et al. (US 20200319416 A1), hereafter Patel.
Regarding claim 1; Ghiasi teaches (see Figure 3A) An electronic-photonic package (title) comprising: a substrate (200) having an opening (204) defined therethrough; an application specific integrated circuit (ASIC) (106) and a photonic integrated circuit (PIC) (300), wherein a first chip (106) selected from the ASIC (106) and the PIC (300) is disposed in the opening (204); an interposer (100), wherein the first chip (106) is coupled to a first side (bottom) of the interposer (100) and a second chip (300) selected from the ASIC (106) and the PIC (300) is coupled to a second side (top) of the interposer (100) opposite the first side (bottom); a heat spreader (201) disposed in the opening (204) and in thermal contact with the first chip (106; Paragraph [0023]).
Ghiasi does not teach a thermally conductive lid in thermal contact with the second chip, wherein the thermally conductive lid has a fiber passage defined therethrough, and wherein a fiber passing through the fiber passage is configured to edge-couple to the PIC. However, in the same field of endeavor Patel teaches (see Figure 2A) a thermally conductive lid (210; “a frame lid is mounted above the ASIC in order to provide protection as well as heat dissipation” (Paragraph [0005])) in thermal contact (via thermal interface material 160c) with the second chip (PIC 150), wherein the thermally conductive lid (210) has a fiber passage (slot 230; Paragraph [0032]) defined therethrough, and wherein a fiber (170) passing through the fiber passage (slot 230) is configured to edge-couple (fiber 170 is edge-coupled to PIC 150; see Figure 2A) to the PIC (150). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the electronic photonic package taught by Ghiasi to include the thermally conductive lid with a passage for a fiber and to edge couple the fiber to the PIC as taught by Patel. One of ordinary skill in the art would have been motivated to make this modification because Patel teaches that the lid provides protection as well as heat dissipation in Paragraph [0005].
Regarding claim 2; Ghiasi/Patel teaches the electronic-photonic package of claim 1. Ghiasi further teaches (see Figure 3A) wherein the opening (204) is defined from a top surface of the substrate (200) to a bottom surface of the substrate (200; the opening 204 is bounded by the stiffeners 103 and can be seen in Figure 3A).
Regarding claim 4; Ghiasi/Patel teaches the electronic-photonic package of claim 1. Ghiasi further teaches (see Figure 3A) wherein the first chip (106) is disposed at least partially in the opening (204; As seen by the dashed line in Figure 3A 106 is disposed partially in the opening 204).
Regarding claim 9; Ghiasi/Patel teaches the electronic-photonic package of claim 1. Ghiasi further teaches wherein the electronic-photonic package lacks lasers disposed therein (in Figure 3A fibers 301 can be used to input laser light to PIC 300 so the package can lack lasers disposed therein).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ghiasi in view of Patel as applied to claim 1 above, and further in view of Byrd et al. (US 20190044002 A1), hereafter Byrd.
Regarding claim 7; Ghiasi/Patel teaches the electronic-photonic package of claim 1. Ghiasi further teaches (see Figure 3A) wherein the substrate (200) has a top surface (top of 200) facing the interposer (100) and a bottom surface (bottom of 200).
Ghiasi/Patel does not teach wherein the electronic-photonic package further comprise land grid array (LGA) pads coupled to the bottom surface of the substrate. However, in the same field of endeavor, Byrd teaches (see Figure 1) wherein the electronic-photonic package further comprise land grid array (LGA) pads (lang grid array 137; Paragraph [0040]) coupled to the bottom surface of the substrate (130). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the electronic-photonic package taught by Ghiasi/Patel to include the LGA pads on the bottom surface of the substrate as taught by Byrd. One of ordinary skill in the art would have been motivated to make this modification to allow for the electronic-photonic package to be connected to a printed circuit board as taught by Byrd in Paragraph [0040].
Claims 8, 10-11, and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ghiasi in view of Patel as applied to claim 1 above, and further in view of Lin et al. (US 20210064958 A1), hereafter Lin.
Regarding claim 8; Ghiasi/Patel teaches the electronic-photonic package of claim 1. Ghiasi/Patel does not teach wherein the PIC comprises a photonic accelerator configured to perform matrix multiplication in an optical domain, and wherein the ASIC comprises a digital controller configured to control the photonic accelerator. However, in the same field of endeavor, Lin teaches (see Figure 11; abstract) wherein the PIC (1100) comprises a photonic accelerator (1105) configured to perform matrix multiplication (Paragraph [0073]) in an optical domain, and wherein the ASIC (1102) comprises a digital controller (1102) configured to control (Paragraph [0084]) the photonic accelerator (1105). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the electronic-photonic package taught by Ghiasi/Patel to include the PIC components and corresponding ASIC control components taught by Lin. One of ordinary skill in the art would have been motivated to make these modifications to form an optical neural network device using the structure of the Ghiasi/Patel device.
Regarding claim 10; Ghiasi teaches (see Figure 3A) an electronic-photonic processor (title) comprising: a plurality of photonic integrated circuits (PICs) (300); an ASIC (106) configured to control the PICs (106); an interposer (100), wherein the plurality of PICs (300) are coupled to a first side (top) of the interposer (100) and the ASIC (106) is coupled to a second side (bottom) of the interposer (100) opposite the first side (PIC 300 and ASIC 106 are on opposite sides of the interposer 100); and a second thermally conductive member (201) in thermal contact with the ASIC (106), wherein the second thermally conductive member (201) faces the second side (is on the bottom side) of the interposer (100).
Ghiasi does not teach a thermally conductive lid in thermal contact with the second chip, wherein the thermally conductive lid has a fiber passage defined therethrough, wherein a fiber passing through the fiber passage is configured to edge-couple to the PIC, and wherein the first thermally conductive member faces the first side of the interposer. However, in the same field of endeavor Patel teaches (see Figure 2A) a thermally conductive lid (210; “a frame lid is mounted above the ASIC in order to provide protection as well as heat dissipation” (Paragraph [0005])) in thermal contact (via thermal interface material 160c) with the second chip (PIC 150), wherein the thermally conductive lid (210) has a fiber passage (slot 230; Paragraph [0032]) defined therethrough, and wherein a fiber (170) passing through the fiber passage (slot 230) is configured to edge-couple (fiber 170 is edge-coupled to PIC 150; see Figure 2A) to the PIC (150). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the electronic photonic package taught by Ghiasi to include the thermally conductive lid with a passage for a fiber and to edge couple the fiber to the PIC as taught by Patel. Modified Ghiasi with the thermally conductive lid placed over the PIC as taught by Patel would have the first thermally conductive member (thermal lid) on the first side (top) of the interposer (100). One of ordinary skill in the art would have been motivated to make this modification because Patel teaches that the lid provides protection as well as heat dissipation in Paragraph [0005].
Ghiasi/Patel does not teach wherein each PIC comprising a photonic accelerator configured to perform matrix multiplication in an optical domain; an application specific integrated circuit (ASIC) configured to control at least one of the photonic accelerators. However, in the same field of endeavor, Lin teaches (see Figure 11) a PIC (1100) comprising a photonic accelerator (1105) configured to perform matrix multiplication (Paragraph [0073]) in an optical domain; an application specific integrated circuit (ASIC) (1102) configured to control (Paragraph [0084]) at least one of the photonic accelerators (1105). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the electronic-photonic package taught by Ghiasi/Patel to include the PIC components and corresponding ASIC control components taught by Lin. One of ordinary skill in the art would have been motivated to make these modifications to form an optical neural network device using the structure of the Ghiasi/Patel device.
Regarding claim 11; Ghiasi/Patel/Lin teaches the electronic-photonic processor of claim 10. Ghiasi further teaches (see Figure 3A) comprising a substrate (200) having an opening (204) formed therethrough, wherein the interposer (100) is mounted on the substrate (200), and wherein either the first thermally conductive member (thermal lid, see rejection to claim 10 above) or the second thermally conductive member (201) is disposed in the opening (204; Ghiasi shows in Figure 3A the second thermally conductive member (201) is disposed in the opening 204).
Regarding claim 13; Ghiasi/Patel/Lin teaches the electronic-photonic processor of claim 11, wherein the second thermally conductive member (201) is in contact with the substrate (200; see Figure 3A second thermally conductive member 201 is in contact with substrate 200).
Regarding claim 14-16; Ghiasi/Patel/Lin teaches the electronic-photonic processor of claim 10. Ghiasi/Patel/Lin as applied to claim 10 above teaches (see Lin Figure 11 and rejection to claim 10 above) wherein the further comprising a digital controller (1102) is configured to control the photonic accelerators (1105) to perform matrix multiplication (Paragraph [0073]) in the optical domain, but does not teach matrix multiplication in parallel on a tile-by-tile basis, wherein the photonic accelerators comprise photonic multipliers configured to perform scalar multiplications in the optical domain, nor wherein the photonic accelerators comprise photonic adders configured to perform scalar additions in the optical domain. Lin further teaches (see Figure 9) matrix multiplication in parallel on a tile-by-tile basis (MMI couplers are in parallel to do matrix multiplication (Paragraph [0060])), photonic multipliers configured to perform scalar multiplications (Paragraph [0022-0023]), and photonic adders configured to perform scalar additions (Paragraph [0022-0023]). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the photonic accelerators in Ghiasi/Patel/Lin as applied to claim 10 above perform matrix multiplication in parallel on a tile-by-tile basis, to perform scalar multiplication and to perform scalar addition as taught by Lin to perform optical neural network calculations more efficiently.
Regarding claim 17; Ghiasi/Patel/Lin teaches the electronic-photonic processor of claim 10. Ghiasi/Patel/Lin as applied to claim 10 above (see rejection to claim 10 above) further teaches wherein the plurality of PICs (300), the ASIC (106), the interposer (100), and the first (thermal lid; see rejection to claim 10 above) and second (201) thermally conductive members form a package (entirety of components constitute a package), and wherein the electronic-photonic processor further comprises a laser disposed outside the package (Ghiasi shows fibers 301 to input light to PICs 300 from outside the package shown in Figure 3A).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ghiasi in view of Patel and further in view of Lin as applied to claim 11 above, and further in view of Byrd.
Regarding claim 12; Ghiasi/Patel/Lin teaches the electronic-photonic processor of claim 11. Ghiasi further teaches (see Figure 3A) wherein the substrate (200) has a top surface (top of 200) facing the interposer (100) and a bottom surface (bottom of 200).
Ghiasi/Patel/Lin does not teach wherein the electronic-photonic processor further comprise land grid array (LGA) pads coupled to the bottom surface of the substrate. However, in the same field of endeavor, Byrd teaches (see Figure 1) wherein the electronic-photonic package further comprise land grid array (LGA) pads (lang grid array 137; Paragraph [0040]) coupled to the bottom surface of the substrate (130). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the electronic-photonic package taught by Ghiasi/Patel to include the LGA pads on the bottom surface of the substrate as taught by Byrd. One of ordinary skill in the art would have been motivated to make this modification to allow for the electronic-photonic package to be connected to a printed circuit board as taught by Byrd in Paragraph [0040].
Claim(s) 1, 3, and 19-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Decker et al. (US 20160085038 A1), hereafter Decker, in view of Patel.
Regarding claims 1; Decker discloses an electronic-photonic package (Fig. 1) comprising:
a substrate (144, Fig. 1) having an opening (106, Fig. 1) defined therethrough;
an application specific integrated circuit (ASIC) (110, Fig. 1) and a photonic integrated circuit (PIC) (134, Fig. 1),
wherein a first chip between the ASIC (110) and the PIC (134) is disposed in the opening (106) (The PIC (134) is disposed in the opening);
an interposer (118, Fig. 1), wherein the first chip (PIC, 134) is coupled to a first side (124, Fig. 1) of the interposer (118) and a second chip between the ASIC (110) and the PIC (134) is coupled to a second side (122, Fig. 1) of the interposer (118) opposite the first side (The ASIC (110) is coupled to a second side (122) of the interposer (118) opposite the first side (124), see Fig. 1);
a heat spreader (146, Fig. 1) disposed in the opening (106) and in thermal contact with the first chip (134); and a thermally conductive lid (HEAT SINK AND THERMAL PADS, Fig. 1) in thermal contact with the second chip (110).
Decker does not teach wherein the thermally conductive lid has a fiber passage defined therethrough, and wherein a fiber passing through the fiber passage is configured to edge-couple to the PIC, but does teach in Paragraph [0040] “Furthermore, FIGS. 1 and 2 may be used with edge (or horizontal) coupling or vertical coupling of optical-fiber assembly 140. As noted previously, horizontal coupling may involve the use of additional mirrors, lenses and/or optical coupling elements”. However, in the same field of endeavor Patel teaches (see Figure 2A) a thermally conductive lid (210; “a frame lid is mounted above the ASIC in order to provide protection as well as heat dissipation” (Paragraph [0005])) in thermal contact (via thermal interface material 160c) with the second chip (PIC 150), wherein the thermally conductive lid (210) has a fiber passage (slot 230; Paragraph [0032]) defined therethrough, and wherein a fiber (170) passing through the fiber passage (slot 230) is configured to edge-couple (fiber 170 is edge-coupled to PIC 150; see Figure 2A) to the PIC (150). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the electronic photonic package taught by Decker to replace the HEAT SINK AND THERMAL PADS with the thermally conductive lid with a passage for a fiber and to edge couple the fiber to the PIC as taught by Patel. One of ordinary skill in the art would have been motivated to make this modification because Patel teaches that the lid provides protection as well as heat dissipation in Paragraph [0005].
Regarding claim 3; Decker/Patel teach the electronic-photonic package of claim 1. Decker further teaches (see Figure 1) wherein the first chip (134) is the PIC (134) and the second chip (110) is the ASIC (110), such that the heat spreader (HEAT SINK 146) is in thermal contact with the PIC (134) and the thermally conductive lid (thermal lid taught by Patel; see rejection to claim 1 above) is in thermal contact with the ASIC (110).
Regarding claim 19; Decker discloses a method for fabricating an electronic-photonic package (Fig. 1), comprising: obtaining a substrate (144, Fig. 1), an application-specific integrated circuit (ASIC) (110. Fig 1), a photonic integrated circuit (PIC) (134, Fig. 1), and an interposer (118, Fig. 1); forming an interposer module by attaching the ASIC (110) to a first side of the interposer (118) and the PIC (134) to a second side of the interposer (118); attaching the interposer module to the substrate (144); placing a first thermally conductive member (HEAT SINK AND THERMAL PADS, Fig. 1) in thermal contact with the ASIC (110); and placing a second thermally conductive member (146, Fig. 1) in thermal contact with the PIC (134).
Decker does not teach wherein the thermally conductive lid has a fiber passage defined therethrough, and wherein a fiber passing through the fiber passage is configured to edge-couple to the PIC, but does teach in Paragraph [0040] “Furthermore, FIGS. 1 and 2 may be used with edge (or horizontal) coupling or vertical coupling of optical-fiber assembly 140. As noted previously, horizontal coupling may involve the use of additional mirrors, lenses and/or optical coupling elements”. However, in the same field of endeavor Patel teaches (see Figure 2A) a thermally conductive lid (210; “a frame lid is mounted above the ASIC in order to provide protection as well as heat dissipation” (Paragraph [0005])) in thermal contact (via thermal interface material 160c) with the second chip (PIC 150), wherein the thermally conductive lid (210) has a fiber passage (slot 230; Paragraph [0032]) defined therethrough, and wherein a fiber (170) passing through the fiber passage (slot 230) is configured to edge-couple (fiber 170 is edge-coupled to PIC 150; see Figure 2A) to the PIC (150). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the electronic photonic package taught by Decker to replace the HEAT SINK AND THERMAL PADS with the thermally conductive lid with a passage for a fiber as taught by Patel. One of ordinary skill in the art would have been motivated to make this modification because Patel teaches that the lid provides protection as well as heat dissipation in Paragraph [0005].
Regarding claims 20-22; Decker/Patel teaches the method of claim 19. Decker further teaches (see Figure 1) comprising: forming a first underfill on the first side of the interposer (118) (Par. 55); flipping the interposer (118); and subsequent to flipping, forming a second underfill on the second side of the interposer (118) (Par. 56). Wherein placing the second thermally conductive member (146) in thermal contact with the PIC (134) comprises inserting the second thermally conductive member (146) through an opening (106, Fig. 1) formed in the substrate (144). Further comprising flipping the substrate (144), so that placing the first thermally conductive member (thermal lid as taught by Patel applied to claim 19 above) in thermal contact with the ASIC (110) is performed prior to flipping the substrate (144) and placing the second thermally conductive member (146) in thermal contact with the PIC (134) is performed after flipping the substrate (144).
Claims 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Decker in view of Patel as applied to claim 1 above, and further in view of Ghiasi.
Regarding claim 23; Decker/Patel teaches the electronic-photonic package of claim 1. Decker/Patel does not teach wherein the PIC is raised relative to a top surface of the substrate. However, Ghiasi teaches (see Figure 3A), wherein the first chip (ASIC 106 in the case of Ghiasi) is disposed in the hole (204) and raised relative to the top surface of the substrate (200; see Figure 3A). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to raise the chip in the hole (the PIC in the case of Decker) to be partially out of the hole to allow for easier edge-coupling into the chip.
Regarding claim 24; Decker/Patel/Ghiasi teach the electronic-photonic package of claim 23. Decker further teaches (see Figure 1) wherein the interposer (118) sits in part on the top surface of the substrate (144) and in part on the PIC (134).
Regarding claim 25; Decker/Patel/Ghiasi teach the electronic-photonic package of claim 24. Decker does not teach further comprising: a first set of connections coupling the interposer to the substrate and a second set of connections coupling the interposer to the PIC, wherein the first set of connections have different sizes with respect to the second set of connections. However, in the same field of endeavor, Ghiasi teaches (see Figure 3A) a first set of connections (203) coupling the interposer (100) to the substrate (200) and a second set of connections (BGA 109; see Figure 1A) coupling the interposer (100) to the PIC (300; BGA 109 and LGA socket 110 connect PIC 300 to interposer 100), wherein the first set of connections (203) have different sizes with respect to the second set of connections (109; it can be seen in Figure 3A that the BGAs 203 are larger than the BGAs 109). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the BGAs taught by Decker to have different sizes as taught by Ghiasi. One of ordinary skill in the art would have been motivated to have different sized BGA connections to allow for increased/decreased current flow to the different components in the electronic-photonic package taught by Decker.
Conclusion
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/P.L.K./Examiner, Art Unit 2874
/MICHELLE R CONNELLY/Primary Examiner, Art Unit 2874
