DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings. The objections to the drawings are withdrawn based on argument and amendment to claims.
35 USC 112(b). Applicant asserts that the claims have been amended for clarity therefore the rejections under 35 USC 112(b) should be withdrawn. With the exception of the following, the rejections under 35 USC 112(b) are withdrawn based on amendment to claims:
Claim 7 and 17 recite “the original input data matrix outputs the feature data matrix through the filter matrix and the GEMM operation”. As stated on p. 4 of the nonfinal office action, it is unclear how original data matrix can output a feature data matrix, or how it is output through a filter matrix and GEMM operation. This limitation, having not been amended results in the rejection under 35 USC 112(b) being maintained.
35 USC 101. The rejection under 35 USC 101 is withdrawn based on amendment to claims.
35 USC 103.
Applicant asserts that Espig does not teach or suggest every feature of claim 11, specifically that Espig does not disclose a “first data of a first component and second data of a second component” and the “first component and the second component are in the input data matrix” (Remarks p. 15). Applicant asserts that Espig discloses common data elements are allowed to span two input matrices (Remarks p. 15). Applicant further asserts that neither Warden nor Lecture 11 disclose these limitations (Remarks p. 16).
Examiner respectfully disagrees. Although Espig allows common data elements to span two input matrices, Espig does also disclose common data elements in one input matrix (Espig fig 3 data in overlapping fields in in physical input matrix 1301, such as field 6 for first component and field 7 for second component), wherein the first component and the second component are in the input data matrix (the first and second data of fields 6 and 7 both in the single input matrix 1301. Furthermore, Examiner relies neither on Warden nor Lecture 11 for these limitations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-8, and 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7, and claim 17 lines recite “the original input data matrix outputs the feature data matrix through the filter matrix and the GEMM operation.” It is unclear how original input data matrix can output a feature data matrix, or how it is output through a filter matrix and GEMM operation. For purposes of examination, Examiner interprets as the input data is stored into a memory region. Furthermore, for purposes of examination, Examiner interprets as the processor outputs the original input data matrix as the feature data matrix as associated with the filter matrix and for a GEMM operation. Claim 8 inherits the same deficiency as claim 7 based on dependence. Claim 18 inherits the same deficiency as claim 17 based on dependence.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As to treatment of claims, the apparatus claims will be addressed first followed by the method and computer-readable recording medium claims.
Claims 1 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190042262 A1 Espig et al., (hereinafter “Espig”) in view of Lecture 11: Modern Superscalar Processor Models, Iowa State University, 2005, found at https://home.engineering .iastate.edu/~zzhang/courses/cpre585-f04/slides/lecture11.pdf (hereinafter “lecture 11”), in view of P. Warden, Why GEMM is at the heart of deep learning, Pete Warden’s blog, 2015, found at https://petewarden.com/2015/04/20/why-gemm-is-at-the-heart-of-deep-learning/ (hereinafter “Warden”).
Regarding claim 11, Espig teaches the following:
a memory storing a register map (fig 4B physical register files units 458 for memory [0087], register maps); and
a processor configured to perform a general matrix multiplication (GEMM) operation on an input data matrix with a filter matrix ([0130]),
update a register map so that first destination register addresses of redundant components indicating data redundant with each other among a plurality of components of the input data matrix correspond to a same second destination register address ([0134], fig 13, physical input matrix for first destination register address, virtual input matrix for second destination register address, rows of the respective matrices 1311-1314 for plurality of components, [0135] common data elements are reused), the data redundant comprising first data of a first component and second data of a second component (fig13, data in overlapping fields in in physical input matrix 1301, such as field 6 for first component and field 7 for second component), wherein the first component and the second component are in the input data matrix (the first and second data of fields 6 and 7 both in the single input matrix 1301); and
perform the convolutional operation by reusing a register having the same second destination register address with respect to the redundant components, based on the register map (fig 14A-C, fig 15, [0130], [0139-0143], [0158]].
Espig discloses register maps, but does not explicitly disclose a register mapping table or wherein the reusing a register is based on the register mapping table. Espig further does not explicitly disclose wherein the GEMM operation is used in performing a convolution operation for generating a feature data matrix corresponding to an output data matrix.
However, in the same field of endeavor, a mechanism for mapping from virtual architectural registers to physical registers using a register mapping table (slide 6, slide 8). It would have been obvious to one of ordinary skill in the art before the effective filing date, to use as the mechanism for register mapping as disclosed by Espig, the register mapping table as disclosed in Lecture 11. It is obvious to use a known technique to improve similar devices in the same way. See MPEP 2141.III.(C). Therefore Espig in view of Lecture II teaches a memory storing a register mapping table, and wherein the reusing a register is based on the register mapping table.
Furthermore Warden discloses wherein the GEMM operation is used in performing a convolution operation for generating a feature data matrix corresponding to an output data matrix (How GEMM works for Convolutions section). It would have been obvious to one of ordinary skill in the art before the effective filing data to use the GEMM operation as disclosed by Espig for performing a convolution operation for generating a feature data matrix corresponding to an output data matrix as disclosed by Warden, to achieve the benefit of very regular patterns of memory access (Why GEMM works for Convolutions section). Therefore Espig in view of Warden teaches wherein the GEMM operation is used in performing a convolution operation for generating a feature data matrix corresponding to an output data matrix, and Espig in view of Lecture 11 in view of Warden teaches the claim 11 limitations.
Claim 1 is directed to a method that would be practiced by the apparatus as in claim 11. All steps performed by the method as in claim 1 is performed by the apparatus as in claim 11 as configured. The claim 11 analysis applies equally to claim 1.
Claim 10 is directed to a computer program stored in a computer-readable recording medium that would execute the method as in claim 1. All steps performed by the method as in claim 1 are executed by the computer program stored in a computer-readable recording medium as in claim 10. The claim 1 analysis applies equally to claim 10.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Espig in view of Lecture 11 in view Warden in view of J. Jeon et al., Locality-aware GPU Register File, IEEE Computer Architecture Letters. 2019 (hereinafter “Jeon”).
Regarding claim 12, Espig in view of lecture 11 in view of Warden teach the claim 11 limitations. Espig in view of lecture 11 in view of Warden do not explicitly disclose wherein the processor is further configured to generate an identifier of the plurality of components; and update the register mapping table so that first destination register addresses of components for which a same identifier is generated among the plurality of components correspond to a same second destination register address. However in the same field of endeavor Jeon discloses:
wherein the processor is further configured to generate an identifier of the plurality of components; and update the register mapping table so that first destination register addresses of components for which a same identifier is generated among the plurality of components correspond to a same second destination register address (figure 3 one of the tables inside the register renaming module, section 3, first paragraph register id for identifier).
It would have been obvious to one of ordinary skill in the art before the effective filing date to update the register mapping table of Espig in view of lecture 11 in view of Warden using the identifier as in Jeon. It would have been obvious to achieve the benefit of mapping multiplier entries of physical registers to multiple architectural registers (Section 3 first paragraph).
Claim 2 is directed to a method that would be practiced by the apparatus as in claim 12. All steps performed by the method as in claim 2 is performed by the apparatus as in claim 12 as configured. The claim 12 analysis applies equally to claim 2.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Espig in view of Lecture 11 in view Warden in view of US 20220066960 A1 Park et al., (hereinafter “Park”).
Regarding claim 17, Espig in view of lecture 11 in view of Warden teach the claim 1 limitations. Espig in view of lecture 11 in view of Warden do not explicitly disclose wherein the processor is further configured to generate the input data matrix stored into a memory region corresponding to a workspace, wherein generating the input data matrix is performed by changing (i) a size of an original input data matrix and (ii) a number and an order of a plurality of components, wherein the input data matrix is a matrix in which the plurality of components of the original input data matrix are recombined and arranged with a rule so that the original input data matrix outputs the feature data matrix through the filter matrix and the GEMM operation. However in the same field of endeavor Park discloses:
wherein the processor is further configured to generate the input data matrix stored into a memory region corresponding to a workspace, wherein the generating the input data matrix is performed by (i) changing a size of an original input data matrix and (ii) a number and an order of a plurality of components (fig 5, [0058-0061]),
wherein the input data matrix is a matrix in which the plurality of components of the original input data matrix are recombined and arranged with a rule so that the original input data matrix outputs the feature data matrix through the filter matrix and the GEMM operation (fig 5, [0058-0061], the rule being changing the size based on the spatial size of the filter).
It would have been obvious to one of ordinary skill in the art before the effective filing date to generate the input data matrix into a memory region according to Park, and to recombine and rearrange with a rule as in Park for a GEMM operation associated with the filter matrix as in Espig in view of lecture 11 in view of Warner. It would have been obvious to achieve the benefit of not overlapping redundant data in memory ([0061]).
Claim 7 is directed to a method that would be practiced by the apparatus as in claim 17. All steps performed by the method as in claim 7 is performed by the apparatus as in claim 17 as configured. The claim 17 analysis applies equally to claim 7.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Espig in view of Lecture 11 in view Warden in view of Park in view of US 20190205735 A1 Smelyanskiy et al, (hereinafter “Smelyanskiy”).
Regarding claim 18, Espig in view of lecture 11 in view of Warden in view of Park teach the claim 17 limitations. Espig in view of lecture 11 in view of Warden in view of Park do not explicitly disclose wherein the processor is further configured to generate the input data matrix by converting the original input data matrix into the workspace having a same number of rows as a number of rows of the feature data matrix and a same number of columns as a size of the filter matrix.. However in the same field of endeavor Smelyanskiy discloses:
wherein the processor is further configured to generate the input data matrix by converting the original input data matrix into the workspace having a same number of rows as a number of rows of the feature data matrix and a same number of columns as a size of the filter matrix (fig 4B, [0048-0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to generate the input data matrix of Espig in view of lecture 1 in view of Warden in view of Park using the lowering procedure as disclosed by Smelyanskiy. It would have been obvious to achieve the benefit of allowing a GEMM operation to be performed for a convolution ([0048]).
Claim 8 is directed to a method that would be practiced by the apparatus as in claim 18. All steps performed by the method as in claim 8 is performed by the apparatus as in claim 18 as configured. The claim 18 analysis applies equally to claim 8.
Allowable Subject Matter
For the reasons set forth in the nonfinal office action dated 02/18/26, claims 3-6, 9,13-16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EMILY E LAROCQUE/Examiner, Art Unit 2182
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