Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on re hah has been entered.
Response to Amendment
Applicant’s arguments filed 12/04/2025 have been fully considered but they are not persuasive.
The applicant argues that Miyake does not disclose the limitation as presented in claim 1. The examiner respectfully disagrees. Miyake (figures 1A-5C) discloses a display substrate as claimed including data lines and gate lines crossing and insulated from the data lines (135-136), wherein each sub-pixel is provided with a thin film transistor (431 or 434) and a pixel electrode (125; figures 3 and 4B), a gate electrode of the thin film transistor is coupled to a corresponding gate line, a source electrode of the thin film transistor is coupled to a corresponding data line, and a drain electrode of the thin film transistor is coupled to the pixel electrode (figure 4A); and in a plurality of pixel units in a same row, the source electrodes of the thin film transistors of the sub-pixels in different colors are coupled to different data lines, the gate electrode of the thin film transistor of each sub-pixel is coupled to a same gate line adjacent to the pixel units in the row (figures 4A and 4B), or coupled to at least two gate lines adjacent to the pixel units in the row, and the gate electrodes of the thin film transistors of the sub-pixels in a same color are coupled to a same gate line; wherein in at least one of the first peripheral display region and the second peripheral display region, at least one gate line branch is further arranged on and cross-coupled to each gate line, and the source electrode of the thin film transistor of the sub-pixel in at least one color in the pixel unit is coupled to the gate line branch (portion of gate lines 137 and the gate electrodes, and source electrode is coupled to the TFT and therefore the gate line branch).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 7-8, 10-11, 14, 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyake (US 2015/0076473).
Regarding claim 1, Miyake (figures 1A-5C) discloses a display substrate, comprising a middle display region, and a first peripheral display region and a second peripheral display region arranged at two opposite sides of the middle display region respectively (170 and 160), wherein each display region comprises an array of pixel units, each pixel unit comprises at least two sub-pixels emitting light in different colors (RGB), and an aperture of each sub-pixel is of a rectangular shape comprising a long side and a short side (figure 1F);
wherein in at least one of the first peripheral display region and the second peripheral display region and in the middle display region (160 and 170), the sub-pixels in each pixel unit are sequentially arranged along a short side extension direction of the sub-pixel, an extension direction of the first peripheral display region and an extension direction of the second peripheral display region are perpendicular to a short side extension direction of the sub-pixel in the middle display region, and a short side extension direction of the sub-pixel in at least one of the first peripheral display region and the second peripheral display region is perpendicular to the short side extension direction of the sub-pixel in the middle display region (160 and 170; figure 1F);
data lines and gate lines crossing and insulated from the data lines (135-136), wherein each sub-pixel is provided with a thin film transistor (431 or 434) and a pixel electrode (125; figures 3 and 4B), a gate electrode of the thin film transistor is coupled to a corresponding gate line, a source electrode of the thin film transistor is coupled to a corresponding data line, and a drain electrode of the thin film transistor is coupled to the pixel electrode (figure 4A); and
in a plurality of pixel units in a same row, the source electrodes of the thin film transistors of the sub-pixels in different colors are coupled to different data lines, the gate electrode of the thin film transistor of each sub-pixel is coupled to a same gate line adjacent to the pixel units in the row (figures 4A and 4B), or coupled to at least two gate lines adjacent to the pixel units in the row, and the gate electrodes of the thin film transistors of the sub-pixels in a same color are coupled to a same gate line;
wherein in at least one of the first peripheral display region and the second peripheral display region, at least one gate line branch is further arranged on and cross-coupled to each gate line, and the source electrode of the thin film transistor of the sub-pixel in at least one color in the pixel unit is coupled to the gate line branch (portion of gate lines 137 and the gate electrodes, and source electrode is coupled to the TFT and therefore the gate line branch).
Regarding claim 2, Miyake (figures 1A-5C) discloses wherein the pixel unit at least comprises a first sub-pixel, a second sub-pixel and a third sub-pixel, a pixel aperture area of the first sub-pixel in the middle display region is the same as a pixel aperture area of the first sub-pixel in the first peripheral display region and the second peripheral display region, a pixel aperture area (125; figures 3 and 4B) of the second sub-pixel in the middle display region is the same as a pixel aperture area of the second sub-pixel in the first peripheral display region and the second peripheral display region, and a pixel aperture area of the third sub-pixel in the middle display region is the same as a pixel aperture area of the third sub-pixel in the first peripheral display region and the second peripheral display region (figure 1F).
Regarding claim 5, Miyake (figures 1A-5C) wherein when the gate electrode of each sub-pixel in the pixel units in the same row is coupled to a same gate line adjacent to the pixel units in the row, in the first peripheral display region and the second peripheral display region, at least one gate line branch is further arranged on and cross-coupled to the gate line, the gate electrode of the thin film transistor of one sub-pixel closest to the gate line in the pixel unit is coupled to the gate line, and the gate electrode of the thin film transistor of the sub-pixel away from the gate line in the pixel unit is coupled to the gate line branch (portion of gate lines 137 and the gate electrodes).
Regarding claim 7, Miyake (figures 1A-5C) discloses wherein in the first peripheral display region and the second peripheral display region, the sub-pixels in a same color in the pixel units in a same column are coupled to a same data line, and each data line perpendicularly crosses the gate line or is arranged in such a manner as to bypass the sub-pixel.
Regarding claim 8, Miyake (figures 1A-5C) discloses a display device, comprising the display substrate according to any one of claim 1.
Regarding claim 11, Miyake (figures 1A-5C) discloses wherein the pixel unit at least comprises a first sub-pixel, a second sub-pixel and a third sub-pixel, a pixel aperture area of the first sub-pixel in the middle display region is the same as a pixel aperture area of the first sub-pixel in the first peripheral display region and the second peripheral display region, a pixel aperture area of the second sub-pixel in the middle display region is the same as a pixel aperture area of the second sub-pixel in the first peripheral display region and the second peripheral display region, and a pixel aperture area of the third sub-pixel in the middle display region is the same as a pixel aperture area of the third sub-pixel in the first peripheral display region and the second peripheral display region.
Regarding claim 14, Miyake (figures 1A-5C) wherein when the gate electrode of each sub-pixel in the pixel units in the same row is coupled to a same gate line adjacent to the pixel units in the row, in the first peripheral display region and the second peripheral display region, at least one gate line branch is further arranged on and cross-coupled to the gate line, the gate electrode of the thin film transistor of one sub-pixel closest to the gate line in the pixel unit is coupled to the gate line, and the gate electrode of the thin film transistor of the sub-pixel away from the gate line in the pixel unit is coupled to the gate line branch (portion of gate lines 137 and the gate electrodes).
Regarding claim 16, Miyake (figures 1A-5C) discloses wherein in the first peripheral display region and the second peripheral display region, the sub-pixels in a same color in the pixel units in a same column are coupled to a same data line, and each data line perpendicularly crosses the gate line or is arranged in such a manner as to bypass the sub-pixel.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (US 2015/0076473) in view of Shao et al. (CN 101221337).
Regarding claim 6, Miyake discloses the limitations as shown in the rejection of claim 5 above. However, Miyake is silent regarding teaches wherein when the gate electrodes of the sub-pixels in the pixel units in a same row are coupled to at least two gate lines adjacent to the pixel units in the row. Shao et al. (figure 2) teaches wherein when the gate electrodes of the sub-pixels in the pixel units in a same row are coupled to at least two gate lines adjacent to the pixel units in the row, in the first peripheral display region and the second peripheral display region, one of the at least two gate lines adjacent to the pixel units in the row is a first gate line, and the other gate line is a second gate line; at least one first gate line branch is arranged on and cross-coupled to the first gate line, or at least one second gate line branch is arranged on and cross-coupled to the second gate line; and the gate electrode of the thin film transistor of one sub-pixel closest to the first gate line in the pixel unit is coupled to the first gate line, the gate electrode of the thin film transistor of one sub-pixel closest to the second gate line in the pixel unit is coupled to the second gate line, and the gate electrode of the thin film transistor of the sub-pixel away from the first gate line and the second gate line in the pixel unit is coupled to the first gate line branch or the second gate line branch (portion of gate lines 4 and the gate electrodes). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify gate lines as taught by Shao et al. in order to turn on/off and apply a signal voltage may be across the liquid crystal. Therefore, the end portion unit pixels 41 cause their sub-pixels to function by utilizing the scanning lines for the inner unit pixels in common without wiring around the scanning line in particular.
Regarding claim 15, Miyake discloses the limitations as shown in the rejection of claim 14 above. However, Miyake is silent regarding teaches wherein when the gate electrodes of the sub-pixels in the pixel units in a same row are coupled to at least two gate lines adjacent to the pixel units in the row. Shao et al. (figure 2) teaches wherein when the gate electrodes of the sub-pixels in the pixel units in a same row are coupled to at least two gate lines adjacent to the pixel units in the row, in the first peripheral display region and the second peripheral display region, one of the at least two gate lines adjacent to the pixel units in the row is a first gate line, and the other gate line is a second gate line; at least one first gate line branch is arranged on and cross-coupled to the first gate line, or at least one second gate line branch is arranged on and cross-coupled to the second gate line; and the gate electrode of the thin film transistor of one sub-pixel closest to the first gate line in the pixel unit is coupled to the first gate line, the gate electrode of the thin film transistor of one sub-pixel closest to the second gate line in the pixel unit is coupled to the second gate line, and the gate electrode of the thin film transistor of the sub-pixel away from the first gate line and the second gate line in the pixel unit is coupled to the first gate line branch or the second gate line branch (portion of gate lines 4 and the gate electrodes). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify gate lines as taught by Shao et al. in order to turn on/off and apply a signal voltage may be across the liquid crystal. Therefore, the end portion unit pixels 41 cause their sub-pixels to function by utilizing the scanning lines for the inner unit pixels in common without wiring around the scanning line in particular.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (US 2015/0076473) in view of Nonaka (US 2010/0289994).
Regarding claim 9, Miyake discloses the limitations as shown in the rejection of claim 8 above. However, Miyake is silent regarding a light shielding layer. Nonaka (figures 1-5) teaches wherein the display device comprises a spliced screen comprising a plurality of single screens spliced with each other, each single screen comprises the display substrate and a protective cover plate, a light shielding layer is arranged on the protective cover plate and extends along a side edge of the protective cover plate, a part of the peripheral display region is shielded by the light shielding layer, and the other part of the peripheral display region is not shielded by the light shielding layer (17-18). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the light shielding layer as taught by Nonaka in order to maintain color balance at the outer edge of the image display region.
Regarding claim 10, Nonaka (figures 1-5) teaches wherein the array of pixel units in each single screen is aligned with the array of pixel units in an adjacent single screen.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAUREN NGUYEN whose telephone number is (571)270-1428. The examiner can normally be reached on Monday - Thursday, 8:00 AM -6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth, can be reached at 571-272-97911. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Lauren Nguyen/
Primary Examiner, Art Unit 2871