DETAILED ACTION
The instant application having Application No. 17/754,029 filed on 3/22/2022 is presented for examination by the examiner. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. In this case, the claim limitation is: “output units” in Claim 17.
Because this claim limitation is being interpreted under 35 U.S.C. 112(f), it is being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. In this case, such corresponding structure is described in Paragraph 0201 of the instant specification.
If applicant does not intend to have this limitation interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation to avoid it being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation recites sufficient structure to perform the claimed function so as to avoid it being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 14-17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
As per Claim 14, it recites the limitations “the corresponding word line,” “the corresponding source line” and “the corresponding bit line”. There is insufficient antecedent basis for these limitations in the claim, i.e. it is unclear which of the plurality of word/source/bit lines the “corresponding” line(s) are antecedently referring to.
As per Claim 15, it recites the limitations “the corresponding control line,” “the corresponding input line” and “the corresponding output line”. There is insufficient antecedent basis for these limitations in the claim, i.e. it is unclear which of the plurality of control/input/output lines the “corresponding” line(s) are antecedently referring to.
Moreover, Claim 15 recites the limitation “the common output line”. There is insufficient antecedent basis for this limitation in the claim.
As per Claim 16, it recites the limitations “the corresponding source line,” “the corresponding bit line,” and “the corresponding word line”. There is insufficient antecedent basis for these limitations in the claim, i.e. it is unclear which of the plurality of source/bit/word lines the “corresponding” line(s) are antecedently referring to.
As per Claim 17, it recites the limitations “the corresponding input line,” “the corresponding output line” (in lines 7 and 16), and “the corresponding control line”. There is insufficient antecedent basis for these limitations in the claim, i.e. it is unclear which of the plurality of input/output/control lines the “corresponding” line(s) are antecedently referring to.
Moreover, Claim 17 recites the limitation “the common output line”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-6, 8, 11, 13 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nazarian (US 2015/0248931).
As per Claim 1, Nazarian discloses a semiconductor element, comprising: a plurality of cell blocks configured by connecting a plurality of cell portions in series with each other (Abstract and Figures 1-2 and Paragraphs 0006-0007 and 0031, a NAND flash memory comprises a plurality of NAND memory arrays, each including a plurality of memory cells connected in series);
the plurality of cell portions each having a MOSFET for controlling conduction of a channel portion and a resistor connected in parallel to the channel portion (Figures 5-8 and Paragraphs 0008, 0029, 0032 and Claim 18, the channel region(s) of MOSFET transistors are set into a conductive or non-conductive state according a wordline voltage applied to the gate of the transistor, wherein each memory cell forms a 1-transistor 1-resistor (1T1R) memory cell via a transistor connected in parallel with a resistive device);
and configured to store data by a resistance level set for each of the plurality of cell portions (Paragraphs 0023 and 0027, memory cells store data via resistance values).
As per Claim 2, Nazarian discloses the semiconductor element according to claim 1, wherein the resistance level is represented by a resistance value of the cell portion in a state where a predetermined voltage is applied to a gate of the MOSFET (Figure 3 and Paragraphs 0033 and 0035, a program voltage is applied to transistor gates via wordlines in order to activate or deactivate, wherein the memory cells’ values are programmed according to the relative electrical resistances of the transistor and resistor in each cell).
As per Claim 5, Nazarian discloses the semiconductor element according to claim 1, wherein a threshold voltage of the MOSFET of each of the plurality of cell portions is set to either a first value or a second value different from each other, and the resistance level is set by a threshold voltage of the MOSFET (Figure 3 and Paragraphs 0033-0035, a transistor is activated or deactivated according to whether a wordline voltage applied to the gate is greater or less than a “suitable program voltage”, i.e. threshold voltage, wherein the memory cells comprising deactivated transistors are programmed according to the wordline voltage which causes the corresponding relative electrical resistances of the transistor and resistor in each cell).
As per Claim 6, Nazarian discloses the semiconductor element according to claim 1, wherein the cell block includes the plurality of cell portions formed on a same surface (Figure 5 and Paragraph 0048, a series of memory cells comprising transistors and resistive memory devices are formed on a same substrate 502).
As per Claim 8, Nazarian discloses the semiconductor element according to claim 1, wherein the cell block includes the plurality of cell portions stacked on each other (Figures 2-5, the series-connected memory cells are stacked on each other, i.e. formed directly next to one another, where e.g. bitlines are arranged vertically and wordlines are arranged horizontally).
As per Claim 11, Nazarian discloses the semiconductor element according to claim 1, wherein a resistance value of the resistor is set to a different value for each of the plurality of cell portions included in the cell block (Figure 3 and Paragraphs 0008, 0010 and 0033-0035, each individual cell can be accessed for a program operation, i.e. programmed with a different resistance value).
As per Claim 13, Nazarian discloses the semiconductor element according to claim 1, wherein a resistance value of the resistor is set to a same value for each of the plurality of cell portions included in the cell block (Figure 3 and Paragraphs 0008, 0010 and 0033-0035, each individual cell can be accessed for a program operation, wherein a plurality of cells can be activated simultaneously, i.e. programmed with a same resistance value).
As per Claim 18, Nazarian discloses a method of manufacturing a semiconductor element (Figures 6-8 and Paragraphs 0055-0060 show method(s) for fabricating the discloses NAND flash memory array); including a plurality of cell blocks in which a plurality of cell portions are connected in series (Abstract and Figures 1-2 and Paragraphs 0006-0007 and 0031, a NAND flash memory comprises a plurality of NAND memory arrays, each including a plurality of memory cells connected in series); comprising: a forming process of the plurality of cell portions including forming a MOSFET for controlling conduction of a channel portion, and forming a resistor connected in parallel to the channel portion (Figures 5-8 and Paragraphs 0008, 0029, 0032 and Claim 18, the channel region(s) of MOSFET transistors are set into a conductive or non-conductive state according a wordline voltage applied to the gate of the transistor, wherein each memory cell forms a 1-transistor 1-resistor (1T1R) memory cell via a transistor connected in parallel with a resistive device).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Kanamori et al. (US 2020/0020396).
As per Claim 14, Nazarian discloses the semiconductor element according to claim 1, further comprising: a source line; a plurality of bit lines; and a plurality of word lines (Figure 2, plurality of BL bitlines 204, WL wordlines 206, and a source line 216); wherein the MOSFET controls conduction of the channel portion in accordance with a voltage of the corresponding word line, and each of the plurality of cell blocks is a nonvolatile memory cell connected between the corresponding source line and the corresponding bit line, and configured to store data according to the resistance level set for each of the plurality of cell portions (Figures 2-3, 5-8 and Paragraphs 0008, 0029 and 0032, each memory cell is a nonvolatile memory device coupled in series between a source line 216 and a corresponding bitline 204, wherein the channel region(s) of MOSFET transistors are set into a conductive or non-conductive state according a wordline voltage applied to the gate of the transistor, wherein a program voltage is applied to transistor gates via wordlines in order to activate or deactivate, wherein the memory cells’ values are programmed according to the relative electrical resistances of the transistor and resistor in each cell).
Nazarian does not explicitly disclose a plurality of source lines, and connecting a plurality of cell portions in series between the corresponding source line and the corresponding bit line.
However, Kanamori similarly teaches a semiconductor memory comprising a plurality of bitlines, a plurality of wordlines, and strings of memory cells connected in series, wherein each memory cell comprises a transistor connected in parallel with a variable resistor (Abstract and Figures 2, 4B, 5B-6 and Paragraphs 0034-0035, 0068 and 0071); but also further discloses a plurality of source lines, and connecting a plurality of cell portions in series between the corresponding source line and the corresponding bit line (Figures 2-3 and 6 and Paragraphs 0051 and 0073-0077, a 3 dimensional memory block includes a plurality of cell strings connected between a respective source line and a respective bit line, i.e. which form planes in the D2 direction; alternatively, the memory cell array 110 comprises a plurality of memory blocks, where each 3D memory block comprises a common source line).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the three dimensional nonvolatile memory architecture taught by Kanamori with the nonvolatile memory of Nazarian because it improves the capacity and integration density of semiconductor memory devices (Kanamori, Paragraph 0003) and because it provides efficient methods of writing and erasing data in such semiconductor memories (Kanamori, Paragraphs 0004-0005).
As per Claim 16, Nazarian discloses a nonvolatile memory device, comprising: a source line; a plurality of bit lines; a plurality of word lines (Figure 2, plurality of BL bitlines 204, WL wordlines 206, and a source line 216);
and a plurality of memory cells configured by connecting a plurality of cell portions in series between the corresponding source line and the corresponding bit line, the plurality of cell portions each having a MOSFET for controlling conduction of a channel portion in accordance with a voltage of the corresponding word line and a resistor connected in parallel to the channel portion, and configured to store data by a resistance level set for each of the plurality of cell portions (Figures 2-3, 5-8 and Paragraphs 0008, 0029, 0032 and Claim 18, each memory cell is a nonvolatile memory device forming a 1-transistor 1-resistor (1T1R) memory cell via a transistor connected in parallel with a resistive device and coupled in series between a source line 216 and a corresponding bitline 204, wherein the channel region(s) of MOSFET transistors are set into a conductive or non-conductive state according a wordline voltage applied to the gate of the transistor, wherein a program voltage is applied to transistor gates via wordlines in order to activate or deactivate, wherein the memory cells’ values are programmed according to the relative electrical resistances of the transistor and resistor in each cell).
Nazarian does not explicitly disclose a plurality of source lines, and connecting a plurality of cell portions in series between the corresponding source line and the corresponding bit line.
However, Kanamori similarly teaches a semiconductor memory comprising a plurality of bitlines, a plurality of wordlines, and strings of memory cells connected in series, wherein each memory cell comprises a transistor connected in parallel with a variable resistor (Abstract and Figures 2, 4B, 5B-6 and Paragraphs 0034-0035, 0068 and 0071); but also further discloses a plurality of source lines, and connecting a plurality of cell portions in series between the corresponding source line and the corresponding bit line (Figures 2-3 and 6 and Paragraphs 0051 and 0073-0077, a 3 dimensional memory block includes a plurality of cell strings connected between a respective source line and a respective bit line, i.e. which form planes in the D2 direction; alternatively, the memory cell array 110 comprises a plurality of memory blocks, where each 3D memory block comprises a common source line).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the three dimensional nonvolatile memory architecture taught by Kanamori with the nonvolatile memory of Nazarian because it improves the capacity and integration density of semiconductor memory devices (Kanamori, Paragraph 0003) and because it provides efficient methods of writing and erasing data in such semiconductor memories (Kanamori, Paragraphs 0004-0005).
Allowable Subject Matter
Claims 3-4, 7, 9-10, 12, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 17 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SANDIFER whose telephone number is (571)270-5175. The examiner can normally be reached Mon-Fri 9:30am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW D SANDIFER/Primary Examiner, Art Unit 2151
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