DETAILED ACTION
This action is responsive to U.S. Patent Application No. 17/754,999 filed on 7 September 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
The status of the application as a 371 of PCT/CN2022/080456 is acknowledged.
Election/Restrictions
Applicant’s election without traverse of the Species VI embodiment in the reply filed on 30 December 2025 is acknowledged.
Accordingly, claims 10-12 and 17, drawn to a nonelected embodiment, are withdrawn from further consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 19, and 20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Korean Patent Publication No. KR20180068076A (published June 21, 2018) (hereinafter “Hyun”) (original with translation attached).
Regarding independent claim 1, Hyun discloses: A display device (FIG. 5, display device 200) comprising:
a substrate (FIG. 5, substrate 201, Translation at 8-14);
a driving circuit layer disposed on the substrate (FIG. 5, thin film transistor TR disposed on the substrate 201, Translation at 8-14);
a light emitting device layer disposed on the driving circuit layer (FIG. 5, light emitting diode E disposed on the thin film transistor TR, Translation at 8-14), wherein the light emitting device layer is electrically connected to the driving circuit layer (FIG. 5, depicting wherein the light emitting diode E is electrically connected to the thin film transistor TR, Translation at 8-14); and
a color filter unit covering the light emitting device layer (FIG. 5, depicting a plurality of elements that may include a color filter and thus be considered to comprise a color filter unit; “Although not shown, a color filter that absorbs red (R), green (G), blue (B), and white (not shown) light may be located on the interlayer insulating layer 240 of the light emitting area AA.”, Translation at 9),
wherein at least one of the light emitting device layer or the color filter unit is provided with a buffer groove (FIG. 5, depicting a groove provided between various layers of the light emitting diode E, including the first electrode 261, light emitting layer 263, and second electrode 265, exposing a portion of the planarizing film 246, Translation at 8-14), a plurality of elastic particles are provided in the buffer groove (FIG. 5, depicting wherein a plurality of nanoparticles, which may be formed from, e.g., titanium dioxide, are provided in the groove, Translation at 2 and 8-14).
Regarding claim 2, Hyun further discloses wherein a filling amount of the elastic particles in the buffer groove is less than 95% (“In one exemplary embodiment, the nanoparticles 120 of the present invention may be added in an amount of 1 to 50 wt%, preferably 5 to 40 wt%”, Translation at 7).
Regarding claim 3, Hyun further discloses wherein the display device comprises a display area (FIG. 5, pixel region PA, Translation at 8-14), the display area comprises a light shielding area (FIG. 5, area NA, Translation at 8-14) and a plurality of sub-pixel areas (FIG. 5, light emitting areas AA, Translation at 8-14), the light shielding area divides the display area into the plurality of sub-pixel areas (FIG. 5, depicting wherein the area NA divides the pixel region PA into a plurality of light emitting areas AA, Translation at 8-14), and both the buffer groove and the plurality of elastic particles are disposed corresponding to the light shielding area (FIG. 5, depicting wherein the groove between various layers of the light emitting diode E and nanoparticles 320 are disposed in the area NA, Translation at 8-14).
Regarding claim 4, Hyun further discloses wherein the driving circuit layer (FIG. 5, thin film transistor TR, Translation at 8-14) comprises a light shielding electrode (FIG. 5, light shielding film 210, Translation at 8-14), a buffer layer (FIG. 5, buffer layer 212, Translation at 8-14), an active layer (FIG. 5, semiconductor layer 220, Translation at 8-14), a gate insulating layer (FIG. 5, gate insulating layer 230, Translation at 8-14), a gate (FIG. 5, gate electrode 232, Translation at 8-14), an interlayer dielectric layer (FIG. 5, interlayer insulating film 240, which may be formed from, e.g., SiO2, Translation at 8-14), a source (FIG. 5, source region 222b, Translation at 8-14), a drain (FIG. 5, drain region 222c, Translation at 8-14) and an interlayer insulating layer (FIG. 5, planarizing film 246, Translation at 8-14), wherein the light shielding electrode is disposed on the substrate (FIG. 5, depicting wherein the light shielding film 210 is disposed on the substrate 201), the buffer layer covers the substrate and the light shielding electrode (FIG. 5, depicting wherein the buffer layer 212 covers the substrate 201 and the light shielding film 210), the active layer is disposed on the buffer layer and corresponds to the light shielding electrode (FIG. 5, depicting wherein the semiconductor layer 220 is disposed on the buffer layer 212 and overlaps the light shielding film 210), the gate insulating layer is disposed on the active layer (FIG. 5, depicting wherein the gate insulating layer 230 is disposed on the semiconductor layer 220), the gate is disposed on the gate insulating layer (FIG. 5, depicting wherein the gate electrode 232 is disposed on the gate insulating layer 230), the interlayer dielectric layer covers the buffer layer, the active layer and the gate (FIG. 5, depicting wherein the interlayer insulating film 240 covers the buffer layer 212, the semiconductor layer 220, and the gate electrode 232), the source and the drain are spaced apart from each other on the interlayer dielectric layer (FIG. 5, depicting wherein the source region 222b and the drain region 222c are spaced apart from each other on the interlayer insulating film 240), the source is electrically connected to one end of the active layer (FIG. 5, depicting wherein the source region 222b is electrically connected to one end of the semiconductor layer 220), the drain is electrically connected to another end of the active layer (FIG. 5, depicting wherein the drain region 222c is electrically connected to another end of the semiconductor layer), and the interlayer insulating layer covers the interlayer dielectric layer, the source and the drain (FIG. 5, depicting wherein the planarizing film 246 covers the interlayer insulating film 240, the source region 222b, and the drain region 222c).
Regarding claim 5, Hyun further discloses wherein the light emitting device layer comprises a first electrode (FIG. 5, first electrode 261, Translation at 8-14), a pixel defining layer (FIG. 5, bank layer 300, Translation at 8-14), a light emitting function layer (FIG. 5, light emitting layer 263, Translation at 8-14), and a second electrode (FIG. 5, second electrode, Translation at 8-14), the first electrode is provided on the driving circuit layer (FIG. 5, depicting wherein the first electrode 261 is provided on the thin film transistor TR); the pixel defining layer covers the first electrode and the driving circuit layer (FIG. 5, depicting wherein the bank 300 covers the first electrode 261 and the thin film transistor), the pixel defining layer is provided with a pixel opening (FIG. 5, depicting wherein the bank 300 includes an opening), and the pixel opening exposes the first electrode (FIG. 5, depicting wherein the opening in the bank 300 exposes the first electrode 261); the light emitting function layer is disposed on the first electrode in the pixel opening (FIG. 5, depicting wherein the light emitting layer 263 is disposed on the first electrode 261 in the opening in the bank 300); the second electrode covers the light emitting function layer and the pixel defining layer (FIG. 5, depicting wherein the second electrode 265 covers the light emitting layer 263 and the bank 300); and the buffer groove comprises a first buffer groove disposed in the pixel defining layer (FIG. 5, depicting wherein the groove is disposed in the bank 300), and the plurality of elastic particles are disposed in the first buffer groove (FIG. 5, depicting wherein a plurality of nanoparticles, which may be formed from, e.g., titanium dioxide, are provided in the groove).
Regarding claim 19, Hyun further discloses wherein the elastic particles are selected from at least one of silver nanoparticles, zinc oxide particles, tin oxide particles, titanium dioxide particles, gold particles, aluminum particles, or carbon nanotube particles (FIG. 5, depicting a plurality of nanoparticles, which may be formed from, e.g., titanium dioxide, Translation at 2).
Regarding claim 20, Hyun further discloses wherein a particle size of the elastic particles ranges from 5 nanometers to 100 nanometers (FIGS. 5/8, depicting wherein the nanoparticle 320 size ranges from approximately 10 nm to approximately 30 nm, Translation at 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-15 are rejected under 35 U.S.C. § 103 as being unpatentable over Hyun in view of U.S. Patent Publication No. 2023/0105598 (effectively filed Sept. 13, 2021) (hereinafter “Kim 1”) and further in view of U.S. Patent Publication No. 2019/0103583 (filed Sept. 17, 2018) (hereinafter “Kim 2”).
Regarding claim 13, Hyun discloses a package cover plate (FIG. 5, second substrate 202). Hyun does not specifically disclose wherein the color filter unit comprises a light shielding layer, the light shielding layer is disposed on a side of the package cover plate near the light emitting device layer, the buffer groove comprises a third buffer groove disposed on the light shielding layer, and the plurality of elastic particles are disposed in the third buffer groove.
In the same field of endeavor, Kim 1 discloses a display device (FIG. 5, display panel 1000, [0181]) including a light shielding layer (FIG. 5, depicting a layer in which a light blocking pattern 220 is formed, [0220]), the buffer groove comprises a third buffer groove disposed on the light shielding layer (FIG. 5, depicting wherein the layer in which the light blocking pattern 220 is disposed defines a groove between adjacent light blocking patterns 220). Regarding the light blocking layer configuration, in [0232], Kim 1 states: “The light blocking pattern 220 may partition each subpixel PX1, PX2, and PX3 and be disposed between the neighboring subpixels PX1, PX2, and PX3. The light blocking pattern 220 may be, for example, a black matrix. The light blocking pattern 220 may be overlapped with the edges of the neighboring color filters 230 a, 230 b, and 230 c.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display device of Hyun by adding the light blocking configuration of Kim 1 in order to block light and partition the light emitting elements. See Kim 1 [0232].
Moreover, adding the light blocking configuration of Kim 1 would result in a configuration wherein the light shielding layer is disposed on a side of the package cover plate near the light emitting device layer (Kim 1 FIG. 5; Hyun FIG. 5; depicting wherein the light blocking pattern 220 would be disposed on a side of the second substrate 202 of Hyun near the light emitting diode E, just as the light blocking pattern 220 is disposed on a side of the substrate 210 of Kim 1).
Hyun in view of Kim 1 does not specifically disclose wherein a plurality of elastic particles are disposed in the third buffer groove.
In the same field of endeavor, Kim 2 discloses a display device including an encapsulation layer configuration wherein a plurality of elastic particles disposed in the encapsulation layer (FIG. 5, depicting an encapsulating layer 500 including reinforcing members 700 including metal beads 700b, [0074]-[0077]). Regarding the encapsulating layer 500, in [0077], Kim 2 discloses: “Thus, in the organic light-emitting display device according to the embodiment of the present disclosure, the rigidity of the encapsulating substrate 600 may be complemented without increasing the overall thickness. Therefore, in the organic light-emitting display device according to the embodiment of the present disclosure, damage of the light-emitting element 300 due to the external impact may be prevented.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display device of Hyun by adding the encapsulation layer configuration of Kim 2 in order improve rigidity of the display device and prevent damage due to external impact. See Kim 2 [0077].
Moreover, adding the encapsulation layer configuration of Kim 2 would result in a configuration wherein a plurality of elastic particles are disposed in the third buffer groove (Hyun FIG. 5; Kim 1 FIG. 5; Kim 2 FIG. 5; depicting wherein the reinforcing portions 700 containing metal beads are disposed over display area AA of Kim 2, and would be disposed over the display area AA of Hyun, as well as overlapping with the layer in which the light blocking pattern 220 is disposed defining a groove between adjacent light blocking patterns 220 of Kim 1).
Regarding claim 14, Hyun in view of Kim 1 and Kim 2 further discloses wherein the light shielding layer (Kim 1 FIG. 5, depicting a layer in which a light blocking pattern 220 is formed) comprises a first light shielding strip extending in a first direction (Kim 1 FIG. 5, depicting a first light blocking pattern 220 portion, e.g., a left light blocking pattern portion, extending in a first direction, e.g., left) and a second light shielding strip extending in a second direction (Kim 1 FIG. 5, depicting a second light blocking pattern 220 portion, e.g., a right light blocking pattern portion, extending in a second direction, e.g., right), the first light shielding strip intersects the second light shielding strip (Kim 1 FIG. 5, disclosing wherein the light blocking pattern 220 is a black matrix having a lattice shape, [0244]), and each of the first light shielding strip and the second light shielding strip is provided with the third buffer groove (Kim 1 FIG. 5, depicting wherein each of the first and second light blocking pattern 200 portions define the groove in the layer in which a light blocking pattern 220 is formed).
Regarding claim 15, Hyun in view of Kim 1 and Kim 2 further discloses wherein a plurality of first light shielding strips and a plurality of second light shielding strips are combined to form a plurality of grooves (Kim 1 FIGS. 4/5, depicting wherein there are a plurality of first and second light blocking pattern 220 portions forming a plurality of grooves in the layer in which a light blocking pattern 220 is formed), and a corresponding color filter is provided in each of the plurality of grooves (Hyun FIG. 5, disclosing wherein a color filter is disposed in the light emitting area AA and thus would be provided in grooves in the layer in which a light blocking pattern 220 is formed).
Allowable Subject Matter
Claims 6-9, 16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
Regarding claim 6: the cited prior art does not anticipate or make obvious, inter alia: “wherein the display device further comprises a first force-bearing layer disposed on the pixel defining layer, the first force-bearing layer is spaced apart from the second electrode, and the first force-bearing layer covers the elastic particles in the first buffer groove,” wherein the first force-bearing layer is interpreted as being a structure separate from the pixel defining layer and the second electrode. Claims 7-9, which depend from claim 6, contain allowable subject matter for at least the same reasons as claim 6.
Regarding claim 16: the cited prior art does not anticipate or make obvious, inter alia: “wherein the display device further comprises a second force-bearing layer disposed on a side of the light shielding layer near the light emitting device layer, the second force-bearing layer covers the elastic particles in the third buffer groove,” wherein the second force-bearing layer is interpreted as being a structure separate from the light shielding layer. Claim 18, which depends from claim 16, contains allowable subject matter for the same reasons as claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication No. 20200075694.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813