DETAILED ACTION
This action is responsive to the communication filed on 23 May 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of Applicant’s claim of priority as a 371 of PCT/ PCT/JP2020/042399.
Response to Arguments
The indicated allowability of claim 8 is withdrawn in view of the newly discovered reference(s) to U.S. Patent Publication No. 2002/0158345 (filed April 25, 2002) (hereinafter “Hedler”). Rejections based on the newly cited reference follow.
Applicant asserts that claims 1-3, 9, and 12 are allowable due to the incorporation of dependent claims 4 and 8 in independent claim 1. Regarding claims 1-3, 9, and 12, consistent with the withdrawal of the indicated allowability of the subject matter of claim 8, the rejection of each of the claims as anticipated under 35 U.S.C. § 102(a)(1) over U.S. Patent Publication No. 2018/0166490 (published June 4, 2018) (hereinafter “Wakiyama”) is withdrawn. New rejections of claims 1-3, 9, and 12 under 35 U.S.C. § 103 over Wakiyama in view of newly cited reference Hedler are detailed below. Accordingly, Applicant’s assertion that claims 1-3, 9, and 12 are allowable due to incorporation of claims 4 and 8 in independent claims 1 and 12 is unpersuasive.
Applicant asserts that claims 10 and 11 are allowable due to the incorporation of dependent claims 4 and 8 in independent claim 1. Regarding claims 10 and 11, consistent with the withdrawal of the indicated allowability of the subject matter of claim 8, the rejection of each of the claims as obvious under 35 U.S.C. § 103 over Wakiyama in view of U.S. Patent Publication No. 2008/0303107 (published Dec. 11, 2008) (hereinafter “Minamio”) is withdrawn. New rejections of claims 10 and 11 under 35 U.S.C. § 103 over Wakiyama in view of newly cited reference Hedler and Minamio are detailed below. Accordingly, Applicant’s assertion that claims 10 and 11 are allowable due to incorporation of claims 4 and 8 in independent claim 1 is unpersuasive.
Claim Rejections - 35 USC § 112
The § 112(b) rejection of claim 9 regarding the “single film formation” terminology in the Non-Final Office Action mailed 27 February 2025 at pages 4-5 is withdrawn.
New § 112(b) rejections of claims 1 and 12 are detailed below.
Claims 1 and 9-12 are rejected under 35 U.S.C. § 112(b) or 35 U.S.C. § 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity. ‘As the statutory language of “particular[ity]” and “distinct[ness]” indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not.’” MPEP § 2173.02(II) (quoting In re Packard, 751 F.3d 1307, 1313, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014)).
Regarding claims 1 and 12: Claims 1 and 12 both contain the same problematic language (and are thus addressed together) and state, in relevant part, “a protective film on at least a part of each of: a side surface of the first chip, and a side surface of the second chip, wherein the side surface of the first chip is connected to a surface of the first chip, the surface of the first chip is on a first side, of the first chip, on which the first chip is on the sensor substrate, the side surface of the second chip is connected to a surface of the second chip, the surface of the second chip is on a first side, of the second chip, on which the second chip is on the sensor substrate, the protective film is in a region between the first chip and the second chip, the region is on each of the first side of the first chip and the first side of the second chip, the region has a reversely tapered shape in a cross-sectional view of the solid-state imaging device, and the cross-section view is from a second side of the first chip and a second side of the second chip.” Respectfully, the Examiner is unable to determine what relative configuration of sides, surfaces, and side surfaces on which the protective film is formed, the differences between sides and surfaces (e.g., what the difference is between the surface of the first chip and the first side of the first chip, and for what reason the first side of the first chip is referenced with respect to the region rather than the surface of the first chip) and thus what configuration of the region between the first chip and the second chip, as well as what relative configuration of the protective film, the first chip, and the second chip, is that is being claimed in the relevant portions of claims 1 and 12. For the purposes of examination, the relevant portions of claims 1 and 12 regarding the terms “surface” and “first side” of the first and second chips as being the portion of the chip facing and on the sensor substrate, and wherein the term “side surface” does not include a surface facing the sensor substrate.
Claims 2, 3, and 9-11, which depend from claim 1, are also rejected under § 112(b) for the same reasons as claim 1.
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3 and 12 are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Publication No. 2018/0166490 (published June 14, 2018) (hereinafter “Wakiyama”) in view of Hedler.
Regarding independent claim 1, Wakiyama discloses: A solid-state imaging device (FIGS. 35/36, solid state image capturing device 391 including sensor semiconductor element 402, interposer substrate 403, semiconductor element 404, [0311]), comprising:
a sensor substrate (FIG. 36, interposer substrate 403, [0207], [0219]) having an imaging element (FIG. 36, sensor semiconductor element 402 having photoelectric conversion elements 443, [0207], [0219]),
wherein the imaging element includes a pixel unit (FIG. 36, depicting wherein the sensor semiconductor element 402 includes a photoelectric conversion element 443 in each pixel, [0219]: “[E]ach pixel includes a photoelectric conversion element that receives and photoelectrically converts a light from a subject, an electric charge accumulating section that accumulates an electric charge obtained by the photoelectric conversion element, and a pixel circuit including a plurality of field-effect transistors.”), and
the imaging element is configured to generate a pixel signal in the pixel unit (FIG. 36, sensor semiconductor element 402 including photoelectric conversion elements 443 for each pixel; [0219]: “[E]ach pixel includes a photoelectric conversion element that receives and photoelectrically converts a light from a subject, an electric charge accumulating section that accumulates an electric charge obtained by the photoelectric conversion element, and a pixel circuit including a plurality of field-effect transistors.”);
a first chip on the sensor substrate (FIG. 36, logic semiconductor element 471 or DRAM semiconductor element 472 on the interposer substrate 403, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”),
wherein the first chip is electrically connected to the sensor substrate (FIG. 36, depicting wherein logic semiconductor element 471 or DRAM semiconductor element 472 is electrically connected to the interposer substrate 403, [0228])
a second chip on the sensor substrate (FIG. 36, logic semiconductor element 471 or DRAM semiconductor element 472 on the interposer substrate 403, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”),
wherein the second chip is electrically connected to the sensor substrate (FIG. 36, depicting wherein logic semiconductor element 471 or DRAM semiconductor element 472 is electrically connected to the interposer substrate 403, [0228]),
at least one of the first chip or the second chip includes a signal processing circuit (FIG. 36, logic semiconductor element 471, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”; [0470]: “The solid-state image capturing device may be formed as one substrate, or may be formed as a module having an image capturing function and including an imaging unit and a signal processing unit or an optical system packaged therein.”),
the signal processing circuit is configured to execute a signal processing operation on the pixel signal (FIG. 36, logic semiconductor element 471, [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”), and
the first chip and the second chip are in a same direction on the sensor substrate (FIG. 36, depicting wherein logic semiconductor element 471 and DRAM semiconductor element 472 are stacked in the same direction on interposer substrate 403);
and a protective film (FIG. 36, resin 741, [0308]-[0309]) on at least a part of each of:
a side surface of the first chip (FIG. 36, depicting wherein resin 741 is disposed on all side surfaces of logic semiconductor element 471 and DRAM semiconductor element 472), and
a side surface of the second chip (FIG. 36, depicting wherein resin 741 is disposed on all side surfaces of logic semiconductor element 471 and DRAM semiconductor element 472),
wherein the side surface of the first chip is connected to a surface of the first chip (FIG. 36, depicting wherein the logic semiconductor element 471 and DRAM semiconductor element 472 each have a surface facing the interposer substrate 403, as well as side surfaces connected to that surface facing the interposer substrate 403),
the surface of the first chip is on a first side, of the first chip, on which the first chip is on the sensor substrate (FIG. 36, depicting wherein the logic semiconductor element 471 and DRAM semiconductor element 472 each have a surface facing the interposer substrate 403, as well as side surfaces connected to that surface facing the interposer substrate 403),
the side surface of the second chip is connected to a surface of the second chip (FIG. 36, depicting wherein the logic semiconductor element 471 and DRAM semiconductor element 472 each have a surface facing the interposer substrate 403, as well as side surfaces connected to that surface facing the interposer substrate 403),
the surface of the second chip is on a first side, of the second chip, on which the second chip is on the sensor substrate (FIG. 36, depicting wherein the logic semiconductor element 471 and DRAM semiconductor element 472 each have a surface facing the interposer substrate 403, as well as side surfaces connected to that surface facing the interposer substrate 403),
the protective film is in a region between the first chip and the second chip (FIG. 36, depicting wherein resin 741 is disposed on all side surfaces of logic semiconductor element 471 and DRAM semiconductor element 472, as well as between the logic semiconductor element 471 and DRAM semiconductor element 472),
the region is on each of the first side of the first chip and the first side of the second chip (FIG. 36, depicting wherein resin 741 is disposed on all side surfaces of logic semiconductor element 471 and DRAM semiconductor element 472, as well as between the logic semiconductor element 471 and DRAM semiconductor element 472).
Wakiyama does not specifically disclose wherein the region has a reversely tapered shape in a cross-sectional view of the solid-state imaging device, and the cross-section view is from a second side of the first chip and a second side of the second chip.
In the same field of endeavor, Hedler discloses an electronic component including a plurality of semiconductor chips (FIG. 4, depicting semiconductor chips 3, [0089]), wherein the region between adjacent semiconductor chips has a reversely tapered shape in a cross-sectional view (FIG. 4, depicting a region between adjacent semiconductor chips 3 on substrate 20 having a reversely tapered shape), and the cross-section view is from a second side of the first chip and a second side of the second chip (FIG. 4, depicting wherein the region has a reversely tapered shape in a cross-sectional view from a side of the semiconductor chips 3). Regarding the reversely tapered shape of the region between the semiconductor chips 3, Hedler discloses that the angled sidewalls of the semiconductor chips 3 which creates the reversely tapered shape of the region between the semiconductor chips 3 functions to promote easier application of additional material layers on the semiconductor chips and in the regions between the semiconductor chips ([0086]: “In a process step following this, FIG. 4 shows a schematic cross section through the wafer, which has been separated into semiconductor chips 3. In this case, the SiO2 layer 4 and the polyimide layer 10 at the base of the etched trench 13 are in each case removed, so that the semiconductor chips 3 are separated. This removal of the SiO2 layer 4 and of the polyimide layer 10 is expediently carried out chemically, resulting in smooth edges on the side surfaces of the semiconductor chips 3, which can easily be metalized in a subsequent method step.”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed imaging device of Wakiyama by substituting the shape of the semiconductor chips 3 of Hedler such that the region between the reversely tapered shaped logic semiconductor element 471 and DRAM semiconductor element 472 has a reversely tapered shape in order to promote easier application of additional material layers on the semiconductor chips and in the regions between the semiconductor chips. See Hedler [0086].
Regarding claim 2, Wakiyama in view of Hedler further discloses wherein the protective film (FIG. 36, resin 741) covers a region of the sensor substrate (FIG. 36, depicting wherein the resin 741 covers a region of the interposer substrate 403, [0308]-[0309]),
the region of the sensor substrate is on each of the first side of the first chip and the first side of the second chip (FIG. 36, depicting wherein resin 741 is disposed on all side surfaces of logic semiconductor element 471 and DRAM semiconductor element 472 and covers the interposer substrate 403 on those side surfaces, [0308]-[0309]), and
in the region of the sensor substrate (FIG. 36, depicting wherein resin 741 is disposed on all side surfaces of logic semiconductor element 471 and DRAM semiconductor element 472 and covers the interposer substrate 403 on those side surfaces), the sensor substrate and each of the first chip and the second chip are unstacked (FIG. 36, depicting wherein the logic semiconductor element 471 and DRAM semiconductor element 472 are not stacked on each other on the interposer substrate 403).
Regarding claim 3, Wakiyama in view of Hedler further discloses wherein the protective film (FIG. 36, resin 741) covers an outer periphery of each of the first chip and the second chip in a plan view of the solid-state imaging device (FIG. 36, resin 741 is disposed on all side surfaces of the logic semiconductor element 471 and DRAM semiconductor element 472), and the plan view from a third side of the first chip and a third side of the second chip (FIG. 36, depicting wherein the resin 741 is disposed on all side surfaces of the logic semiconductor element 471 and DRAM semiconductor element 472, including from various sides).
Regarding independent claim 12, Wakiyama discloses: Electronic equipment (FIG. 61, showing electronic equipment applications of the imaging device including, for example, a camera for monitoring the state of farm/crops, [0478]-[0487]), comprising:
a solid-state imaging device (FIGS. 35/36, solid state image capturing device 391 including sensor semiconductor element 402, interposer substrate 403, semiconductor element 404, [0311]) that includes:
a sensor substrate (FIG. 36, interposer substrate 403, [0207], [0219]) having an imaging element (FIG. 36, sensor semiconductor element 402 having photoelectric conversion elements 443, [0207], [0219]),
wherein the imaging element includes a pixel unit (FIG. 36, depicting wherein the sensor semiconductor element 402 includes a photoelectric conversion element 443 in each pixel, [0219]: “[E]ach pixel includes a photoelectric conversion element that receives and photoelectrically converts a light from a subject, an electric charge accumulating section that accumulates an electric charge obtained by the photoelectric conversion element, and a pixel circuit including a plurality of field-effect transistors.”), and
the imaging element is configured to generate a pixel signal in the pixel unit (FIG. 36, sensor semiconductor element 402 including photoelectric conversion elements 443 for each pixel; [0219]: “[E]ach pixel includes a photoelectric conversion element that receives and photoelectrically converts a light from a subject, an electric charge accumulating section that accumulates an electric charge obtained by the photoelectric conversion element, and a pixel circuit including a plurality of field-effect transistors.”);
a first chip on the sensor substrate (FIG. 36, logic semiconductor element 471 or DRAM semiconductor element 472 on the interposer substrate 403, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”),
wherein the first chip is electrically connected to the sensor substrate (FIG. 36, depicting wherein logic semiconductor element 471 or DRAM semiconductor element 472 is electrically connected to the interposer substrate 403, [0228])
a second chip on the sensor substrate (FIG. 36, logic semiconductor element 471 or DRAM semiconductor element 472 on the interposer substrate 403, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”),
wherein the second chip is electrically connected to the sensor substrate (FIG. 36, depicting wherein logic semiconductor element 471 or DRAM semiconductor element 472 is electrically connected to the interposer substrate 403, [0228]),
at least one of the first chip or the second chip includes a signal processing circuit (FIG. 36, logic semiconductor element 471, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”; [0470]: “The solid-state image capturing device may be formed as one substrate, or may be formed as a module having an image capturing function and including an imaging unit and a signal processing unit or an optical system packaged therein.”),
the signal processing circuit is configured to execute a signal processing operation on the pixel signal (FIG. 36, logic semiconductor element 471, [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”), and
the first chip and the second chip are in a same direction on the sensor substrate (FIG. 36, depicting wherein logic semiconductor element 471 and DRAM semiconductor element 472 are stacked in the same direction on interposer substrate 403);
and a protective film (FIG. 36, resin 741, [0308]-[0309]) on at least a part of each of:
a side surface of the first chip (FIG. 36, depicting wherein resin 741 is disposed on all side surfaces of logic semiconductor element 471 and DRAM semiconductor element 472), and
a side surface of the second chip (FIG. 36, depicting wherein resin 741 is disposed on all side surfaces of logic semiconductor element 471 and DRAM semiconductor element 472),
wherein the side surface of the first chip is connected to a surface of the first chip (FIG. 36, depicting wherein the logic semiconductor element 471 and DRAM semiconductor element 472 each have a surface facing the interposer substrate 403, as well as side surfaces connected to that surface facing the interposer substrate 403),
the surface of the first chip is on a first side, of the first chip, on which the first chip is on the sensor substrate (FIG. 36, depicting wherein the logic semiconductor element 471 and DRAM semiconductor element 472 each have a surface facing the interposer substrate 403, as well as side surfaces connected to that surface facing the interposer substrate 403),
the side surface of the second chip is connected to a surface of the second chip (FIG. 36, depicting wherein the logic semiconductor element 471 and DRAM semiconductor element 472 each have a surface facing the interposer substrate 403, as well as side surfaces connected to that surface facing the interposer substrate 403),
the surface of the second chip is on a first side, of the second chip, on which the second chip is on the sensor substrate (FIG. 36, depicting wherein the logic semiconductor element 471 and DRAM semiconductor element 472 each have a surface facing the interposer substrate 403, as well as side surfaces connected to that surface facing the interposer substrate 403),
the protective film is in a region between the first chip and the second chip (FIG. 36, depicting wherein resin 741 is disposed on all side surfaces of logic semiconductor element 471 and DRAM semiconductor element 472, as well as between the logic semiconductor element 471 and DRAM semiconductor element 472),
the region is on each of the first side of the first chip and the first side of the second chip (FIG. 36, depicting wherein resin 741 is disposed on all side surfaces of logic semiconductor element 471 and DRAM semiconductor element 472, as well as between the logic semiconductor element 471 and DRAM semiconductor element 472).
Wakiyama does not specifically disclose wherein the region has a reversely tapered shape in a cross-sectional view of the solid-state imaging device, and the cross-section view is from a second side of the first chip and a second side of the second chip.
In the same field of endeavor, Hedler discloses an electronic component including a plurality of semiconductor chips (FIG. 4, depicting semiconductor chips 3, [0089]), wherein the region between adjacent semiconductor chips has a reversely tapered shape in a cross-sectional view (FIG. 4, depicting a region between adjacent semiconductor chips 3 on substrate 20 having a reversely tapered shape), and the cross-section view is from a second side of the first chip and a second side of the second chip (FIG. 4, depicting wherein the region has a reversely tapered shape in a cross-sectional view from a side of the semiconductor chips 3). Regarding the reversely tapered shape of the region between the semiconductor chips 3, Hedler discloses that the angled sidewalls of the semiconductor chips 3 which creates the reversely tapered shape of the region between the semiconductor chips 3 functions to promote easier application of additional material layers on the semiconductor chips and in the regions between the semiconductor chips ([0086]: “In a process step following this, FIG. 4 shows a schematic cross section through the wafer, which has been separated into semiconductor chips 3. In this case, the SiO2 layer 4 and the polyimide layer 10 at the base of the etched trench 13 are in each case removed, so that the semiconductor chips 3 are separated. This removal of the SiO2 layer 4 and of the polyimide layer 10 is expediently carried out chemically, resulting in smooth edges on the side surfaces of the semiconductor chips 3, which can easily be metalized in a subsequent method step.”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed imaging device of Wakiyama by substituting the shape of the semiconductor chips 3 of Hedler such that the region between the reversely tapered shaped logic semiconductor element 471 and DRAM semiconductor element 472 has a reversely tapered shape in order to promote easier application of additional material layers on the semiconductor chips and in the regions between the semiconductor chips. See Hedler [0086].
Claims 9-11 are rejected under 35 U.S.C. § 103 as being unpatentable over Wakiyama in view of Hedler, and further in view of U.S. Patent Publication No. 2008/0303107 (published Dec. 11, 2008) (hereinafter “Minamio”).
Regarding claim 9, Wakiyama discloses wherein the protective film includes a single film (FIG. 36, depicting wherein resin 741 is formed as a single layer, [0308]-[0309]).
Wakiyama does not specifically disclose wherein the protective film includes silicon nitride.
In the same field of endeavor, however, Minamio discloses a protective film containing silicon nitride (FIG. 3, protective film 23 coating solid state imaging device 10 containing silicon nitride, [0044]-[0045], [0053]). Regarding the protective film 23, in [0055], Minamio states: “[T]he transparent protective film 23 of an inorganic material has an excellent mechanical strength and an excellent moisture interception capability. Therefore, even though, for example, dust or the like is wiped, degradation of the reliability caused by the wiping can be prevented.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed solid state image device of Wakiyama with the silicon nitride protective film of Minamio in order to provide increased insulating properties and protection from dust and other contamination. See Minamio [0055].
Regarding claim 10, Wakiyama does not specifically disclose wherein the protective film includes a material having an insulating property.
In [0050], however, Minamio discloses resins comprising insulating materials including , among other materials, “one type or two or more types of epoxy-based resin, polycarbonate-based resin, polyethylene-based resin, polyolefin-based resin, polystyrene-based resin, polyurethane-based resin, polyimide-based resin, and silicone-based resin.”
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known resin material, as shown by Minamio in [0050], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose an organic polymer over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer.
Regarding claim 11, Wakiyama does not specifically disclose wherein the protective film includes silicon nitride.
In the same field of endeavor, however, Minamio discloses a protective film containing silicon nitride (FIG. 3, protective film 23 coating solid state imaging device 10 containing silicon nitride, [0044]-[0045], [0053]). Regarding the protective film 23, in [0055], Minamio states: “[T]he transparent protective film 23 of an inorganic material has an excellent mechanical strength and an excellent moisture interception capability. Therefore, even though, for example, dust or the like is wiped, degradation of the reliability caused by the wiping can be prevented.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed solid state image device of Wakiyama with the silicon nitride protective film of Minamio in order to provide increased insulating properties and protection from dust and other contamination. See Minamio [0055].
Allowable Subject Matter
Claims 13 and 14 are allowed.
The following is the Examiner’s statement of reasons for allowance:
Applicant’s reply, filed 23 May 2025 with the amended claims, makes evident the reasons for allowance of claims 13 and 14, satisfying the “record as a whole” provision of the rule 37 CFR 1.104(e). Specifically, in addition to the reasons for indicating allowable subject matter in the Non-Final Rejection mailed 27 February 2025, the substance of Applicant' s amendments and remarks regarding claims 13 and 14 are persuasive (See Applicant Arguments/Remarks Made in an Amendment (filed 23 May 2025) at 8), and as such the reasons for allowance are in all probability evident from the record and no statement is deemed necessary. See MPEP §1302.14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submission should be clearly labeled "Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813