DETAILED ACTION
This action is responsive to the communication filed on 23 October 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of Applicant’s claim of priority as a 371 of PCT/ PCT/JP2020/042399.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 1 and 12 are objected to because of the following informalities:
Claim 1 contains a typo and should read: “the cross-sectional view”
Claim 12 contains a typo and should read: “the cross-sectional view”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The § 112(b) rejection of claims 1 and 9-12 is withdrawn, responsive to Applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 9-12, and 15 are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Publication No. 2018/0166490 (published June 14, 2018) (hereinafter “Wakiyama”) in view of U.S. Patent Publication No. 2002/0158345 (filed April 25, 2002) (hereinafter “Hedler”) and U.S. Patent Publication No. 2021/0020601 (filed July 17, 2019) (hereinafter “Chen”).
Regarding independent claim 1, Wakiyama discloses: A solid-state imaging device (FIGS. 41/42, solid state image capturing device 391 including sensor semiconductor element 402, interposer substrate 403, semiconductor element 404, [0311]), comprising:
a sensor substrate (FIG. 42, interposer substrate 403, [0207], [0219]) having an imaging element (FIG. 42, sensor semiconductor element 402 having photoelectric conversion elements 443, [0207], [0219]),
wherein the imaging element includes a pixel unit (FIG. 42, depicting wherein the sensor semiconductor element 402 includes a photoelectric conversion element 443 in each pixel, [0219]: “[E]ach pixel includes a photoelectric conversion element that receives and photoelectrically converts a light from a subject, an electric charge accumulating section that accumulates an electric charge obtained by the photoelectric conversion element, and a pixel circuit including a plurality of field-effect transistors.”), and
the imaging element is configured to generate a pixel signal in the pixel unit (FIG. 42, sensor semiconductor element 402 including photoelectric conversion elements 443 for each pixel; [0219]: “[E]ach pixel includes a photoelectric conversion element that receives and photoelectrically converts a light from a subject, an electric charge accumulating section that accumulates an electric charge obtained by the photoelectric conversion element, and a pixel circuit including a plurality of field-effect transistors.”);
a first chip on the sensor substrate (FIG. 42, logic semiconductor element 471 or DRAM semiconductor element 472 on the interposer substrate 403, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”),
wherein the first chip is electrically connected to the sensor substrate (FIG. 42, depicting wherein logic semiconductor element 471 or DRAM semiconductor element 472 is electrically connected to the interposer substrate 403, [0228])
a second chip on the sensor substrate (FIG. 42, logic semiconductor element 471 or DRAM semiconductor element 472 on the interposer substrate 403, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”),
wherein the second chip is electrically connected to the sensor substrate (FIG. 42, depicting wherein logic semiconductor element 471 or DRAM semiconductor element 472 is electrically connected to the interposer substrate 403, [0228]),
at least one of the first chip or the second chip includes a signal processing circuit (FIG. 42, logic semiconductor element 471, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”; [0470]: “The solid-state image capturing device may be formed as one substrate, or may be formed as a module having an image capturing function and including an imaging unit and a signal processing unit or an optical system packaged therein.”),
the signal processing circuit is configured to execute a signal processing operation on the pixel signal (FIG. 42, logic semiconductor element 471, [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”), and
the first chip and the second chip are in a same direction on the sensor substrate (FIG. 42, depicting wherein logic semiconductor element 471 and DRAM semiconductor element 472 are stacked in the same direction on interposer substrate 403);
wherein the first chip includes a first side surface (FIG. 42, depicting, e.g., the left side of the DRAM semiconductor element 472 or the right side of the logic semiconductor element 471),
wherein the second chip includes a first side surface (FIG. 42, depicting, e.g., the left side of the DRAM semiconductor element 472 or the right side of the logic semiconductor element 471),
wherein the first side surface of the first chip is connected to a first surface of the first chip (FIG. 42, depicting, e.g., the surface closest to the interposer substrate 403 of either of the DRAM semiconductor element 472 or the logic semiconductor element 471),
wherein the first chip is on the sensor substrate via the first surface of the first chip (FIG. 42, depicting, e.g., wherein either of the DRAM semiconductor element 472 or the logic semiconductor element 471 are on the on the interposer substrate 403 via the surface of either of the DRAM semiconductor element 472 or the logic semiconductor element 471 closest to the interposer substrate 403),
wherein the first side surface of the second chip is connected to a first surface of the second chip (FIG. 42, depicting, e.g., the surface closest to the interposer substrate 403 of either of the DRAM semiconductor element 472 or the logic semiconductor element 471),
wherein the second chip is on the sensor substrate via the first surface of the second chip (FIG. 42, depicting, e.g., wherein either of the DRAM semiconductor element 472 or the logic semiconductor element 471 are on the on the interposer substrate 403 via the surface of either of the DRAM semiconductor element 472 or the logic semiconductor element 471 closest to the interposer substrate 403),
wherein there is a first region between the first chip and the second chip (FIG. 42, depicting a region between the DRAM semiconductor element 472 and the logic semiconductor element 471),
wherein the first region includes a second side surface of the first chip (FIG. 42, depicting, e.g., the right side of the DRAM semiconductor element 472 or the left side of the logic semiconductor element 471) and a second side surface of the second chip (FIG. 42, depicting, e.g., the right side of the DRAM semiconductor element 472 or the left side of the logic semiconductor element 471) and a second region between the second side surface of the first chip and the second side surface of the second chip (FIG. 42, depicting the region between the right side of the DRAM semiconductor element 472 and the left side of the logic semiconductor element 471),
wherein the first chip includes a second surface opposite to the first surface of the first chip (FIG. 42, depicting, e.g., the surface furthest from the interposer substrate 403 of either of the DRAM semiconductor element 472 or the logic semiconductor element 471),
wherein the second chip includes a second surface opposite to the first surface of the second chip (FIG. 42, depicting, e.g., the surface furthest from the interposer substrate 403 of either of the DRAM semiconductor element 472 or the logic semiconductor element 471).
Wakiyama does not specifically disclose wherein the first region has a reversely tapered shape in a cross-sectional view of the solid-state imaging device, and the cross-section view is from a second side of the first chip and a second side of the second chip.
In the same field of endeavor, Hedler discloses an electronic component including a plurality of semiconductor chips (FIG. 4, depicting semiconductor chips 3, [0089]), wherein the region between adjacent semiconductor chips has a reversely tapered shape in a cross-sectional view (FIG. 4, depicting a region between adjacent semiconductor chips 3 on substrate 20 having a reversely tapered shape), and the cross-section view is from a second side of the first chip and a second side of the second chip (FIG. 4, depicting wherein the region has a reversely tapered shape in a cross-sectional view from a side of the semiconductor chips 3). Regarding the reversely tapered shape of the region between the semiconductor chips 3, Hedler discloses that the angled sidewalls of the semiconductor chips 3 which creates the reversely tapered shape of the region between the semiconductor chips 3 functions to promote easier application of additional material layers on the semiconductor chips and in the regions between the semiconductor chips ([0086]: “In a process step following this, FIG. 4 shows a schematic cross section through the wafer, which has been separated into semiconductor chips 3. In this case, the SiO2 layer 4 and the polyimide layer 10 at the base of the etched trench 13 are in each case removed, so that the semiconductor chips 3 are separated. This removal of the SiO2 layer 4 and of the polyimide layer 10 is expediently carried out chemically, resulting in smooth edges on the side surfaces of the semiconductor chips 3, which can easily be metalized in a subsequent method step.”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed imaging device of Wakiyama by substituting the shape of the semiconductor chips 3 of Hedler such that the region between the reversely tapered shaped logic semiconductor element 471 and DRAM semiconductor element 472 has a reversely tapered shape in order to promote easier application of additional material layers on the semiconductor chips and in the regions between the semiconductor chips. See Hedler [0086].
Wakiyama in view of Hedler does not specifically disclose wherein a protective film is formed on at least a part of each of the first side surface of the first chip, the first side surface of the second chip, the first region between the first chip and the second chip, and wherein each of the second surface of the first chip and the second surface of the second chip excludes the protective film.
In the same field of endeavor, Chen discloses an integrated circuit structure including a first chip (FIG. 1F, depicting a left second die 200, [0020]) and a second chip (FIG. 1F, depicting a right second die, [0020]), and further including a protective film (FIG. 1F, dielectric layer BL, [0031]) formed on at least a part of each of the first side surface of the first chip and the first side surface of the second chip (FIG. 1F, depicting wherein the dielectric layer BL is formed on left and right sides of each of the left and right second dies 200), wherein the protective film is further formed in a first region between the first chip and the second chip (FIG. 1F, depicting wherein the dielectric layer BL is formed in the region between the left and right second dies 200), and further wherein a second surface of the first chip and a second surface of the second chip excludes the protective film (FIG. 1F, depicting wherein the dielectric layer is not formed on the surface of the left and right second dies 200 furthest from the first semiconductor substrate 102). Regarding the dielectric layer BL, in [0031], Chen states: “the dielectric layer BL may be formed by a deposition process which provides a good adhesion to the surfaces of the gap G1 and provides a suitable thickness efficiently. Accordingly, the to-be formed dielectric structure DS may be adhered to the first and second dies 100, 200 stably.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed imaging device of Wakiyama and Hedler by adding the dielectric layer BL of Chen in order to promote adhesion of additional layers subsequently deposited to the imaging device. See Chen [0031].
Regarding claim 2, Wakiyama in view of Hedler and Chen further discloses wherein the sensor substrate includes the second region (FIG. 42, depicting wherein the interposer substrate 403 includes the region between the right side of the DRAM semiconductor element 472 and the left side of the logic semiconductor element 471) and in the second region of the sensor substrate, the sensor substrate and each of the first chip and the second chip are unstacked (FIG. 42, depicting wherein the DRAM semiconductor element 472 and the logic semiconductor element 471 are unstacked in the region between the right side of the DRAM semiconductor element 472 and the left side of the logic semiconductor element 471).
Regarding claim 3, Wakiyama in view of Hedler and Chen further discloses wherein the protective film covers an outer periphery of each of the first chip and the second chip in a plan view of the solid-state imaging device (Wakiyama FIG. 42; Chen FIG. 1F; depicting wherein the dielectric layer BL covers an outer periphery (i.e., at least the left and right sides of the left and right second dies 200, respectively) of each of the left and right second dies 200 in a plan view; [0031]: “In some embodiments, as shown in FIG. 1C, a dielectric layer BL is formed over the first die 100 to cover the second dies 200 and the first die 100 between the second dies 200, and then a gap G2 is formed. The dielectric layer BL may be formed over top surfaces of the second dies 200 and the sidewall SW1 and the bottom BT1 of the gap G1.”), and the plan view is from a second side of the first chip and a second side of the second chip (Wakiyama FIG. 42; Chen FIG. 1F; depicting wherein the plan view is from a second side of the DRAM semiconductor element 472 and the logic semiconductor element 471).
Regarding claim 9, Wakiyama in view of Hedler and Chen further discloses wherein the protective film (Chen FIG. 1F, dielectric layer BL) includes a single film of silicon nitride (Chen FIG. 1F, depicting wherein the dielectric layer BL is a single film and comprises silicon nitride, [0032]).
Regarding claim 10, Wakiyama in view of Hedler and Chen further discloses wherein the protective film (Chen FIG. 1F, dielectric layer BL) includes a material having an insulating property (Chen FIG. 1F, depicting wherein the dielectric layer BL is a single film and comprises silicon nitride, [0032]).
Regarding claim 11, Wakiyama in view of Hedler and Chen further discloses wherein the protective film (Chen FIG. 1F, dielectric layer BL) includes silicon nitride (Chen FIG. 1F, depicting wherein the dielectric layer BL is a single film and comprises silicon nitride, [0032]).
Regarding independent claim 12, Wakiyama discloses: Electronic equipment (FIG. 61, showing electronic equipment applications of the imaging device including, for example, a camera for monitoring the state of farm/crops, [0478]-[0487]), comprising:
a solid-state imaging device (FIGS. 41/42, solid state image capturing device 391 including sensor semiconductor element 402, interposer substrate 403, semiconductor element 404, [0311]) that includes:
a sensor substrate (FIG. 42, interposer substrate 403, [0207], [0219]) having an imaging element (FIG. 42, sensor semiconductor element 402 having photoelectric conversion elements 443, [0207], [0219]),
wherein the imaging element includes a pixel unit (FIG. 42, depicting wherein the sensor semiconductor element 402 includes a photoelectric conversion element 443 in each pixel, [0219]: “[E]ach pixel includes a photoelectric conversion element that receives and photoelectrically converts a light from a subject, an electric charge accumulating section that accumulates an electric charge obtained by the photoelectric conversion element, and a pixel circuit including a plurality of field-effect transistors.”), and
the imaging element is configured to generate a pixel signal in the pixel unit (FIG. 42, sensor semiconductor element 402 including photoelectric conversion elements 443 for each pixel; [0219]: “[E]ach pixel includes a photoelectric conversion element that receives and photoelectrically converts a light from a subject, an electric charge accumulating section that accumulates an electric charge obtained by the photoelectric conversion element, and a pixel circuit including a plurality of field-effect transistors.”);
a first chip on the sensor substrate (FIG. 42, logic semiconductor element 471 or DRAM semiconductor element 472 on the interposer substrate 403, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”),
wherein the first chip is electrically connected to the sensor substrate (FIG. 42, depicting wherein logic semiconductor element 471 or DRAM semiconductor element 472 is electrically connected to the interposer substrate 403, [0228])
a second chip on the sensor substrate (FIG. 42, logic semiconductor element 471 or DRAM semiconductor element 472 on the interposer substrate 403, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”),
wherein the second chip is electrically connected to the sensor substrate (FIG. 42, depicting wherein logic semiconductor element 471 or DRAM semiconductor element 472 is electrically connected to the interposer substrate 403, [0228]),
at least one of the first chip or the second chip includes a signal processing circuit (FIG. 42, logic semiconductor element 471, [0228], [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”; [0470]: “The solid-state image capturing device may be formed as one substrate, or may be formed as a module having an image capturing function and including an imaging unit and a signal processing unit or an optical system packaged therein.”),
the signal processing circuit is configured to execute a signal processing operation on the pixel signal (FIG. 42, logic semiconductor element 471, [0230]: “Here, the logic semiconductor element 471 including a logic circuit to perform a signal processing and a DRAM semiconductor element 472 including a memory circuit to function as a memory correspond to the semiconductor element 404 illustrated in FIG. 24.”), and
the first chip and the second chip are in a same direction on the sensor substrate (FIG. 42, depicting wherein logic semiconductor element 471 and DRAM semiconductor element 472 are stacked in the same direction on interposer substrate 403);
wherein the first chip includes a first side surface (FIG. 42, depicting, e.g., the left side of the DRAM semiconductor element 472 or the right side of the logic semiconductor element 471),
wherein the second chip includes a first side surface (FIG. 42, depicting, e.g., the left side of the DRAM semiconductor element 472 or the right side of the logic semiconductor element 471),
wherein the first side surface of the first chip is connected to a first surface of the first chip (FIG. 42, depicting, e.g., the surface closest to the interposer substrate 403 of either of the DRAM semiconductor element 472 or the logic semiconductor element 471),
wherein the first chip is on the sensor substrate via the first surface of the first chip (FIG. 42, depicting, e.g., wherein either of the DRAM semiconductor element 472 or the logic semiconductor element 471 are on the on the interposer substrate 403 via the surface of either of the DRAM semiconductor element 472 or the logic semiconductor element 471 closest to the interposer substrate 403),
wherein the first side surface of the second chip is connected to a first surface of the second chip (FIG. 42, depicting, e.g., the surface closest to the interposer substrate 403 of either of the DRAM semiconductor element 472 or the logic semiconductor element 471),
wherein the second chip is on the sensor substrate via the first surface of the second chip (FIG. 42, depicting, e.g., wherein either of the DRAM semiconductor element 472 or the logic semiconductor element 471 are on the on the interposer substrate 403 via the surface of either of the DRAM semiconductor element 472 or the logic semiconductor element 471 closest to the interposer substrate 403),
wherein there is a first region between the first chip and the second chip (FIG. 42, depicting a region between the DRAM semiconductor element 472 and the logic semiconductor element 471),
wherein the first region includes a second side surface of the first chip (FIG. 42, depicting, e.g., the right side of the DRAM semiconductor element 472 or the left side of the logic semiconductor element 471) and a second side surface of the second chip (FIG. 42, depicting, e.g., the right side of the DRAM semiconductor element 472 or the left side of the logic semiconductor element 471) and a second region between the second side surface of the first chip and the second side surface of the second chip (FIG. 42, depicting the region between the right side of the DRAM semiconductor element 472 and the left side of the logic semiconductor element 471),
wherein the first chip includes a second surface opposite to the first surface of the first chip (FIG. 42, depicting, e.g., the surface furthest from the interposer substrate 403 of either of the DRAM semiconductor element 472 or the logic semiconductor element 471),
wherein the second chip includes a second surface opposite to the first surface of the second chip (FIG. 42, depicting, e.g., the surface furthest from the interposer substrate 403 of either of the DRAM semiconductor element 472 or the logic semiconductor element 471).
Wakiyama does not specifically disclose wherein the first region has a reversely tapered shape in a cross-sectional view of the solid-state imaging device, and the cross-section view is from a second side of the first chip and a second side of the second chip.
In the same field of endeavor, Hedler discloses an electronic component including a plurality of semiconductor chips (FIG. 4, depicting semiconductor chips 3, [0089]), wherein the region between adjacent semiconductor chips has a reversely tapered shape in a cross-sectional view (FIG. 4, depicting a region between adjacent semiconductor chips 3 on substrate 20 having a reversely tapered shape), and the cross-section view is from a second side of the first chip and a second side of the second chip (FIG. 4, depicting wherein the region has a reversely tapered shape in a cross-sectional view from a side of the semiconductor chips 3). Regarding the reversely tapered shape of the region between the semiconductor chips 3, Hedler discloses that the angled sidewalls of the semiconductor chips 3 which creates the reversely tapered shape of the region between the semiconductor chips 3 functions to promote easier application of additional material layers on the semiconductor chips and in the regions between the semiconductor chips ([0086]: “In a process step following this, FIG. 4 shows a schematic cross section through the wafer, which has been separated into semiconductor chips 3. In this case, the SiO2 layer 4 and the polyimide layer 10 at the base of the etched trench 13 are in each case removed, so that the semiconductor chips 3 are separated. This removal of the SiO2 layer 4 and of the polyimide layer 10 is expediently carried out chemically, resulting in smooth edges on the side surfaces of the semiconductor chips 3, which can easily be metalized in a subsequent method step.”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed imaging device of Wakiyama by substituting the shape of the semiconductor chips 3 of Hedler such that the region between the reversely tapered shaped logic semiconductor element 471 and DRAM semiconductor element 472 has a reversely tapered shape in order to promote easier application of additional material layers on the semiconductor chips and in the regions between the semiconductor chips. See Hedler [0086].
Wakiyama in view of Hedler does not specifically disclose wherein a protective film is formed on at least a part of each of the first side surface of the first chip, the first side surface of the second chip, the first region between the first chip and the second chip, and wherein each of the second surface of the first chip and the second surface of the second chip excludes the protective film.
In the same field of endeavor, Chen discloses an integrated circuit structure including a first chip (FIG. 1F, depicting a left second die 200, [0020]) and a second chip (FIG. 1F, depicting a right second die, [0020]), and further including a protective film (FIG. 1F, dielectric layer BL, [0031]) formed on at least a part of each of the first side surface of the first chip and the first side surface of the second chip (FIG. 1F, depicting wherein the dielectric layer BL is formed on left and right sides of each of the left and right second dies 200), wherein the protective film is further formed in a first region between the first chip and the second chip (FIG. 1F, depicting wherein the dielectric layer BL is formed in the region between the left and right second dies 200), and further wherein a second surface of the first chip and a second surface of the second chip excludes the protective film (FIG. 1F, depicting wherein the dielectric layer is not formed on the surface of the left and right second dies 200 furthest from the first semiconductor substrate 102). Regarding the dielectric layer BL, in [0031], Chen states: “the dielectric layer BL may be formed by a deposition process which provides a good adhesion to the surfaces of the gap G1 and provides a suitable thickness efficiently. Accordingly, the to-be formed dielectric structure DS may be adhered to the first and second dies 100, 200 stably.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed imaging device of Wakiyama and Hedler by adding the dielectric layer BL of Chen in order to promote adhesion of additional layers subsequently deposited to the imaging device. See Chen [0031].
Regarding claim 15, Wakiyama in view of Hedler and Chen further discloses wherein the protective film covers side surfaces of the sensor substrate (Wakiyama FIG. 42; Chen FIG. 1F; depicting wherein the dielectric layer BL covers the side surfaces of the first semiconductor substrate 102 in the regions to the left and right of each of the left and right second dies 200, such that the dielectric layer BL configuration would cover the side surfaces of the interposer substrate 403 in the regions to the left and right of the DRAM semiconductor element 472 and the logic semiconductor element 471).
Allowable Subject Matter
Claims 13 and 14 are allowed.
The following is the Examiner’s statement of reasons for allowance:
Applicant’s reply, filed 23 May 2025 with the amended claims, makes evident the reasons for allowance of claims 13 and 14, satisfying the “record as a whole” provision of the rule 37 CFR 1.104(e). Specifically, in addition to the reasons for indicating allowable subject matter in the Non-Final Rejection mailed 27 February 2025, the substance of Applicant' s amendments and remarks regarding claims 13 and 14 are persuasive (See Applicant Arguments/Remarks Made in an Amendment (filed 23 May 2025) at 8), and as such the reasons for allowance are in all probability evident from the record and no statement is deemed necessary. See MPEP §1302.14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submission should be clearly labeled "Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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