Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
THIS ACTION IS MADE FINAL.
Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
The applicant’s arguments filed on July 7, 2025, have been fully considered. However, the arguments are not persuasive for the reasons set forth below.
1. Re: Applicant’s Argument Regarding Equivalency of PAU in Zhao
Applicant contends that “the PAU annotated by the PTO in Zhao cannot be equivalent to the precision adjustment unit in this application.” The examiner respectfully disagrees. As disclosed in Zhao, the current detection and control unit is configured to dynamically switch among various resistance paths—referred to herein as the “PAU” (Precision Adjustment Unit) for ease of reference to applicant’s terminology—based on the read current value. This configuration enables multi-stage current detection, allowing for both a broad application range and high precision, as stated in the abstract and background sections of Zhao. Thus, the functionality of the PAU in Zhao reasonably corresponds to that of the claimed precision adjustment unit.
2. Re: Applicant’s Argument Regarding the Status of FIG. 3 in Zhao
Applicant argues that “FIG. 3 of Zhao mentioned by the PTO is the prior art of the scheme involved in Zhao.” The examiner finds this assertion to be inaccurate. Zhao explicitly identifies FIGS. 3 and 4 as part of a second embodiment of the invention, not prior art. Specifically, paragraphs [0030]–[0031] of Zhao describe a multilevel resistance network used to sample current through a dedicated current detection chip, which allows current to be read across a wide dynamic range with adequate precision. The measurement occurs between the source end (point A in FIG. 3) and the output end (point B in FIG. 3). Accordingly, FIG. 3 is part of the inventive disclosure of Zhao, not prior art, and supports the examiner’s position.
The examiner further notes that the applicant appears to have conflated FIG. 1 and FIG. 3 of Zhao. While FIG. 1 is indeed cited in Zhao as prior art—illustrating the limitations of using a single resistor value and low-resolution ADCs, as acknowledged by applicant on page 6 of the remarks—FIG. 3 represents a disclosed improvement over that prior art.
3. Re: Applicant’s Argument Regarding the Power Supply Circuit under Vcc in FIG. 3 of Zhao
Applicant argues that “there is not any module under the Vcc annotated by the PTO in FIG. 3 of Zhao, only the connection line was shown to be grounded, and there was no written record in the specification indicating that the wire provided a power supply circuit for the power amplifier transistor, so Zhao did not disclose the power amplifier transistor power supply circuit of this application.”
The examiner clarifies that the §103 rejection is not based on Zhao explicitly disclosing a power amplifier transistor power supply circuit. Rather, Zhao is relied upon for teaching a wide-range, precision current detection circuit, which is capable of monitoring and controlling current with high accuracy. It would have been obvious to one of ordinary skill in the art to apply such a circuit to monitor the supply current for a power amplifier module.
To support this position, the examiner notes the availability and widespread application of commercially available current detection ICs, such as MAX4373/MAX4374/MAX4375, ADM4073, INA138, and INS168, which are routinely used to monitor bias currents in power amplifier circuits, particularly in battery-powered portable devices. In this context, Zhao’s output node B can be connected to the Vcc terminal of a power amplifier, enabling real-time current sensing and control.
4. Re: Combination with Lautzenhiser
To further support the rationale under §103, the examiner relies on Lautzenhiser as a secondary reference. Lautzenhiser, operating in a similar field of endeavor, discloses (in FIG. 5) a power amplifier gate bias control circuit that senses the drain current and uses a microprocessor (see ¶[0080]) to automatically adjust the gate voltage. This adjustment maintains a stable drain current, independent of variations in temperature, input drive, frequency, and device-to-device inconsistencies.
Therefore, it would have been obvious to one of ordinary skill in the art to use Zhao’s precision current detection circuit to supply and monitor the Vcc line of a power amplifier as disclosed in Lautzenhiser. This integration would provide the benefit of accurately controlling the quiescent current of the power amplifier transistor gate, thereby stabilizing amplifier performance across environmental and operational variations.
In view of the above, the applicant’s arguments do not overcome the prior art rejection under 35 U.S.C. § 103. The combination of Zhao and Lautzenhiser remains a proper basis for the rejection, and no persuasive rebuttal has been presented to overcome the rationale of obviousness as previously articulated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (CN 203849312 U, cited by the applicant and a marked machine translation is relied upon) in view of Lautzenhiser (US 2014/0333382).
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Fig. 3 of Zhao annotated by the examiner for ease of reference.
Regarding claim 1, An auxiliary control circuit (as shown in annotated Fig. 3 of Zhao as a precision multi-stage current detection unit). Zhao, however, is not explicit about the particular use of this precision multi-stage current detection unit in a RF power amplification module although essentially this type of precision multi-stage current detection unit is applicable for power amplifiers where large range and high precision are required, so power amplifiers for battery powered portable devices are suitable choice for such circuits, please see applications of series of current sensing devices’ datasheets of a range of off-the shelf devices, such as MAX4373/MAX4374/MAX4375, ADM4073 and INA138, INS168),
Lautzenhiser in a similar field of endeavor teaches (in Fig. 5) a power amplifier transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device-to-device variations (abstract) using a microprocessor (§0080).
A person of ordinary skill in the art would find it obvious with a precision drain current (DC supply current of a power amplifier transistor), such as Zhao’s to control the quiescent current setting of the power amplifier transistor gate such that the power amplifier operates in a constant gate bias setting irrespective of temperature, time, input drive, frequency, as well as from device-to-device variations as taught by Lautzenhiser. The Lautzenhiser, Zhao combination would therefore, teaches on the auxiliary control circuit (replacing the simple current detection circuit Lautzenhiser with the precision multi-stage current detection unit of Zhao) for a power amplification module such as Lautzenhiser’s.
the auxiliary control circuit (precision multi-stage current detection unit of Zhao) comprising a main control chip (CPU), a current detection chip (designated as CDC by the examiner in the annotated Fig. 3 of Zhao above, which exemplarily comprising of RSENSE and an op-AMP as shown in Fig. 1 of Zhao), and a precision adjustment unit (designated as PAU by the examiner in the annotated Fig. 3 of Zhao above), wherein:
the precision adjustment unit (PAU) is connected in parallel to a precision control resistor (resistor RSENSE in CDC) of the current detection chip (CDC), and the precision adjustment unit (PAU) has a switch control terminal (plurality of switches, see Fig. 3) electrically connected to the main control chip (see Fig. 3 with the firm line) and is configured to be turned on or to be turned off (resistance sampling module comprising a movable contact and a static contact, §0011-§0018) when receiving a switch signal output by the main control chip, and to adjust an output voltage amplification factor (more resistors are connected in parallel by channel selection with the precision resistor in CDC less will be the overall resistance and less will be the voltage drop across the sense resistor block combination which will reduce the sensitivity of the measurement when high current needs to be measured. At time of low current measurements more precision is needed and least no of resistors are connected in parallel to have higher voltage drop across the sense resistor block, steps 401 through 408 of Fig. 4, §0033-§0046) of the current detection chip when the precision adjustment unit is turned on (when the current detection, a certain resistance via resistance sampling module is preset to be turned on (default condition, quantity range minimum resistance path is turned on), §0018); and
a detection input terminal of the current detection chip (CDC) is configured to receive a voltage of a power amplifier transistor power supply circuit (designated as Vcc by the examiner in the annotated Fig. 3 of Zhao above) of the power amplification module to be measured, a detection output terminal (designated as Do by the examiner in the annotated Fig. 3 of Zhao above, §0031) of the current detection chip (CDC) is electrically connected to the main control chip (CPU through the interface ADC), and the main control chip (CPU) is configured to estimate a power amplification current (current Isense) corresponding to the voltage to be measured (voltage drop across the resistor block of the current detection chip) after receiving a voltage signal output by the current detection chip. Also, per claim 2, Zhao teaches the precision adjustment unit (PAU) includes a first programmed switch (one of the plurality of switches, Fig. 3) and a first auxiliary resistor (R1), and a switch control terminal (designated as Sc by the examiner in the annotated Fig. 3 of Zhao above) of the first programmed switch (SW1) is electrically connected to the main control chip (CPU);
an input terminal of the first programmed switch (SW1) is electrically connected to a first terminal of the precision control resistor (RSENSE in CDC), an output terminal (bottom terminal) of the first programmed switch (SW1) is electrically connected to a first terminal of the first auxiliary resistor (R1), and a second terminal (right end) of the first auxiliary resistor (R1) is electrically connected to a second terminal of the precision control resistor (CDC); and the precision control resistor (RSENSE in CDC) is a current sensing resistor (RSENSE) or an external amplification resistor of the current detection chip (CDC); and again per claim 3, Zhao further teaches that the precision adjustment unit further includes a second programmed switch (one of the plurality of switches, Fig. 3) and a second auxiliary resistor (R2), a switch control terminal of the second programmed switch being electrically connected to the main control chip (CPU); and
an input terminal of the second programmed switch is electrically connected to the first terminal of the precision control resistor (RSENSE in CDC), an output terminal of the second programmed switch (one of the plurality of switches, Fig. 3) is electrically connected to a first terminal of the second auxiliary resistor (R2), and a second terminal of the second auxiliary resistor is electrically connected to the second terminal of the precision control resistor (RSENSE in CDC), wherein per claim 4, the precision adjustment unit (PAU) includes a first programmed switch (first one of the plurality of switches, Fig. 3) and a first auxiliary resistor (R1) connected in series (Fig. 3), and a second programmed switch (second one of the plurality of switches, Fig. 3) and a second auxiliary resistor (R2) connected in series (Fig. 3), and the precision control resistor (RSENSE in CDC) is a current sensing resistor of the current detection chip (CDC);
a switch control terminal (Sc) of the first programmed switch (one of the pluralities of the arms of the switch S1) is electrically connected to the main control chip (CPU), an input terminal of the first programmed switch is electrically connected to a first terminal of the current sensing resistor (RSENSE of CDC), and a second terminal of the first auxiliary resistor (R1) is electrically connected to a second terminal of the current sensing resistor (RSENSE of CDC connected in parallel with R1 as R1 is switched in to the circuit); and
a switch control terminal (one of the two ends of each arm of the plurality of arms of the switch, Fig. 3) of the second programmed switch (second arm of the plurality of arms of the switch) is electrically connected to the main control chip (CPU), an input terminal of the second programmed switch is electrically connected to a first terminal of the external amplification resistor, and a second terminal of the second auxiliary resistor is electrically connected to a second terminal of the external amplification resistor (resistors R1-R12 external to CDC and part of amplification control by a person of ordinary skill in the art can be perceived in two different categories as six of them are considered as auxiliary resistors and the rest six of them can be considered as external amplification resistors).
Regarding claim 5, the combination teaches all limitations of claim 1, Zhao, however, is not explicit about the gate voltage automatic adjustment circuit is configured to adjust the magnitude of a gate voltage of a power amplifier transistor of the power amplification module after receiving a static current adjustment signal output by the main control chip.
Lautzenhiser teaches a power amplifier transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device-to-device variations (abstract) using a microprocessor (§0080).
Also, per claim 6, it would be an obvious addition to the resultant modified circuit of Zhao in view of Lautzenhiser to provide warning about overcurrent of an operating current of the intended power amplifier transistor circuit of Zhao after receiving a warning signal output by the main control chip (CPU) connected as claimed (claim 6) and as per detection of damaging range of over current, turn down(0ff) the gate voltage or disconnect the supply voltage through the CDC circuit to protect the power amplifier transistor because the power amplifier transistors are often the most expensive devices in a power amplifier circuit.
Also, per claim 7, the resultant modified circuit of Zhao in view of Lautzenhiser would also have an RF link for the RF amplifier and per claim 8, it would be a communication device, comprising the power amplification module wherein per claim 10, the communication device is an integrated power amplifier of a communication device.
Although the modified amplifier device of Zhao and Lautzenhiser is not explicit about a display device to monitor the current and power through the CPU as required for claim 9. It would have been an obvious extension to the amplifier monitoring system to add a display, especially since the Zhao and Lautzenhiser combination has CPU and ADC to equip the circuit with a plug and play digital display.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
Prosecution Insights