DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 15-19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20220320215 A1), hereinafter Lee, and Jang et al. (US 2015/0241501 A1), hereinafter Jang.
Regarding Claim 1, Lee teaches:
A display substrate (FIG. 1), comprising:
a base substrate (FIG. 5: 200); and
a plurality of sub-pixels (FIG. 1: PX) arranged in an array (See paragraph [0056]), wherein at least one of the plurality of sub-pixels (See FIG. 3A: e.g., PXij) comprises a pixel driving circuit (See FIG. 3A: the pixel driving circuit outlined by the dashed line) and a light-emitting device (FIG. 3A: OLED), the plurality of sub-pixels form an array of M rows*N columns, and M and N are positive integers greater than or equal to 1 (See paragraph [0056]); the pixel driving circuit comprises a plurality of transistors (FIG. 3A: T1-T7) (See paragraph [0116]), and the plurality of transistors comprise driving transistors (FIG. 3A: T1) (See paragraph [0117]); and the light-emitting device comprises a first electrode (See FIG. 3A: an anode of OLED corresponds to a first electrode) (See paragraph [0116]);
wherein the base substrate comprises: a first initialization signal line and a second initialization signal line (See annotated FIG. 3A below); and the first initialization signal line and the second initialization signal line extend in a first direction (DR2), and the first direction is an extension direction of sub-pixel rows (See FIG. 3A: VL1h and VL2h extend in DR2, DR2 is an extension direction of sub-pixel rows);
the first initialization signal line is respectively electrically connected with a mth row of sub-pixels (See annotated FIG 3A below: the first initialization signal line is respectively electrically connected with a mth (ith in the figure) row of sub-pixels), and is configured to transmit a first initialization signal to a control electrode of a driving transistor of the mth row of sub-pixels (See FIG. 3A: VL1h is configured to transmit a first initialization signal VINT1 to a control electrode of T1 of the ith row of sub-pixels via T4a and T4b); and the second initialization signal line is respectively electrically connected with a (m-1)th row of sub-pixels (See annotated FIG 3A below: the second initialization signal line is respectively electrically connected with a (m-1)th ((i-1)th in the figure) row of sub-pixels), and is configured to transmit a second initialization signal to a first electrode of a light-emitting device of the (m-1)th row of sub-pixels (See FIG. 3A: VL2h is configured to transmit a second initialization signal VINT2 to a first electrode of OLED of the (i-1)th row of sub-pixels via T7);
in a second direction (DR1), a projection of the first initialization signal line on the base substrate is located on one side of a projection of the second initialization signal line on the base substrate close to a projection of the (m-1)th row of sub-pixels on the base substrate, the second direction is an extension direction of sub-pixel columns, and m is a positive integer greater than or equal to 1 and less than or equal to M (See annotated FIG 3A below: in DR1, a projection of the first initialization signal line on the base substrate is located on one side of a projection of the second initialization signal line on the base substrate close to a projection of the (i-1)th row of sub-pixels on the base substrate, the second direction is an extension direction of sub-pixel columns, and m = i is a positive integer greater than or equal to 1 and less than or equal to M); and
the first initialization signal is different from the second initialization signal (See annotated FIG 3A below: the first initialization signal is different from the second initialization signal);
wherein in the second direction, the first initialization signal line and the second initialization signal line are both located between driving transistors of adjacent two rows of sub-pixels (See annotated FIG 3A below: the second direction (DR1), the first initialization signal line (VL1h) and the second initialization signal line (VL2h) are both located between driving transistors T6 and two adjacent rows of sub-pixels (VL1h and VL2h above of T1 of the shown pixel are located between the driving transistor of the pixel above the shown driving transistor and the driving transistor of the shown pixel) (FIGS 3A-3B), and located on a same side of driving transistors of any row of the same and adjacent two rows of sub-pixels (VL1h and VL2h above of T1 of the shown pixel (e.g. PX(j+1) are located between the driving transistor (T6) of the pixel above the shown driving transistor (T6 of PX(j+1)) and the driving transistor (T6) of the shown pixel (T6 of PX(j+1)) since in a matrix display, it is inherent that the pixel is a repeating pattern (FIGS 3A-3B) (e.g. in the second direction (DR1), the first initialization signal line is located between T1 of two adjacent rows of sub-pixels (ith and (i+1)th rows) and the second initialization signal line is located between T1 of the two adjacent rows of sub-pixels (ith and (i+1)th rows), and located on a same side of any row of the two adjacent rows of driving transistors (See FIGS 3A-3B, annotated FIG 3A below: the first initialization signal line (VL1h) and the second initialization signal line (VL2h) are located on a same side of any row of the two adjacent rows of driving transistors T1 in DR1)
wherein the display substrate further comprises a third initialization signal line (VL1v) extending in the second direction (See FIG. 3A: VL1v extending in DR2);
wherein the plurality of sub-pixels comprise red sub-pixels emitting red light, blue sub-pixels emitting blue light, and green sub-pixels emitting green light (Par. 192).
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Lee does not expressly disclose the plurality of sub-pixel columns comprise red-blue pixel columns and green pixel columns; the red-blue pixel columns comprise the red sub-pixels and the blue sub-pixels disposed alternately in the second direction: the green pixel columns comprise the green sub-pixels disposed in sequence in the second direction; and wherein the third initialization signal line is only located in the red-blue pixel columns, or the third initialization signal line is only located in the green pixel columns.
Jang discloses the plurality of sub-pixel columns comprise red-blue pixel columns (e.g. DL1) and green pixel columns (e.g. DL2) (Fig. 10, Pars. 106, 109-110); the red-blue pixel columns comprise the red sub-pixels and the blue sub-pixels disposed alternately in the second direction(Fig. 10, Pars. 106, 109-110); the green pixel columns comprise the green sub-pixels disposed in sequence in the second direction(Fig. 10, Pars. 106, 109-110); and wherein the third initialization signal line is only located in the red-blue pixel columns (Fig. 10, Pars. 106, 109-110).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Lee with the teaching of Jang to provide an improved display device as suggested by Jang (Par. 116).
Regarding Claim 6, Lee teaches:
The display substrate according to claim 1, further comprising: a reset signal line (GIL_i), wherein the reset signal line extends in the first direction and is configured to transmit a reset signal (GI_i) to the pixel driving circuit (See annotated FIG. 3A below: GIL_i extends in DR2 and is configured to transmit GI_i to the pixel driving circuit);
the plurality of transistors further comprise: a first reset transistor (T4a/T4b) and a second reset transistor (T7) (See FIG. 3A); and
the first reset transistor is configured to transmit the first initialization signal on the first initialization signal line to the control electrode of the driving transistor of the mth row of sub-pixels under control of the reset signal (See annotated FIG. 3A below: T4a/T4b is configured to transmit VINT1 on VL1h to the control electrode of T1 of the ith row of sub-pixels under control of GI_i); and the second reset transistor is configured to transmit the second initialization signal on the second initialization signal line to the first electrode of the light-emitting device of the (m-1)th row of sub-pixels under control of the reset signal (See annotated FIG. 3A below: T7 is configured to transmit VINT1 on VL1h to the control electrode of T1 of the (i-1)th row of sub-pixels under control of GI_i).
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Regarding Claim 22, see claim 1 rejection and motivation above. Lee further teaches:
A display apparatus (FIG. 1), comprising a display substrate (FIG. 1: 110), wherein the display substrate comprises:
a base substrate (FIG. 5: 200); and
a plurality of sub-pixels (FIG. 1: PX) arranged in an array (See paragraph [0056]), wherein at least one of the plurality of sub-pixels (See FIG. 3A: e.g., PXij) comprises a pixel driving circuit (See FIG. 3A: the pixel driving circuit outlined by the dashed line) and a light-emitting device (FIG. 3A: OLED), the plurality of sub-pixels form an array of M rows*N columns, and M and N are positive integers greater than or equal to 1 (See paragraph [0056]); the pixel driving circuit comprises a plurality of transistors (FIG. 3A: T1-T7) (See paragraph [0116]), and the plurality of transistors comprise driving transistors (FIG. 3A: T1) (See paragraph [0117]); and the light-emitting device comprises a first electrode (See FIG. 3A: an anode of OLED corresponds to a first electrode) (See paragraph [0116]);
wherein the base substrate comprises: a first initialization signal line and a second initialization signal line (See annotated FIG. 3A below); and the first initialization signal line and the second initialization signal line extend in a first direction (DR2), and the first direction is an extension direction of sub-pixel rows (See FIG. 3A: VL1h and VL2h extend in DR2, DR2 is an extension direction of sub-pixel rows);
the first initialization signal line is respectively electrically connected with a mth row of sub-pixels (See annotated FIG 3A below: the first initialization signal line is respectively electrically connected with a mth (ith in the figure) row of sub-pixels), and is configured to transmit a first initialization signal to a control electrode of a driving transistor of the mth row of sub-pixels (See FIG. 3A: VL1h is configured to transmit a first initialization signal VINT1 to a control electrode of T1 of the ith row of sub-pixels via T4a and T4b); and the second initialization signal line is respectively electrically connected with a (m-1)th row of sub-pixels (See annotated FIG 3A below: the second initialization signal line is respectively electrically connected with a (m-1)th ((i-1)th in the figure) row of sub-pixels), and is configured to transmit a second initialization signal to a first electrode of a light-emitting device of the (m-1)th row of sub-pixels (See FIG. 3A: VL2h is configured to transmit a second initialization signal VINT2 to a first electrode of OLED of the (i-1)th row of sub-pixels via T7);
in a second direction (DR1), a projection of the first initialization signal line on the base substrate is located on one side of a projection of the second initialization signal line on the base substrate away from a projection of the (m-1)th row of sub-pixels on the base substrate, the second direction is an extension direction of sub-pixel columns, and m is a positive integer greater than or equal to 1 and less than or equal to M (See annotated FIG 3A below: in DR1, a projection of the first initialization signal line on the base substrate is located on one side of a projection of the second initialization signal line on the base substrate away from a projection of the (i-1)th row of sub-pixels on the base substrate, the second direction is an extension direction of sub-pixel columns, and m = i is a positive integer greater than or equal to 1 and less than or equal to M); and
the first initialization signal is different from the second initialization signal (See annotated FIG 3A below: the first initialization signal is different from the second initialization signal).
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Regarding Claim 15, Lee in view of Jang teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee in view of Jang teaches:
The display substrate according to claim 1, wherein when the third initialization signal line (e.g. Jang’s DL1) is located in the red-blue pixel columns (Jang’s Fig. 10, Pars. 106, 109-110), wherein a shape of the third initialization signal line electrically connected with a nth column of red-blue pixel columns is roughly the same as a shape of the third initialization signal line electrically connected with a (n+1)th column of red-blue pixel columns, and n is a positive integer greater than or equal to 1 and less than or equal to N (See Lee, FIG. 3B: a shape of VLv1 is roughly the same shape for each of the depicted columns j-1, j and j+1. Therefore, adopting the red-blue pixel columns taught by Jang, a shape of VLv1 connected with any nth column of red-blue pixel columns is roughly the same as a shape of VLv1 connected with a (n+1)th column of red-blue pixel columns).
Regarding Claim 16, Lee in view of Jang teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 15, wherein the third initialization signal line comprises a first extension portion, a second extension portion and a third extension portion connected in sequence in the second direction (See annotated FIG. 3B below: the portions of VLv1 labeled “1”, “2” and “3”, respectively correspond to a first extension portion, a second extension portion and a third extension portion, connected in sequence in DR1), the first extension portion extends in the second direction and is electrically connected with the first initialization signal line through a via hole (CP8) (See annotated FIG. 3B below: “1” extends in DR1 and is electrically connected with the first initialization signal line VL1h through CP8) (See also paragraph [0105]), an extension direction of the third extension portion is different from an extension direction of the first extension portion (See annotated FIG. 3B below: an extension direction of “3” is different from an extension direction of “1”), the second extension portion is configured to connect the first extension portion with the third extension portion, and an extension direction of the second extension portion deviates from the second direction (See annotated FIG. 3B below: “2” is configured to connect “1” with “3”, and an extension direction of “2” deviates from DR1).
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Regarding Claim 17, Lee in view of Jang teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 16, wherein a projection of the first extension portion on the base substrate has an overlapped region with projections of the reset signal line, the first initialization signal line and the second initialization signal line on the base substrate (See annotated FIG. 3B below: a projection of “1” on the base substrate has an overlapped region with projections of GBL_i, VL1h and VL2h on the base substrate).
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Regarding Claim 18, Lee in view of Jang teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 17, wherein the first extension portion is connected with a first pole of a first transistor through a via hole (CP5) (See FIG. 3A and annotated FIG. 3B below: “1” is connected with a first pole of a first transistor through CP5) (See also paragraph [0104]).
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Regarding Claim 19, Lee in view of Jang teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 16, wherein,
the second extension portion and the first extension portion form an angle greater than 90° and less than 180° (See annotated FIG. 3B below: “2” and “1” form an angle greater than 90° and less than 180°); and
the third extension portion and the second extension portion form an angle greater than 90° and less than 180° (See annotated FIG. 3B below: “3” and “2” form an angle greater than 90° and less than 180°).
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Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and Jang in view of Kim et al. (US 20210272985 A1; Cited in Applicant’s IDS dated 12/28/2022), hereinafter Kim.
Regarding Claim 3, Lee teaches:
The display substrate according to claim 2, wherein in the second direction, a width of the first initialization signal line is different from a width of the second initialization signal line (See annotated FIG. 3B below: in DR1, a width of the first initialization signal line (labeled “1”) is different from a width of the second initialization signal line (labeled “2”));
wherein in the second direction, the width of the second initialization signal line is greater than the width of the first initialization signal line (See annotated FIG. 3B below: in DR1, the width of the second initialization signal line (labeled “2”) is greater than the width of the first initialization signal line (labeled “1”)).
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Lee does not explicitly teach:
wherein in the second direction, the width of the second initialization signal line is 1.3-2.4 times the width of the first initialization signal line.
However, in the same field of endeavor, display devices (Kim, paragraph [0002]), Kim teaches:
in a second direction, a width of a second initialization signal line (FIG. 3: 128) is 1.3-2.4 times a width of a first initialization signal line (FIG. 3: 127) (See annotated FIG. 11 below: a width of 128 (labeled “2”) is 1.3-2.4 times a width of the 127 (labeled “1”)).
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Lee contained a device which differed from the claimed device by the substitution of in the second direction, the width of the second initialization signal line is greater than the width of the first initialization signal line, but not explicitly 1.3-2.4 times the width of the first initialization signal line. Kim teaches the substituted element of the width of the second initialization signal line is 1.3-2.4 times the width of the first initialization signal line. Their functions were known in the art to provide initialization voltages to the pixels. The widths of the first and second initialization signal lines taught by Lee could have been substituted with the widths of the first and second initialization signal lines as taught by Kim and the results would have been predictable and resulted in arranging the first and second initialization lines so the widths differ by a particular amount.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claims 7-13, 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Jang in view of Li et al. (US 20210384289 A1; Cited in Applicant’s IDS dated 12/28/2022), hereinafter Li.
Regarding Claim 7, Lee teaches:
The display substrate according to claim 6, wherein in the second direction, the reset signal line and the second initialization signal line are arranged in sequence in a direction away from the driving transistor of the mth row of sub-pixels (See annotated FIG. 3A below: in DR1, GIL_i, and the second initialization line are arranged in sequence in a direction away from the driving transistor of the ith row of sub-pixels).
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Lee does not explicitly teach (see elements emphasized in italics):
wherein in the second direction, the reset signal line, the second initialization signal line, and the first initialization signal line are arranged in sequence in a direction away from the driving transistor of the mth row of sub-pixels.
However, in the same field of endeavor, display devices (Li, paragraph [0002]), Li teaches:
In a second direction, a second initialization signal line (R2), and a first initialization signal line (R1) are arranged in sequence in a direction away from a driving transistor (FIG. 1: Tm) of an mth row of sub-pixels (See FIG. 3: in a vertical direction, R2 and R1 are arranged in sequence in a direction away from a driving transistor of an mth row of sub-pixels).
Lee contained a device which differed from the claimed device by the substitution of the second direction, the reset signal line and the second initialization signal line are arranged in sequence in a direction away from the driving transistor of the mth row of sub-pixels, but not explicitly the second direction, the reset signal line, the second initialization signal line, and the first initialization signal line are arranged in sequence in a direction away from the driving transistor of the mth row of sub-pixels. Li teaches the substituted element of the second initialization signal line, and the first initialization signal line are arranged in sequence in a direction away from the driving transistor of the mth row of sub-pixels. Their functions were known in the art to provide the first and second initialization signal lines in proximity to the pixel circuits. The relative position of the first and second initialization signal lines taught by Lee could have been substituted with the relative position of the first and second initialization signal lines, as taught by Li and the results would have been predictable and resulted in swapping the positions of VL1h and VL2h in FIG. 3A of Lee, such that the reset signal line, the second initialization signal line, and the first initialization signal line are arranged in sequence in a direction away from the driving transistor of the mth row of sub-pixels.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding Claim 8, Lee teaches:
The display substrate according to claim 1, wherein in a direction perpendicular to the display substrate, a driving circuit layer of each of the plurality of sub-pixels comprises a semiconductor layer (See paragraph [0167] and FIG. 5: the active areas), a first conductive layer (See paragraph [0172] and FIG. 5: conductive layer arranged on the first gate insulating layer 213), a second conductive layer (See paragraph [0207] and FIG. 7: conductive layer arranged on the second gate insulating layer 215), a third conductive layer (See paragraph [0177] and FIG. 5: conductive layer arranged on the interlayer insulating layer 217) and a fourth conductive layer disposed on the base substrate in sequence (See paragraph [0181] and FIG. 5: a conductive layer arranged on 219); and
the semiconductor layer comprises an active layer of the plurality of transistors, and the active layer comprises channel regions and source-drain regions of the plurality of transistors (See paragraph [0170]);
the first conductive layer comprises control electrodes of the plurality of transistors (See paragraph [0172]); the second conductive layer comprises the first initialization signal line and the second initialization signal line (See paragraph [0207] and FIG. 7: the second conductive layer comprises VL1h and VL2h); and the third conductive layer comprises a first power supply line (See paragraph [0178] and FIG. 7: the third conductive layer comprises PLv1 and PLv2).
Lee does not explicitly teach:
the first conductive layer comprises a reset signal line; and the fourth conductive layer comprises a second power supply line and a data signal line.
However, in the same field of endeavor, display devices (Li, paragraph [0002]), Li teaches:
A first conductive layer comprises a reset signal line (See FIG. 1: S1) (See paragraph [0091] and FIG. 13: S1 is located in the first metal layer M1); and a fourth conductive layer comprises a second power supply line and a data signal line (See paragraph [0091] and FIG. 13: P and D are located in the third metal layer M3).
Lee contained a device which differed from the claimed device by the substitution of the first and further conductive layer, but not explicitly including a reset signal line and a second power supply line and a data signal line, respectively. Li teaches the substituted element of the first conductive layer comprises a reset signal line; and the fourth conductive layer comprises a second power supply line and a data signal line. Their functions were known in the art to provide conductive layers including the components of a pixel circuit. The first and fourth conductive layers taught by Lee could have been substituted with the first and fourth conductive layers including the claimed elements, as taught by Li and the results would have been predictable and resulted in including a reset signal line (GIL_i or GBL_i in FIG. 3A of Lee) in the first conductive layer and including a second power supply line (PLv1/PLv2 in FIG. 3A of Lee) and a data signal line (DL in FIG. 3A of Lee).
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding Claim 9, Lee in view of Li teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 8, further comprising: wherein the third initialization signal line and the first initialization signal line are disposed in different layers (See FIG. 7: VL1v and VL1h are disposed in different layers), and the third initialization signal line is electrically connected with the first initialization signal line or the second initialization signal line (See FIG. 7 and paragraph [0204]: VL1v is electrically connected with VL1h via CNT8).
Regarding Claim 10, Lee in view of Li teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 9, wherein the third conductive layer further comprises the third initialization signal line (See FIG. 7: the third conductive layer arranged on 217 further comprises VL1v).
Regarding Claim 11, Lee in view of Li teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 9, wherein the third initialization signal line and the first initialization signal line are electrically connected and distributed in a mesh shape (See FIG. 3A: VL1v and VL1h are electrically connected and distributed in a mesh shape).
Regarding Claim 12, Lee in view of Li teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 11, wherein at least one column of sub-pixels is arranged between adjacent third initialization signal lines (See FIG. 3A: at least one column of sub-pixels is arranged between adjacent third initialization signal lines VL1v).
Regarding Claim 13, Lee in view of Li teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 12, wherein the at least two first power supply lines are disposed between the adjacent third initialization signal lines (See FIG. 3A: at least two first power supply lines PLv1 and PLv2 are disposed between the adjacent third initialization signal lines VL1v).
Regarding Claim 20, Lee in view of Li teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 8, wherein the plurality of transistors further comprise: a second transistor (T3a/T3b), a first pole of the second transistor is electrically connected with a second pole of the driving transistor, and a second pole of the second transistor is electrically connected with the control electrode of the driving transistor (See FIG. 3A: a source of T3a/T3b is electrically connected with a drain of T1, and a drain of T3a/T3b is electrically connected with a gate of T1); and
the second conductive layer further comprises a shielding portion (Esh) electrically connected with the first power supply line (See paragraph [0128]), a projection of the shielding portion on the base substrate covers at least part of a source-drain region of the second transistor, and the projection of the shielding portion on the base substrate and a projection of the data signal line on the base substrate are located between projections of adjacent data signal lines on the base substrate (See FIG. 3B: a projection of Esh on the base substrate covers at least part of a source-drain region of T3a/T3b, and the projection of Esh on the base substrate and a projection of the DL_j on the base substrate are located between projections of adjacent data signal lines DL_j-1 and DL_j+1 on the base substrate).
Regarding Claim 21, Lee in view of Li teaches all of the elements of the claimed invention, as stated above. Furthermore, Lee teaches:
The display substrate according to claim 8, wherein the third conductive layer further comprises a fourth connection portion (See annotated FIG. 3B below: the portion of PLv1 overlapping Aca) and a fifth connection portion (See annotated FIG. 3B below: the portion of PLv1 overlapping PLh), the fourth conductive layer further comprises a seventh connection portion (See annotated FIG. 3B below, showing the seventh connection portion (the outlined portion of CP16)), the seventh connection portion is electrically connected with the fourth connection portion and the fifth connection portion (See FIG. 3A: the seventh connection portion (corresponding to CP16) is electrically connected with the fourth connection portion (corresponding to CP1) and the fifth connection portion (corresponding to CP10) via the transistors T5, T1 and T6), and the fourth connection portion and the fifth connection portion are different in shape (See annotated FIG. 3B below: the fourth connection portion and the fifth connection portion are different in shape).
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Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3, 6-13, and 15-22 have been considered but are moot in view of the new ground(s) of rejection.
On pages 11-12 of the Applicant’s Remarks, the Applicant argues that Lee does not teach the amended limitation. Examiner notes that the new claim elements are now addressed in the new claim rejection. Please see above for full basis of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2014/0299843 A1 to Kim teaches a display panel with two symmetrical adjacent pixels sharing an initialization voltage line VL that is arranged along a row line.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARURAT SUTEERAWONGSA whose telephone number is (571)270-7361. The examiner can normally be reached Monday thru Thursday, 8:30AM to 6:00PM, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lun Yi Lao can be reached at 571-272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JARURAT SUTEERAWONGSA/Examiner, Art Unit 2621
/LUNYI LAO/Supervisory Patent Examiner, Art Unit 2621