DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 2 and 4-22 have been considered but are moot because the examiner has cited Wang et al. (US PG Pub 2021/0408768) to teach the amended limitations of claims 1, 13 and 15.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 5, 8-11 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Seurin et al. (US PG Pub 2014/0218898) in view of Wang et al. (US PG Pub 2021/0408768).
Regarding claim 1, Seurin et al. disclose: an optoelectronic semiconductor chip (Figs. 7a, 7b or 7c, [0083], [0085]) comprising a semiconductor body (700) including a plurality of active regions (each VCSEL in array chip section 700 has active region 104 as seen in Fig. 1a) configured to generate electromagnetic radiation (Fig. 1a, [0052], [0053]), the plurality of active regions being arranged in a horizontal plane (Figs. 7a, 7b or 7c, [0083], [0085]); a conductive member (714) configured to electrically connect at least two adjacent ones of the active regions with each other, the conductive member being arranged over a first main surface of the semiconductor body (upper surface of semiconductor body 700) (Figs. 7a, 7b or 7c, [0083], [0085]); a contact element (422) extending from the first main surface to a second main surface of the semiconductor body and being electrically connected to at least one of the active regions via a contact material (407) over the first main surface (array chip section 700 of device of Fig. 7a is the same as section 400 of Fig. 4a or 4b) (Fig. 4a or 4b, [0071]-[0073]); and an optical element (716 or 726) arranged over the first main surface of the semiconductor body, the optical element being arranged over the first main surface of the semiconductor body so that a gap (gap formed by transparent carrier substrate 711) is formed between the optical element and the conductive member (Figs. 7b or 7c, [0085], [0086]).
Seurin et al. do not disclose: and being separated by isolation trenches, respectively.
Wang et al. disclose: VCSEL devices separated by isolation trenches (Fig. 1, [0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Seurin by forming isolation trenches between each active region in order to improve current confinement for each VCSEL device.
Regarding claim 2, Seurin et al. disclose: wherein the optical element comprises a lens (716 or 726) attached to a carrier (711) (Figs. 7b or 7c, [0085], [0086]).
Regarding claim 5, Seurin et al. disclose: wherein the lens is arranged on a side of the optical element remote from the semiconductor body (Figs. 7b or 7c, [0085], [0086]).
Regarding claim 8, Seurin et al. disclose: comprising a plurality of laser diodes, at least some of the active regions forming part of the laser diodes (each VCSEL in array chip section 700 has active region 104 as seen in Fig. 1a) (Fig. 1a, [0052], [0053]).
Regarding claim 9, Seurin et al. disclose: wherein the laser diodes are vertical-cavity surface-emitting lasers (Fig. 1a, [0051]-[0053]).
Regarding claim 10, Seurin et al. disclose: wherein the semiconductor body comprises a semiconductor substrate (101) and epitaxially grown semiconductor layers over the semiconductor substrate (Fig. 1a, [0051]-[0053], [0094]), the epitaxially grown semiconductor layers comprising a first semiconductor layer of a first conductivity type (103 or 106) and a second semiconductor layer of a second conductivity type (the other of 103 or 106), the active region (104) forming part of the epitaxially grown semiconductor layers and being arranged between the first semiconductor layer and the second semiconductor layer (quantum well p-n junction, layers above and below active region must be p or n or vice versa) (Fig. 1a, [0051]-[0053]).
Regarding claim 11, Seurin et al. disclose: further comprising a first contact portion (102 or 107) electrically connected to the first semiconductor layer (103 or 106) and a second contact portion (the other of 102 or 107) electrically connected to the second semiconductor layer (the other of 103 or 106), the first and the second contact portions being arranged adjacent to a second main surface of the semiconductor substrate (Fig. 1a, [0051]-[0053]).
Regarding claim 13, Seurin et al. disclose: an electronic device comprising an optoelectronic semiconductor chip (Figs. 7a, 7b or 7c, [0083], [0085]) comprising: a semiconductor body (700) including a plurality of active regions (each VCSEL in array chip section 700 has active region 104 as seen in Fig. 1a) configured to generate electromagnetic radiation (Fig. 1a, [0052], [0053]), the plurality of active regions being arranged in a horizontal plane (Figs. 7a, 7b or 7c, [0083], [0085]); a conductive member (714) configured to electrically connect at least two adjacent ones of the active regions with each other, the conductive member being arranged over a first main surface of the semiconductor body (upper surface of semiconductor body 700) (Figs. 7a, 7b or 7c, [0083], [0085]); a contact element (422) extending from the first main surface to a second main surface of the semiconductor body and being electrically connected to at least one of the active regions via a contact material (407) over the first main surface (array chip section 700 of device of Fig. 7a is the same as section 400 of Fig. 4a or 4b) (Fig. 4a or 4b, [0071]-[0073]); and an optical element (716 or 726) arranged over the first main surface of the semiconductor body, the optical element being arranged over the first main surface of the semiconductor body so that a gap (gap formed by transparent carrier substrate 711) is formed between the optical element and the conductive member (Figs. 7b or 7c, [0085], [0086]).
Seurin et al. do not disclose: and being separated by isolation trenches, respectively.
Wang et al. disclose: VCSEL devices separated by isolation trenches (Fig. 1, [0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Seurin by forming isolation trenches between each active region in order to improve current confinement for each VCSEL device.
Regarding claim 14, Seurin et al. disclose: wherein the electronic device is selected from the group comprising a time-of-flight sensor, a mobile phone, a smartphone, a tablet, a computer, a laptop, a vacuum cleaner or another home appliance, sanitary or other facilities ([0136]).
Regarding claim 15, Seurin et al. disclose: a method of manufacturing an optoelectronic semiconductor chip, comprising: forming a wafer comprising a semiconductor body including forming a plurality of active regions in a horizontal plane ([0094]), the active regions being configured to generate electromagnetic radiation; forming a conductive member over a first main surface of the semiconductor body, the conductive member being configured to electrically connect at least two adjacent ones of the active regions with each other; forming an optical element over the first main surface of the semiconductor body the optical element being formed over the first main surface of the semiconductor body so that a gap is formed between the optical element and the conductive member; forming a contact element extending from the first main surface to a second main surface of the semiconductor body, and electrically connecting the contact element with a contact material over the first main surface (the apparatus of claim 1 discloses the claimed method, see the rejection of claim 1).
Seurin et al. do not disclose: wherein forming a plurality of active regions comprises forming a plurality of isolation trenches, respectively.
Wang et al. disclose: VCSEL devices separated by isolation trenches (Fig. 1, [0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Seurin by forming isolation trenches between each active region in order to improve current confinement for each VCSEL device.
Regarding claim 16, Seurin et al. disclose: further comprising dicing the wafer into single chips after electrically connecting the contact element with a contact material over the first main surface ([0095], [0106]).
Regarding claim 17, Seurin et al. disclose: wherein forming the optical element over the first main surface of the semiconductor body comprises attaching a carrier to the semiconductor body (wafer bonded to a transparent carrier substrate) ([0094], [0095]).
Regarding claim 18, Seurin et al. disclose: wherein attaching is performed before forming the contact element (non-emission side contact may be made before or after the bonding of the array module with the carrier substrate) ([0095]).
Regarding claim 19, Seurin et al. disclose: wherein the carrier comprises a lens (Figs. 7b or 7c, [0085], [0086], [0094], [0095]).
Regarding claim 20, Seurin as modified do not disclose: further comprising attaching a lens to the carrier after forming the contact element and before dicing the wafer into single chips.
However, In accordance with MPEP 2144.04 [R-6], Legal Precedent as Source of Supporting Rationale: As discussed in MPEP § 2144, if the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below. If the applicant has demonstrated the criticality of a specific limitation, it would not be appropriate to rely solely on case law as the rationale to support an obviousness rejection.
MPEP 2144.04 [R-6] V D, Making Adjustable: In re Stevens , 212 F.2d 197, 101 USPQ 284 (CCPA 1954) (Claims were directed to a handle for a fishing rod wherein the handle has a longitudinally adjustable finger hook, and the hand grip of the handle connects with the body portion by means of a universal joint. The court held that adjustability, where needed, is not a patentable advance, and because there was an art-recognized need for adjustment in a fishing rod, the substitution of a universal joint for the single pivot of the prior art would have been obvious.). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to attach a lens to the carrier after forming the contact element and before dicing the wafer because adjustability where needed is not a patentable advance.
Claims 4, 6, 7, 12, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Seurin et al. (US PG Pub 2014/0218898) in view of Wang et al. (US PG Pub 2021/0408768) and Adachi et al. (US PG Pub 2016/0043528).
Regarding claim 4, Seurin as modified do not disclose: wherein the lens is arranged on a side of the optical element facing the semiconductor body.
Adachi et al. disclose: microlens array (22) is arranged on a side of the optical element facing the semiconductor body (Fig. 1, [0046]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Seurin as modified by forming the lens on a side of the optical element facing the semiconductor body because the substitution of one known element for another yields predictable results to one of ordinary skill in the art. In the instant case, the predictable result is a semiconductor chip comprising an array of VCSELs emitting coherent light that is coupled into a microlens array.
Regarding claim 6, Seurin as modified do not disclose: wherein the carrier forms part of a housing of the optoelectronic semiconductor chip.
Adachi et al. disclose: the carrier (21) forms part of a housing of the optoelectronic semiconductor chip (Fig. 1, [0046]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Seurin as modified by forming the microlens array 22 and carrier 21 above the semiconductor body as disclosed by Adachi because the substitution of one known element for another yields predictable results to one of ordinary skill in the art. In the instant case, the predictable result is a semiconductor chip comprising an array of VCSELs emitting coherent light that is coupled into a microlens array.
Regarding claim 7, Seurin as modified do not disclose: further comprising a spacer material, the spacer material being arranged over portions of the first main surface of the semiconductor body, further portions of the first main surface of the semiconductor body being uncovered with the spacer material, the optical element being attached to the first main surface of the semiconductor body via the spacer material.
Adachi et al. disclose: a spacer material (23, 30), the spacer material being arranged over portions of the first main surface of the semiconductor body, further portions of the first main surface of the semiconductor body being uncovered with the spacer material, the optical element (micro-lens) being attached to the first main surface of the semiconductor body via the spacer material (Fig. 1, [0036], [0046], [0047]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Seurin as modified by forming the microlens array 22 and carrier 21 above the semiconductor body as disclosed by Adachi (using spacer material 23 and 30) because the substitution of one known element for another yields predictable results to one of ordinary skill in the art. In the instant case, the predictable result is a semiconductor chip comprising an array of VCSELs emitting coherent light that is coupled into a microlens array.
Regarding claim 12, Seurin as modified do not disclose: wherein the second main surface of the semiconductor substrate forms part of a housing of the optoelectronic semiconductor chip.
Adachi et al. disclose: the carrier (21) forms part of a housing of the optoelectronic semiconductor chip (Fig. 1, [0046]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Seurin as modified by forming the microlens array 22 and carrier 21 above the semiconductor body as disclosed by Adachi because the substitution of one known element for another yields predictable results to one of ordinary skill in the art. In the instant case, the predictable result is a semiconductor chip comprising an array of VCSELs emitting coherent light that is coupled into a microlens array. The device as modified disclose: wherein the second main surface (bottom surface) of the semiconductor substrate forms part of a housing of the optoelectronic semiconductor chip
Regarding claim 21, Seurin as modified do not disclose: wherein attaching the carrier to the semiconductor body comprises: forming a spacer material over portions of the first main surface and leaving further portions of the first main surface uncovered; and attaching the carrier to the spacer material.
Adachi et al. disclose: a spacer material (23, 30), the spacer material being arranged over portions of the first main surface of the semiconductor body, further portions of the first main surface of the semiconductor body being uncovered with the spacer material, the optical element (micro-lens) being attached to the first main surface of the semiconductor body via the spacer material (Fig. 1, [0036], [0046], [0047]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Seurin as modified by forming the microlens array 22 and carrier 21 above the semiconductor body as disclosed by Adachi (using spacer material 23 and 30) because the substitution of one known element for another yields predictable results to one of ordinary skill in the art. In the instant case, the predictable result is a semiconductor chip comprising an array of VCSELs emitting coherent light that is coupled into a microlens array.
Regarding claim 22, Seurin as modified do not disclose: wherein a thickness of the spacer material is larger than 5 μm.
However, In accordance with MPEP 2144.05 II, Optimization of Ranges: Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In the prior art the general conditions are disclosed, an optoelectronic semiconductor chip comprising spacer material having a thickness. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to obtain a workable range of values for the thickness of the spacer material by routine experimentation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XINNING(TOM) NIU whose telephone number is (571)270-1437. The examiner can normally be reached M-F: 9:30am-6:00pm.
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/XINNING(Tom) NIU/Primary Examiner, Art Unit 2828