DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-19, 22 and 24 are rejected under 35 U.S.C. 102(b)(1) as being anticipated by Mizukami et al. [US 2006/0011973 A1], “Mizukami”.
Regarding claim 13, Mizukami discloses a vertical field effect transistor (Fig. 25, 48 and 51E specifically also Fig. 6 for easier reference identification), comprising:
a drift area (Fig. 48/51E, 10) having a first conductivity type (n-type);
a semiconductor fin (region between gate structure, 10C) on or above the drift area (10);
a first source/drain electrode (6/14) directly above the drift area (10) (as shown);
a second source/drain electrode (D/3/4) below the drift area (as shown in Fig. 51E); and
a shielding structure (11), which is situated laterally adjacent to at least one side wall of the semiconductor fin (10C) in the drift area (10), the shielding structure having a second conductivity type (¶[0076] teaches p-type), which differs from the first conductivity type (n-type);
wherein the semiconductor fin (10C) is electrically conductively connected to the first source/drain electrode (6/14), wherein the shielding structure (as shown in Fig. 51E) is positioned between the drift area (10) and the second source/drain electrode (D/3/4)
wherein the shielding structure is electrically conductively connected to both the semiconductor fin and the drift area (¶[0141] teaches holes discharged from the p-type layer of the first field relaxation layer (11) can more easily flow to the source electrode and the source electrode is electrically connected to the semiconductor fin and drift area (see Fig. 51E)).
Regarding claim 14, Mizukami discloses claim 13, Mizukami further disclose the first source/drain electrode (6/14) is formed laterally adjacent to at least one side wall of the semiconductor fin and is electrically conductively connected to the shielding structure (as shown in Fig. 51E, the source/drain electrode is electrically connected to the shielding structure through the fin, The Examiner notes if there is a different configuration required, a new matter rejection may be applicable ).
Regarding claim 15, Mizukami discloses claim 13, Mizukami further disclose a gate electrode (Fig. 51E, G/5), which is formed adjacent to the at least one side wall of the semiconductor fin (10c).
Regarding claim 16, Mizukami discloses claim 13, Mizukami further disclose the drift area (Fig. 51E, 10) is n- conductive (n-type), and the shielding structure (11) includes at least one p-conductive area (p-type) (also see Fig. 6 for conductive type).
Regarding claim 17, Mizukami discloses claim 13, Mizukami further disclose the shielding structure (Fig. 51E, 11) includes an area situated in the drift area (10), which extends laterally in a direction of the semiconductor fin (10c) –( the region (11) extends from left to right laterally in the direction of the fin).
Regarding claim 18, Mizukami discloses claim 13, Mizukami further disclose the shielding structure (Fig. 51E, 11) is completely enclosed (as shown) by the drift area (10).
Regarding claim 19, Mizukami discloses claim 13, Mizukami further the shielding structure (Fig. 51E, 11) includes at least one area that extends to a surface of the drift area (as shown).
Regarding claim 22, Mizukami discloses claim 13, Mizukami further disclose at least one additional area (Fig. 51E, 12), which has the first conductivity type (n-type and ¶[0076] teaches region 12 is n-type) and is formed laterally adjacent (as shown) to the shielding structure (11).
Regarding claim 24, Mizukami discloses a method for forming a vertical field effect transistor (Fig. 25, 48 and 51E specifically also Fig. 6 for easier reference identification), ¶[0093]), the method comprising the following steps:
forming a drift area (Fig. 48/51E, 10) having a first conductivity type (n-type);
forming a semiconductor fin (region between gate structure, 10C) on or above the drift area,
a first source/drain electrode (6/14) being formed on or directly above the drift area laterally adjacent to at least one side wall of the semiconductor fin (as shown), and
a second source/drain electrode (D/3/4) below the drift area (as shown); and
forming a shielding structure (11), which is situated laterally adjacent to the at least one side wall of the semiconductor fin in the drift area (as shown), the shielding structure having a second conductivity type (¶[0076] teaches p-type), which differs from the first conductivity type (n-type), and the semiconductor fin (10C) being electrically conductively connected to the source/drain electrode (6/14),
wherein the shielding structure (11, as shown in Fig. 51E) is above positioned between the drift area (10) and the second source/drain electrode (D/3/4),
wherein the shielding structure is electrically conductively connected to both the semiconductor fin and the drift area (¶[0141] teaches holes discharged from the p-type layer of the first field relaxation layer (11) can more easily flow to the source electrode and the source electrode is electrically connected to the semiconductor fin and drift area (see Fig. 51E).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Mizukami et al. [US 2006/0011973 A1], “Mizukami”.
Regarding claim 20, Mizukami discloses claim 13, Mizukami further disclose the shielding structure (using Fig. 51E) includes at least one first shielding structure (SS1) and one second shielding structure (SS2), which are directly adjacent (as shown). In the embodiment of Fig. 51E, the at least one second semiconductor fin is formed laterally adjacent to the semiconductor fin on or above the drift area, the semiconductor fin and the at least one second semiconductor fin being situated laterally between the first shielding structure and the second shielding structure.
However, Mizukami discloses wherein at least one second semiconductor fin (Fig. 25 (annotated below), F2) is formed laterally adjacent to the semiconductor fin (F1) on or above the drift area, the semiconductor fin and the at least one second semiconductor fin being situated laterally between the first shielding structure and the second shielding structure (as shown below).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the fin structures of embodiment of Fig. 25 with the modification of Fig. 51E such that the at least one second semiconductor fin is formed laterally adjacent to the semiconductor fin on or above the drift area, the semiconductor fin and the at least one second semiconductor fin being situated laterally between the first shielding structure and the second shielding structure because the combination would result in the device for the control of the turn-off speed and on-resistance to be optimized (¶[0157] and ¶[0160]).
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Regarding claim 23, Mizukami discloses the vertical field effect transistor (Fig. 25-31 is the semiconductor (see 25 above), Fig. 48 and 51E are segments of the semiconductor device specifically also Fig. 6 for easier reference identification), comprising:
a drift area (Fig. 31/51E, 10) having a first conductivity type (n-type);
a first semiconductor fin (F1 ) on or above the drift area (10) and a second semiconductor fin (F2), which is situated laterally adjacent to the first semiconductor fin on or above the drift area (as shown in Fig. 31);
a first source/drain electrode (16, source electrode) formed directly above the drift area laterally adjacent to at least one side wall of the first semiconductor fin (as shown);
a second source/drain electrode (4, drain electrode) below the drift area (as shown); and
a shielding structure (11 – see Fig. 6 for details), which is formed laterally adjacent to the at least one side wall of the first semiconductor fin, and the shielding structure having a second conductivity type (¶[0076] teaches p-type), which differs from the first conductivity type (n-type), and the first semiconductor fin being electrically conductively connected to the source/drain electrode (see Fig. 6 for closer details),
wherein the shielding structure is electrically conductively connected to both the semiconductor fin and the drift area (¶[0141] teaches holes discharged from the p-type layer of the first field relaxation layer (11) can more easily flow to the source electrode and the source electrode is electrically connected to the semiconductor fin and drift area (see Fig. 51E).
In the embodiment of Fig. 31, Mizukami does not disclose the shielding structure is positioned between the drift area and the second source/drain electrode.
However, in an alternative embodiment, Mizukami disclose a vertical field effect transistor (Fig. 48 – 51E) wherein the shielding structure (Fig. 48, 11) is completely enclosed by the drift area (10). The shielding structure (11) is separated from the gate structure.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a suitable alternative arrangement wherein the shielding structure is positioned between the drift area and the second source/drain electrode as taught in embodiment of Fig. 51E in the embodiment of Fig. 6 of Mizukami because such a modification would allow for the control of the turn-off speed and on-resistance to be optimized (¶[0157] and ¶[0160]).
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Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Mizukami et al. [US 2006/0011973 A1], “Mizukami” as applied to claim 13 and further in view of Sakai et al [US 2019/0198663 A1], “Sakai”.
Regarding claim 21, Mizukami disclose claim 13, Mizukami does not disclose the shielding structure includes at least one first shielding structure and one second shielding structure, the first shielding structure extending vertically further into the drift area in relation to the semiconductor fin or being spaced apart vertically farther from the semiconductor fin, than the second shielding structure.
However, Sakai discloses a semiconductor device with the drift layer (Fig. 28, DR) includes an n-type semiconductor region. Within the drift layer (DR), p-type semiconductor regions (PRS, PRT) serving as buried layers are arranged within the drift region. The p-type semiconductor regions (PRS, PRT, electric field relaxing layer) have varying depth wherein regions (PRT) is deeper within the drift region than region (PRS). Providing the p-type semiconductor regions (PRS, PRT) at varying depth makes it possible to increase the breakdown voltage of the gate insulating film (GI) (¶0073]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to vary the locations of the shielding regions within the drift layer as taught in Sakai in the device of Mizukami such that the shielding structure includes at least one first shielding structure and one second shielding structure, the first shielding structure extending vertically further into the drift area in relation to the semiconductor fin or being spaced apart vertically farther from the semiconductor fin, than the second shielding structure because such a modification would increase the breakdown voltage of the gate insulating film (GI) (¶0073] of Sakai).
Response to Arguments
Applicant's arguments filed 01/16/2026 have been fully considered but they are not persuasive. The applicant has argued the current prior art does not disclose, “the shielding structure is electrically conductively connected to both the semiconductor fin and the drift area,” see remarks on pages 6-7.
The Examiner respectfully disagrees. Mizukami discloses holes discharged from the p-type layer of the first field relaxation layer (11) can more easily flow to the source electrode and the source electrode is electrically connected to the semiconductor fin and drift area (see Fig. 51E) (¶[0141]). As such the rejection under 35 U.S.C. 102/103 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Deng et al. [US 2020/0020798 A1] discloses a semiconductor region with a fin structure. Deng does not disclose the source/drain electrode is formed laterally adjacent to at least one side wall of the semiconductor fin and is electrically conductively connected to the shielding structure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/P.M.R/Examiner, Art Unit 2897 /MARK W TORNOW/Primary Examiner, Art Unit 2891